1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 *
5 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/power_supply.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/usb/of.h>
31 #include <linux/usb/otg.h>
32 #include <linux/wakelock.h>
33
34 #define BIT_WRITEABLE_SHIFT 16
35 #define SCHEDULE_DELAY (60 * HZ)
36 #define OTG_SCHEDULE_DELAY (1 * HZ)
37 #define BYPASS_SCHEDULE_DELAY (2 * HZ)
38 #define FILTER_COUNTER 0xF4240
39
40 struct rockchip_usb2phy;
41
42 enum rockchip_usb2phy_port_id {
43 USB2PHY_PORT_OTG,
44 USB2PHY_PORT_HOST,
45 USB2PHY_NUM_PORTS,
46 };
47
48 enum rockchip_usb2phy_host_state {
49 PHY_STATE_HS_ONLINE = 0,
50 PHY_STATE_DISCONNECT = 1,
51 PHY_STATE_CONNECT = 2,
52 PHY_STATE_FS_LS_ONLINE = 4,
53 };
54
55 /**
56 * enum usb_chg_state - Different states involved in USB charger detection.
57 * @USB_CHG_STATE_UNDEFINED: USB charger is not connected or detection
58 * process is not yet started.
59 * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact.
60 * @USB_CHG_STATE_DCD_DONE: Data pin contact is detected.
61 * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects
62 * between SDP and DCP/CDP).
63 * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
64 * between DCP and CDP).
65 * @USB_CHG_STATE_DETECTED: USB charger type is determined.
66 */
67 enum usb_chg_state {
68 USB_CHG_STATE_UNDEFINED = 0,
69 USB_CHG_STATE_WAIT_FOR_DCD,
70 USB_CHG_STATE_DCD_DONE,
71 USB_CHG_STATE_PRIMARY_DONE,
72 USB_CHG_STATE_SECONDARY_DONE,
73 USB_CHG_STATE_DETECTED,
74 };
75
76 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
77 EXTCON_USB, EXTCON_USB_HOST, EXTCON_USB_VBUS_EN, EXTCON_CHG_USB_SDP,
78 EXTCON_CHG_USB_CDP, EXTCON_CHG_USB_DCP, EXTCON_CHG_USB_SLOW, EXTCON_NONE,
79 };
80
81 struct usb2phy_reg {
82 unsigned int offset;
83 unsigned int bitend;
84 unsigned int bitstart;
85 unsigned int disable;
86 unsigned int enable;
87 };
88
89 /**
90 * struct rockchip_chg_det_reg - usb charger detect registers
91 * @cp_det: charging port detected successfully.
92 * @dcp_det: dedicated charging port detected successfully.
93 * @dp_det: assert data pin connect successfully.
94 * @idm_sink_en: open dm sink curren.
95 * @idp_sink_en: open dp sink current.
96 * @idp_src_en: open dm source current.
97 * @rdm_pdwn_en: open dm pull down resistor.
98 * @vdm_src_en: open dm voltage source.
99 * @vdp_src_en: open dp voltage source.
100 * @chg_mode: set phy in charge detection mode.
101 */
102 struct rockchip_chg_det_reg {
103 struct usb2phy_reg cp_det;
104 struct usb2phy_reg dcp_det;
105 struct usb2phy_reg dp_det;
106 struct usb2phy_reg idm_sink_en;
107 struct usb2phy_reg idp_sink_en;
108 struct usb2phy_reg idp_src_en;
109 struct usb2phy_reg rdm_pdwn_en;
110 struct usb2phy_reg vdm_src_en;
111 struct usb2phy_reg vdp_src_en;
112 struct usb2phy_reg chg_mode;
113 };
114
115 /**
116 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
117 * @phy_sus: phy suspend register.
118 * @bvalid_det_en: vbus valid rise detection enable register.
119 * @bvalid_det_st: vbus valid rise detection status register.
120 * @bvalid_det_clr: vbus valid rise detection clear register.
121 * @bvalid_grf_con: vbus valid software control.
122 * @bypass_dm_en: usb bypass uart DM enable register.
123 * @bypass_sel: usb bypass uart select register.
124 * @bypass_iomux: usb bypass uart GRF iomux register.
125 * @bypass_bc: bypass battery charging module.
126 * @bypass_otg: bypass otg module.
127 * @bypass_host: bypass host module.
128 * @disfall_en: host disconnect fall edge detection enable.
129 * @disfall_st: host disconnect fall edge detection state.
130 * @disfall_clr: host disconnect fall edge detection clear.
131 * @disrise_en: host disconnect rise edge detection enable.
132 * @disrise_st: host disconnect rise edge detection state.
133 * @disrise_clr: host disconnect rise edge detection clear.
134 * @ls_det_en: linestate detection enable register.
135 * @ls_det_st: linestate detection state register.
136 * @ls_det_clr: linestate detection clear register.
137 * @iddig_output: iddig output from grf.
138 * @iddig_en: utmi iddig select between grf and phy,
139 * 0: from phy; 1: from grf
140 * @idfall_det_en: id fall detection enable register.
141 * @idfall_det_st: id fall detection state register.
142 * @idfall_det_clr: id fall detection clear register.
143 * @idrise_det_en: id rise detection enable register.
144 * @idrise_det_st: id rise detection state register.
145 * @idrise_det_clr: id rise detection clear register.
146 * @utmi_avalid: utmi vbus avalid status register.
147 * @utmi_bvalid: utmi vbus bvalid status register.
148 * @utmi_iddig: otg port id pin status register.
149 * @utmi_ls: utmi linestate state register.
150 * @utmi_hstdet: utmi host disconnect register.
151 * @vbus_det_en: vbus detect function power down register.
152 */
153 struct rockchip_usb2phy_port_cfg {
154 struct usb2phy_reg phy_sus;
155 struct usb2phy_reg bvalid_det_en;
156 struct usb2phy_reg bvalid_det_st;
157 struct usb2phy_reg bvalid_det_clr;
158 struct usb2phy_reg bvalid_grf_con;
159 struct usb2phy_reg bypass_dm_en;
160 struct usb2phy_reg bypass_sel;
161 struct usb2phy_reg bypass_iomux;
162 struct usb2phy_reg bypass_bc;
163 struct usb2phy_reg bypass_otg;
164 struct usb2phy_reg bypass_host;
165 struct usb2phy_reg disfall_en;
166 struct usb2phy_reg disfall_st;
167 struct usb2phy_reg disfall_clr;
168 struct usb2phy_reg disrise_en;
169 struct usb2phy_reg disrise_st;
170 struct usb2phy_reg disrise_clr;
171 struct usb2phy_reg ls_det_en;
172 struct usb2phy_reg ls_det_st;
173 struct usb2phy_reg ls_det_clr;
174 struct usb2phy_reg iddig_output;
175 struct usb2phy_reg iddig_en;
176 struct usb2phy_reg idfall_det_en;
177 struct usb2phy_reg idfall_det_st;
178 struct usb2phy_reg idfall_det_clr;
179 struct usb2phy_reg idrise_det_en;
180 struct usb2phy_reg idrise_det_st;
181 struct usb2phy_reg idrise_det_clr;
182 struct usb2phy_reg utmi_avalid;
183 struct usb2phy_reg utmi_bvalid;
184 struct usb2phy_reg utmi_iddig;
185 struct usb2phy_reg utmi_ls;
186 struct usb2phy_reg utmi_hstdet;
187 struct usb2phy_reg vbus_det_en;
188 };
189
190 /**
191 * struct rockchip_usb2phy_cfg - usb-phy configuration.
192 * @reg: the address offset of grf for usb-phy config.
193 * @num_ports: specify how many ports that the phy has.
194 * @phy_tuning: phy default parameters tuning.
195 * @vbus_detect: vbus voltage level detection function.
196 * @clkout_ctl: keep on/turn off output clk of phy.
197 * @port_cfgs: usb-phy port configurations.
198 * @chg_det: charger detection registers.
199 */
200 struct rockchip_usb2phy_cfg {
201 unsigned int reg;
202 unsigned int num_ports;
203 int (*phy_tuning)(struct rockchip_usb2phy *rphy);
204 int (*vbus_detect)(struct rockchip_usb2phy *rphy, bool en);
205 struct usb2phy_reg clkout_ctl;
206 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
207 const struct rockchip_chg_det_reg chg_det;
208 };
209
210 /**
211 * struct rockchip_usb2phy_port - usb-phy port data.
212 * @phy: generic phy.
213 * @port_id: flag for otg port or host port.
214 * @low_power_en: enable enter low power when suspend.
215 * @perip_connected: flag for periphyeral connect status.
216 * @prev_iddig: previous otg port id pin status.
217 * @suspended: phy suspended flag.
218 * @typec_vbus_det: Type-C otg vbus detect.
219 * @utmi_avalid: utmi avalid status usage flag.
220 * true - use avalid to get vbus status
221 * false - use bvalid to get vbus status
222 * @vbus_attached: otg device vbus status.
223 * @vbus_always_on: otg vbus is always powered on.
224 * @vbus_enabled: vbus regulator status.
225 * @bypass_uart_en: usb bypass uart enable, passed from DT.
226 * @host_disconnect: usb host disconnect status.
227 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
228 * @ls_irq: IRQ number assigned for linestate detection.
229 * @id_irq: IRQ number assigned for id fall or rise detection.
230 * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
231 * irqs to one irq in otg-port.
232 * @mutex: for register updating in sm_work.
233 * @chg_work: charge detect work.
234 * @bypass_uart_work: usb bypass uart work.
235 * @otg_sm_work: OTG state machine work.
236 * @sm_work: HOST state machine work.
237 * @vbus: vbus regulator supply on few rockchip boards.
238 * @port_cfg: port register configuration, assigned by driver data.
239 * @event_nb: hold event notification callback.
240 * @state: define OTG enumeration states before device reset.
241 * @mode: the dr_mode of the controller.
242 */
243 struct rockchip_usb2phy_port {
244 struct phy *phy;
245 unsigned int port_id;
246 bool low_power_en;
247 bool perip_connected;
248 bool prev_iddig;
249 bool suspended;
250 bool typec_vbus_det;
251 bool utmi_avalid;
252 bool vbus_attached;
253 bool vbus_always_on;
254 bool vbus_enabled;
255 bool bypass_uart_en;
256 bool host_disconnect;
257 int bvalid_irq;
258 int ls_irq;
259 int id_irq;
260 int otg_mux_irq;
261 struct mutex mutex;
262 struct delayed_work bypass_uart_work;
263 struct delayed_work chg_work;
264 struct delayed_work otg_sm_work;
265 struct delayed_work sm_work;
266 struct regulator *vbus;
267 const struct rockchip_usb2phy_port_cfg *port_cfg;
268 struct notifier_block event_nb;
269 struct wake_lock wakelock;
270 enum usb_otg_state state;
271 enum usb_dr_mode mode;
272 };
273
274 /**
275 * struct rockchip_usb2phy - usb2.0 phy driver data.
276 * @dev: pointer to device.
277 * @grf: General Register Files regmap.
278 * @usbgrf: USB General Register Files regmap.
279 * *phy_base: the base address of USB PHY.
280 * @phy_reset: phy reset control.
281 * @clk: clock struct of phy input clk.
282 * @clk480m: clock struct of phy output clk.
283 * @clk480m_hw: clock struct of phy output clk management.
284 * @chg_state: states involved in USB charger detection.
285 * @chg_type: USB charger types.
286 * @dcd_retries: The retry count used to track Data contact
287 * detection process.
288 * @primary_retries: The retry count used for charger
289 * detection primary phase.
290 * @phy_sus_cfg: Store the phy current suspend configuration.
291 * @edev_self: represent the source of extcon.
292 * @irq: IRQ number assigned for phy which combined irqs of
293 * otg port and host port.
294 * @edev: extcon device for notification registration
295 * @phy_cfg: phy register configuration, assigned by driver data.
296 * @ports: phy port instance.
297 */
298 struct rockchip_usb2phy {
299 struct device *dev;
300 struct regmap *grf;
301 struct regmap *usbgrf;
302 void __iomem *phy_base;
303 struct reset_control *phy_reset;
304 struct clk *clk;
305 struct clk *clk480m;
306 struct clk_hw clk480m_hw;
307 enum usb_chg_state chg_state;
308 enum power_supply_type chg_type;
309 u8 dcd_retries;
310 u8 primary_retries;
311 unsigned int phy_sus_cfg;
312 bool edev_self;
313 int irq;
314 struct extcon_dev *edev;
315 const struct rockchip_usb2phy_cfg *phy_cfg;
316 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
317 };
318
get_reg_base(struct rockchip_usb2phy * rphy)319 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
320 {
321 return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
322 }
323
property_enable(struct regmap * base,const struct usb2phy_reg * reg,bool en)324 static inline int property_enable(struct regmap *base, const struct usb2phy_reg *reg, bool en)
325 {
326 unsigned int val, mask, tmp;
327
328 tmp = en ? reg->enable : reg->disable;
329 mask = GENMASK(reg->bitend, reg->bitstart);
330 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
331
332 return regmap_write(base, reg->offset, val);
333 }
334
property_enabled(struct regmap * base,const struct usb2phy_reg * reg)335 static inline bool property_enabled(struct regmap *base, const struct usb2phy_reg *reg)
336 {
337 int ret;
338 unsigned int tmp, orig;
339 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
340
341 ret = regmap_read(base, reg->offset, &orig);
342 if (ret) {
343 return false;
344 }
345
346 tmp = (orig & mask) >> reg->bitstart;
347 return tmp == reg->enable;
348 }
349
rockchip_usb2phy_reset(struct rockchip_usb2phy * rphy)350 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
351 {
352 int ret;
353
354 ret = reset_control_assert(rphy->phy_reset);
355 if (ret) {
356 return ret;
357 }
358
359 udelay(0xa);
360
361 ret = reset_control_deassert(rphy->phy_reset);
362 if (ret) {
363 return ret;
364 }
365
366 usleep_range(0x64, 0xc8);
367
368 return 0;
369 }
370
rockchip_usb2phy_clk480m_prepare(struct clk_hw * hw)371 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
372 {
373 struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw);
374 struct regmap *base = get_reg_base(rphy);
375 int ret;
376
377 /* turn on 480m clk output if it is off */
378 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
379 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
380 if (ret) {
381 return ret;
382 }
383
384 /* waiting for the clk become stable */
385 usleep_range(0x4b0, 0x514);
386 }
387
388 return 0;
389 }
390
rockchip_usb2phy_clk480m_unprepare(struct clk_hw * hw)391 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
392 {
393 struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw);
394 struct regmap *base = get_reg_base(rphy);
395
396 /* turn off 480m clk output */
397 property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
398 }
399
rockchip_usb2phy_clk480m_prepared(struct clk_hw * hw)400 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
401 {
402 struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw);
403 struct regmap *base = get_reg_base(rphy);
404
405 return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
406 }
407
rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)408 static unsigned long rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
409 {
410 return 0x1c9c3800;
411 }
412
413 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
414 .prepare = rockchip_usb2phy_clk480m_prepare,
415 .unprepare = rockchip_usb2phy_clk480m_unprepare,
416 .is_prepared = rockchip_usb2phy_clk480m_prepared,
417 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
418 };
419
rockchip_usb2phy_clk480m_unregister(void * data)420 static void rockchip_usb2phy_clk480m_unregister(void *data)
421 {
422 struct rockchip_usb2phy *rphy = data;
423
424 of_clk_del_provider(rphy->dev->of_node);
425 clk_unregister(rphy->clk480m);
426 }
427
rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy * rphy)428 static int rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
429 {
430 struct device_node *node = rphy->dev->of_node;
431 struct clk_init_data init = {};
432 const char *clk_name;
433 int ret;
434
435 init.flags = 0;
436 init.name = "clk_usbphy_480m";
437 init.ops = &rockchip_usb2phy_clkout_ops;
438
439 /* optional override of the clockname */
440 of_property_read_string(node, "clock-output-names", &init.name);
441
442 if (rphy->clk) {
443 clk_name = __clk_get_name(rphy->clk);
444 init.parent_names = &clk_name;
445 init.num_parents = 1;
446 } else {
447 init.parent_names = NULL;
448 init.num_parents = 0;
449 }
450
451 rphy->clk480m_hw.init = &init;
452
453 /* register the clock */
454 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
455 if (IS_ERR(rphy->clk480m)) {
456 ret = PTR_ERR(rphy->clk480m);
457 goto err_ret;
458 }
459
460 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
461 if (ret < 0) {
462 goto err_clk_provider;
463 }
464
465 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister, rphy);
466 if (ret < 0) {
467 goto err_unreg_action;
468 }
469
470 return 0;
471
472 err_unreg_action:
473 of_clk_del_provider(node);
474 err_clk_provider:
475 clk_unregister(rphy->clk480m);
476 err_ret:
477 return ret;
478 }
479
rockchip_usb2phy_extcon_register(struct rockchip_usb2phy * rphy)480 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
481 {
482 int ret;
483 struct device_node *node = rphy->dev->of_node;
484 struct extcon_dev *edev;
485
486 if (of_property_read_bool(node, "extcon")) {
487 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
488 if (IS_ERR(edev)) {
489 if (PTR_ERR(edev) != -EPROBE_DEFER) {
490 dev_err(rphy->dev, "Invalid or missing extcon\n");
491 }
492 return PTR_ERR(edev);
493 }
494 } else {
495 /* Initialize extcon device */
496 edev = devm_extcon_dev_allocate(rphy->dev, rockchip_usb2phy_extcon_cable);
497 if (IS_ERR(edev)) {
498 return -ENOMEM;
499 }
500
501 ret = devm_extcon_dev_register(rphy->dev, edev);
502 if (ret) {
503 dev_err(rphy->dev, "failed to register extcon device\n");
504 return ret;
505 }
506
507 rphy->edev_self = true;
508 }
509
510 rphy->edev = edev;
511
512 return 0;
513 }
514
515 /* The caller must hold rport->mutex lock */
rockchip_usb2phy_enable_id_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)516 static int rockchip_usb2phy_enable_id_irq(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport, bool en)
517 {
518 int ret;
519
520 ret = property_enable(rphy->grf, &rport->port_cfg->idfall_det_clr, true);
521 if (ret) {
522 goto out;
523 }
524
525 ret = property_enable(rphy->grf, &rport->port_cfg->idfall_det_en, en);
526 if (ret) {
527 goto out;
528 }
529
530 ret = property_enable(rphy->grf, &rport->port_cfg->idrise_det_clr, true);
531 if (ret) {
532 goto out;
533 }
534
535 ret = property_enable(rphy->grf, &rport->port_cfg->idrise_det_en, en);
536 out:
537 return ret;
538 }
539
540 /* The caller must hold rport->mutex lock */
rockchip_usb2phy_enable_vbus_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)541 static int rockchip_usb2phy_enable_vbus_irq(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport, bool en)
542 {
543 int ret;
544
545 ret = property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
546 if (ret) {
547 goto out;
548 }
549
550 ret = property_enable(rphy->grf, &rport->port_cfg->bvalid_det_en, en);
551 out:
552 return ret;
553 }
554
rockchip_usb2phy_enable_line_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)555 static int rockchip_usb2phy_enable_line_irq(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport, bool en)
556 {
557 int ret;
558
559 ret = property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
560 if (ret) {
561 goto out;
562 }
563
564 ret = property_enable(rphy->grf, &rport->port_cfg->ls_det_en, en);
565 out:
566 return ret;
567 }
568
rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)569 static int rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport,
570 bool en)
571 {
572 int ret;
573
574 ret = property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
575 if (ret) {
576 goto out;
577 }
578
579 ret = property_enable(rphy->grf, &rport->port_cfg->disfall_en, en);
580 if (ret) {
581 goto out;
582 }
583
584 ret = property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
585 if (ret) {
586 goto out;
587 }
588
589 ret = property_enable(rphy->grf, &rport->port_cfg->disrise_en, en);
590 out:
591 return ret;
592 }
593
rockchip_usb_bypass_uart(struct rockchip_usb2phy_port * rport,bool en)594 static int rockchip_usb_bypass_uart(struct rockchip_usb2phy_port *rport, bool en)
595 {
596 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
597 const struct usb2phy_reg *iomux = &rport->port_cfg->bypass_iomux;
598 struct regmap *base = get_reg_base(rphy);
599 int ret = 0;
600
601 mutex_lock(&rport->mutex);
602
603 if (en == property_enabled(base, &rport->port_cfg->bypass_sel)) {
604 dev_info(&rport->phy->dev, "bypass uart %s is already set\n", en ? "on" : "off");
605 goto unlock;
606 }
607
608 dev_info(&rport->phy->dev, "bypass uart %s\n", en ? "on" : "off");
609
610 if (en) {
611 /*
612 * To use UART function:
613 * 1. Put the USB PHY in suspend mode and opmode is normal;
614 * 2. Set bypasssel to 1'b1 and bypassdmen to 1'b1;
615 *
616 * Note: Although the datasheet requires that put USB PHY
617 * in non-driving mode to disable resistance when use USB
618 * bypass UART function, but actually we find that if we
619 * set phy in non-driving mode, it will cause UART to print
620 * random codes. So just put USB PHY in normal mode.
621 */
622 ret |= property_enable(base, &rport->port_cfg->bypass_sel, true);
623 ret |= property_enable(base, &rport->port_cfg->bypass_dm_en, true);
624
625 /* Some platforms required to set iomux of bypass uart */
626 if (iomux->offset) {
627 ret |= property_enable(rphy->grf, iomux, true);
628 }
629 } else {
630 /* just disable bypass, and resume phy in phy power_on later */
631 ret |= property_enable(base, &rport->port_cfg->bypass_sel, false);
632 ret |= property_enable(base, &rport->port_cfg->bypass_dm_en, false);
633
634 /* Some platforms required to set iomux of bypass uart */
635 if (iomux->offset) {
636 ret |= property_enable(rphy->grf, iomux, false);
637 }
638 }
639
640 unlock:
641 mutex_unlock(&rport->mutex);
642
643 return ret;
644 }
645
rockchip_usb_bypass_uart_work(struct work_struct * work)646 static void rockchip_usb_bypass_uart_work(struct work_struct *work)
647 {
648 struct rockchip_usb2phy_port *rport = container_of(work, struct rockchip_usb2phy_port, bypass_uart_work.work);
649 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
650 bool vbus, iddig;
651 int ret;
652
653 mutex_lock(&rport->mutex);
654
655 iddig = property_enabled(rphy->grf, &rport->port_cfg->utmi_iddig);
656
657 if (rport->utmi_avalid) {
658 vbus = property_enabled(rphy->grf, &rport->port_cfg->utmi_avalid);
659 } else {
660 vbus = property_enabled(rphy->grf, &rport->port_cfg->utmi_bvalid);
661 }
662
663 mutex_unlock(&rport->mutex);
664
665 /*
666 * If the vbus is low and iddig is high, it indicates that usb
667 * otg is not working, then we can enable usb to bypass uart,
668 * otherwise schedule the work until the conditions (vbus is low
669 * and iddig is high) are matched.
670 */
671 if (!vbus && iddig) {
672 ret = rockchip_usb_bypass_uart(rport, true);
673 if (ret) {
674 dev_warn(&rport->phy->dev, "failed to enable bypass uart\n");
675 }
676 } else {
677 schedule_delayed_work(&rport->bypass_uart_work, BYPASS_SCHEDULE_DELAY);
678 }
679 }
680
rockchip_usb2phy_init(struct phy * phy)681 static int rockchip_usb2phy_init(struct phy *phy)
682 {
683 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
684 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
685 int ret = 0;
686
687 mutex_lock(&rport->mutex);
688
689 if (rport->port_id == USB2PHY_PORT_OTG &&
690 (rport->mode == USB_DR_MODE_PERIPHERAL || rport->mode == USB_DR_MODE_OTG)) {
691 /* clear id status and enable id detect irq */
692 if (rport->id_irq > 0 || rport->otg_mux_irq > 0 || rphy->irq > 0) {
693 ret = rockchip_usb2phy_enable_id_irq(rphy, rport, true);
694 if (ret) {
695 dev_err(rphy->dev, "failed to enable id irq\n");
696 goto out;
697 }
698 }
699
700 /* clear bvalid status and enable bvalid detect irq */
701 if ((rport->bvalid_irq > 0 || rport->otg_mux_irq > 0 || rphy->irq > 0) && !rport->vbus_always_on) {
702 ret = rockchip_usb2phy_enable_vbus_irq(rphy, rport, true);
703 if (ret) {
704 dev_err(rphy->dev, "failed to enable bvalid irq\n");
705 goto out;
706 }
707
708 schedule_delayed_work(&rport->otg_sm_work, 0);
709 }
710 } else if (rport->port_id == USB2PHY_PORT_HOST) {
711 if (rport->port_cfg->disfall_en.offset) {
712 rport->host_disconnect = true;
713 ret = rockchip_usb2phy_enable_host_disc_irq(rphy, rport, true);
714 if (ret) {
715 dev_err(rphy->dev, "failed to enable disconnect irq\n");
716 goto out;
717 }
718 }
719
720 /* clear linestate and enable linestate detect irq */
721 ret = rockchip_usb2phy_enable_line_irq(rphy, rport, true);
722 if (ret) {
723 dev_err(rphy->dev, "failed to enable linestate irq\n");
724 goto out;
725 }
726
727 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
728 }
729
730 out:
731 mutex_unlock(&rport->mutex);
732 return ret;
733 }
734
rockchip_usb2phy_power_on(struct phy * phy)735 static int rockchip_usb2phy_power_on(struct phy *phy)
736 {
737 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
738 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
739 struct regmap *base = get_reg_base(rphy);
740 int ret;
741
742 dev_dbg(&rport->phy->dev, "port power on\n");
743
744 if (rport->bypass_uart_en) {
745 ret = rockchip_usb_bypass_uart(rport, false);
746 if (ret) {
747 dev_warn(&rport->phy->dev, "failed to disable bypass uart\n");
748 goto exit;
749 }
750 }
751
752 mutex_lock(&rport->mutex);
753
754 if (!rport->suspended) {
755 ret = 0;
756 goto unlock;
757 }
758
759 ret = clk_prepare_enable(rphy->clk480m);
760 if (ret) {
761 goto unlock;
762 }
763
764 ret = property_enable(base, &rport->port_cfg->phy_sus, false);
765 if (ret) {
766 goto unlock;
767 }
768
769 /*
770 * For rk3588, it needs to reset phy when exit from
771 * suspend mode with common_on_n 1'b1(aka REFCLK_LOGIC,
772 * Bias, and PLL blocks are powered down) for lower
773 * power consumption. If you don't want to reset phy,
774 * please keep the common_on_n 1'b0 to set these blocks
775 * remain powered.
776 */
777 ret = rockchip_usb2phy_reset(rphy);
778 if (ret) {
779 goto unlock;
780 }
781
782 /* waiting for the utmi_clk to become stable */
783 usleep_range(0x5dc, 0x7d0);
784
785 rport->suspended = false;
786
787 unlock:
788 mutex_unlock(&rport->mutex);
789
790 /* Enable bypass uart in the bypass_uart_work. */
791 if (rport->bypass_uart_en) {
792 schedule_delayed_work(&rport->bypass_uart_work, 0);
793 }
794
795 exit:
796 return ret;
797 }
798
rockchip_usb2phy_power_off(struct phy * phy)799 static int rockchip_usb2phy_power_off(struct phy *phy)
800 {
801 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
802 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
803 struct regmap *base = get_reg_base(rphy);
804 int ret;
805
806 dev_dbg(&rport->phy->dev, "port power off\n");
807
808 mutex_lock(&rport->mutex);
809
810 if (rport->suspended) {
811 ret = 0;
812 goto unlock;
813 }
814
815 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
816 if (ret) {
817 goto unlock;
818 }
819
820 rport->suspended = true;
821 clk_disable_unprepare(rphy->clk480m);
822
823 unlock:
824 mutex_unlock(&rport->mutex);
825
826 /* Enable bypass uart in the bypass_uart_work. */
827 if (rport->bypass_uart_en) {
828 schedule_delayed_work(&rport->bypass_uart_work, 0);
829 }
830
831 return ret;
832 }
833
rockchip_usb2phy_exit(struct phy * phy)834 static int rockchip_usb2phy_exit(struct phy *phy)
835 {
836 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
837
838 if (rport->port_id == USB2PHY_PORT_HOST) {
839 cancel_delayed_work_sync(&rport->sm_work);
840 } else if (rport->port_id == USB2PHY_PORT_OTG && rport->bvalid_irq > 0) {
841 flush_delayed_work(&rport->otg_sm_work);
842 }
843
844 return 0;
845 }
846
rockchip_set_vbus_power(struct rockchip_usb2phy_port * rport,bool en)847 static int rockchip_set_vbus_power(struct rockchip_usb2phy_port *rport, bool en)
848 {
849 int ret = 0;
850
851 if (!rport->vbus) {
852 return 0;
853 }
854
855 if (en && !rport->vbus_enabled) {
856 ret = regulator_enable(rport->vbus);
857 if (ret) {
858 dev_err(&rport->phy->dev, "Failed to enable VBUS supply\n");
859 }
860 } else if (!en && rport->vbus_enabled) {
861 ret = regulator_disable(rport->vbus);
862 }
863
864 if (ret == 0) {
865 rport->vbus_enabled = en;
866 }
867
868 return ret;
869 }
870
rockchip_usb2phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)871 static int rockchip_usb2phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
872 {
873 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
874 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
875 bool vbus_det_en;
876 int ret = 0;
877
878 if (rport->port_id != USB2PHY_PORT_OTG) {
879 return ret;
880 }
881
882 switch (mode) {
883 case PHY_MODE_USB_OTG:
884 /*
885 * In case of using vbus to detect connect state by u2phy,
886 * enable vbus detect on otg mode.
887 */
888 fallthrough;
889 case PHY_MODE_USB_DEVICE:
890 /* Disable VBUS supply */
891 rockchip_set_vbus_power(rport, false);
892 extcon_set_state_sync(rphy->edev, EXTCON_USB_VBUS_EN, false);
893 /* For vbus always on, set EXTCON_USB to true. */
894 extcon_set_state(rphy->edev, EXTCON_USB, true);
895 rport->perip_connected = true;
896 vbus_det_en = true;
897 break;
898 case PHY_MODE_USB_HOST:
899 /* Enable VBUS supply */
900 ret = rockchip_set_vbus_power(rport, true);
901 if (ret) {
902 dev_err(&rport->phy->dev, "Failed to set host mode\n");
903 return ret;
904 }
905
906 extcon_set_state_sync(rphy->edev, EXTCON_USB_VBUS_EN, true);
907 /* For vbus always on, deinit EXTCON_USB to false. */
908 extcon_set_state(rphy->edev, EXTCON_USB, false);
909 rport->perip_connected = false;
910 fallthrough;
911 case PHY_MODE_INVALID:
912 vbus_det_en = false;
913 break;
914 default:
915 dev_info(&rport->phy->dev, "illegal mode\n");
916 return ret;
917 }
918
919 if (rphy->phy_cfg->vbus_detect) {
920 rphy->phy_cfg->vbus_detect(rphy, vbus_det_en);
921 } else {
922 ret = property_enable(rphy->grf, &rport->port_cfg->vbus_det_en, vbus_det_en);
923 }
924
925 return ret;
926 }
927
928 static const struct phy_ops rockchip_usb2phy_ops = {
929 .init = rockchip_usb2phy_init,
930 .exit = rockchip_usb2phy_exit,
931 .power_on = rockchip_usb2phy_power_on,
932 .power_off = rockchip_usb2phy_power_off,
933 .set_mode = rockchip_usb2phy_set_mode,
934 .owner = THIS_MODULE,
935 };
936
937 /* Show & store the current value of otg mode for otg port */
otg_mode_show(struct device * device,struct device_attribute * attr,char * buf)938 static ssize_t otg_mode_show(struct device *device, struct device_attribute *attr, char *buf)
939 {
940 struct rockchip_usb2phy *rphy = dev_get_drvdata(device);
941 struct rockchip_usb2phy_port *rport = NULL;
942 unsigned int index;
943
944 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
945 rport = &rphy->ports[index];
946 if (rport->port_id == USB2PHY_PORT_OTG) {
947 break;
948 }
949 }
950
951 if (!rport) {
952 dev_err(rphy->dev, "Fail to get otg port\n");
953 return -EINVAL;
954 } else if (rport->port_id != USB2PHY_PORT_OTG) {
955 dev_err(rphy->dev, "No support otg\n");
956 return -EINVAL;
957 }
958
959 switch (rport->mode) {
960 case USB_DR_MODE_HOST:
961 return sprintf(buf, "host\n");
962 case USB_DR_MODE_PERIPHERAL:
963 return sprintf(buf, "peripheral\n");
964 case USB_DR_MODE_OTG:
965 return sprintf(buf, "otg\n");
966 case USB_DR_MODE_UNKNOWN:
967 return sprintf(buf, "UNKNOWN\n");
968 }
969
970 return -EINVAL;
971 }
972
otg_mode_store(struct device * device,struct device_attribute * attr,const char * buf,size_t count)973 static ssize_t otg_mode_store(struct device *device, struct device_attribute *attr, const char *buf, size_t count)
974 {
975 struct rockchip_usb2phy *rphy = dev_get_drvdata(device);
976 struct rockchip_usb2phy_port *rport = NULL;
977 struct regmap *base = get_reg_base(rphy);
978 enum usb_dr_mode new_dr_mode;
979 unsigned int index;
980 int rc = count;
981
982 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
983 rport = &rphy->ports[index];
984 if (rport->port_id == USB2PHY_PORT_OTG) {
985 break;
986 }
987 }
988
989 if (!rport) {
990 dev_err(rphy->dev, "Fail to get otg port\n");
991 rc = -EINVAL;
992 goto err0;
993 } else if (rport->port_id != USB2PHY_PORT_OTG || rport->mode == USB_DR_MODE_UNKNOWN) {
994 dev_err(rphy->dev, "No support otg\n");
995 rc = -EINVAL;
996 goto err0;
997 }
998
999 mutex_lock(&rport->mutex);
1000
1001 if (!strncmp(buf, "0", 1) || !strncmp(buf, "otg", 3)) {
1002 new_dr_mode = USB_DR_MODE_OTG;
1003 } else if (!strncmp(buf, "1", 1) || !strncmp(buf, "host", 4)) {
1004 new_dr_mode = USB_DR_MODE_HOST;
1005 } else if (!strncmp(buf, "2", 1) || !strncmp(buf, "peripheral", 10)) {
1006 new_dr_mode = USB_DR_MODE_PERIPHERAL;
1007 } else {
1008 dev_err(rphy->dev, "Error mode! Input 'otg' or 'host' or 'peripheral'\n");
1009 rc = -EINVAL;
1010 goto err1;
1011 }
1012
1013 if (rport->mode == new_dr_mode) {
1014 dev_warn(rphy->dev, "Same as current mode\n");
1015 goto err1;
1016 }
1017
1018 rport->mode = new_dr_mode;
1019
1020 switch (rport->mode) {
1021 case USB_DR_MODE_HOST:
1022 rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
1023 property_enable(base, &rport->port_cfg->iddig_output, false);
1024 property_enable(base, &rport->port_cfg->iddig_en, true);
1025 break;
1026 case USB_DR_MODE_PERIPHERAL:
1027 rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE, 0);
1028 property_enable(base, &rport->port_cfg->iddig_output, true);
1029 property_enable(base, &rport->port_cfg->iddig_en, true);
1030 break;
1031 case USB_DR_MODE_OTG:
1032 rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG, 0);
1033 property_enable(base, &rport->port_cfg->iddig_output, false);
1034 property_enable(base, &rport->port_cfg->iddig_en, false);
1035 break;
1036 default:
1037 break;
1038 }
1039
1040 err1:
1041 mutex_unlock(&rport->mutex);
1042
1043 err0:
1044 return rc;
1045 }
1046 static DEVICE_ATTR_RW(otg_mode);
1047
1048 /* Group all the usb2 phy attributes */
1049 static struct attribute *usb2_phy_attrs[] = {
1050 &dev_attr_otg_mode.attr,
1051 NULL,
1052 };
1053
1054 static struct attribute_group usb2_phy_attr_group = {
1055 .name = NULL, /* we want them in the same directory */
1056 .attrs = usb2_phy_attrs,
1057 };
1058
rockchip_usb2phy_otg_sm_work(struct work_struct * work)1059 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
1060 {
1061 struct rockchip_usb2phy_port *rport = container_of(work, struct rockchip_usb2phy_port, otg_sm_work.work);
1062 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1063 static unsigned int cable;
1064 unsigned long delay;
1065 bool sch_work;
1066
1067 mutex_lock(&rport->mutex);
1068
1069 if (rport->port_cfg->bvalid_grf_con.enable && rport->typec_vbus_det) {
1070 rport->vbus_attached = property_enabled(rphy->grf, &rport->port_cfg->bvalid_grf_con);
1071 } else if (rport->utmi_avalid) {
1072 rport->vbus_attached = property_enabled(rphy->grf, &rport->port_cfg->utmi_avalid);
1073 } else {
1074 rport->vbus_attached = property_enabled(rphy->grf, &rport->port_cfg->utmi_bvalid);
1075 }
1076
1077 sch_work = false;
1078 delay = OTG_SCHEDULE_DELAY;
1079
1080 dev_dbg(&rport->phy->dev, "%s otg sm work\n", usb_otg_state_string(rport->state));
1081
1082 switch (rport->state) {
1083 case OTG_STATE_UNDEFINED:
1084 rport->state = OTG_STATE_B_IDLE;
1085 if (!rport->vbus_attached) {
1086 mutex_unlock(&rport->mutex);
1087 rockchip_usb2phy_power_off(rport->phy);
1088 mutex_lock(&rport->mutex);
1089 }
1090 fallthrough;
1091 case OTG_STATE_B_IDLE:
1092 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0 ||
1093 extcon_get_state(rphy->edev, EXTCON_USB_VBUS_EN) > 0) {
1094 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
1095 rport->state = OTG_STATE_A_HOST;
1096 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1097 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1098 mutex_unlock(&rport->mutex);
1099 rockchip_usb2phy_power_on(rport->phy);
1100 return;
1101 } else if (rport->vbus_attached) {
1102 dev_dbg(&rport->phy->dev, "vbus_attach\n");
1103 switch (rphy->chg_state) {
1104 case USB_CHG_STATE_UNDEFINED:
1105 mutex_unlock(&rport->mutex);
1106 schedule_delayed_work(&rport->chg_work, 0);
1107 return;
1108 case USB_CHG_STATE_DETECTED:
1109 switch (rphy->chg_type) {
1110 case POWER_SUPPLY_TYPE_USB:
1111 dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
1112 wake_lock(&rport->wakelock);
1113 cable = EXTCON_CHG_USB_SDP;
1114 mutex_unlock(&rport->mutex);
1115 rockchip_usb2phy_power_on(rport->phy);
1116 mutex_lock(&rport->mutex);
1117 rport->state = OTG_STATE_B_PERIPHERAL;
1118 rport->perip_connected = true;
1119 sch_work = true;
1120 break;
1121 case POWER_SUPPLY_TYPE_USB_DCP:
1122 dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
1123 cable = EXTCON_CHG_USB_DCP;
1124 sch_work = true;
1125 break;
1126 case POWER_SUPPLY_TYPE_USB_CDP:
1127 dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
1128 wake_lock(&rport->wakelock);
1129 cable = EXTCON_CHG_USB_CDP;
1130 mutex_unlock(&rport->mutex);
1131 rockchip_usb2phy_power_on(rport->phy);
1132 mutex_lock(&rport->mutex);
1133 rport->state = OTG_STATE_B_PERIPHERAL;
1134 rport->perip_connected = true;
1135 sch_work = true;
1136 break;
1137 default:
1138 break;
1139 }
1140 break;
1141 default:
1142 break;
1143 }
1144 } else {
1145 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1146 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1147 mutex_unlock(&rport->mutex);
1148 rockchip_usb2phy_power_off(rport->phy);
1149 mutex_lock(&rport->mutex);
1150 }
1151 break;
1152 case OTG_STATE_B_PERIPHERAL:
1153 sch_work = true;
1154
1155 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0 ||
1156 extcon_get_state(rphy->edev, EXTCON_USB_VBUS_EN) > 0) {
1157 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
1158 rport->state = OTG_STATE_A_HOST;
1159 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1160 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1161 rport->perip_connected = false;
1162 sch_work = false;
1163 wake_unlock(&rport->wakelock);
1164 } else if (!rport->vbus_attached) {
1165 dev_dbg(&rport->phy->dev, "usb disconnect\n");
1166 rport->state = OTG_STATE_B_IDLE;
1167 rport->perip_connected = false;
1168 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1169 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1170 delay = OTG_SCHEDULE_DELAY;
1171 wake_unlock(&rport->wakelock);
1172 }
1173 sch_work = true;
1174 break;
1175 case OTG_STATE_A_HOST:
1176 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
1177 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
1178 rport->state = OTG_STATE_B_IDLE;
1179 sch_work = true;
1180 } else {
1181 mutex_unlock(&rport->mutex);
1182 return;
1183 }
1184 break;
1185 default:
1186 mutex_unlock(&rport->mutex);
1187 return;
1188 }
1189
1190 if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached) {
1191 extcon_set_state_sync(rphy->edev, cable, rport->vbus_attached);
1192
1193 if (!rport->vbus_attached) {
1194 cable = EXTCON_NONE;
1195 }
1196 } else if (rport->state == OTG_STATE_A_HOST && extcon_get_state(rphy->edev, cable)) {
1197 /*
1198 * If plug in OTG host cable when the rport state is
1199 * OTG_STATE_B_PERIPHERAL, the vbus voltage will stay
1200 * in high, so the rport->vbus_attached may not be
1201 * changed. We need to set cable state here.
1202 */
1203 extcon_set_state_sync(rphy->edev, cable, false);
1204 cable = EXTCON_NONE;
1205 }
1206
1207 if (rphy->edev_self && (extcon_get_state(rphy->edev, EXTCON_USB) != rport->perip_connected)) {
1208 extcon_set_state_sync(rphy->edev, EXTCON_USB, rport->perip_connected);
1209 extcon_sync(rphy->edev, EXTCON_USB_HOST);
1210 }
1211 if (sch_work) {
1212 schedule_delayed_work(&rport->otg_sm_work, delay);
1213 }
1214
1215 mutex_unlock(&rport->mutex);
1216 }
1217
chg_to_string(enum power_supply_type chg_type)1218 static const char *chg_to_string(enum power_supply_type chg_type)
1219 {
1220 switch (chg_type) {
1221 case POWER_SUPPLY_TYPE_USB:
1222 return "USB_SDP_CHARGER";
1223 case POWER_SUPPLY_TYPE_USB_DCP:
1224 return "USB_DCP_CHARGER";
1225 case POWER_SUPPLY_TYPE_USB_CDP:
1226 return "USB_CDP_CHARGER";
1227 default:
1228 return "INVALID_CHARGER";
1229 }
1230 }
1231
rockchip_chg_enable_dcd(struct rockchip_usb2phy * rphy,bool en)1232 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, bool en)
1233 {
1234 struct regmap *base = get_reg_base(rphy);
1235
1236 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
1237 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
1238 }
1239
rockchip_chg_enable_primary_det(struct rockchip_usb2phy * rphy,bool en)1240 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, bool en)
1241 {
1242 struct regmap *base = get_reg_base(rphy);
1243
1244 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
1245 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
1246 }
1247
rockchip_chg_enable_secondary_det(struct rockchip_usb2phy * rphy,bool en)1248 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, bool en)
1249 {
1250 struct regmap *base = get_reg_base(rphy);
1251
1252 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
1253 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
1254 }
1255
1256 #define CHG_DCD_POLL_TIME (0x64 * HZ / 0x3e8)
1257 #define CHG_DCD_MAX_RETRIES 0x6
1258 #define CHG_PRIMARY_DET_TIME (0x28 * HZ / 0x3e8)
1259 #define CHG_SECONDARY_DET_TIME (0x28 * HZ / 0x3e8)
rockchip_chg_detect_work(struct work_struct * work)1260 static void rockchip_chg_detect_work(struct work_struct *work)
1261 {
1262 struct rockchip_usb2phy_port *rport = container_of(work, struct rockchip_usb2phy_port, chg_work.work);
1263 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1264 struct regmap *base = get_reg_base(rphy);
1265 const struct usb2phy_reg *phy_sus_reg;
1266 bool is_dcd, tmout, vout;
1267 unsigned long delay;
1268 unsigned int mask;
1269 int ret;
1270
1271 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n", rphy->chg_state);
1272
1273 /*
1274 * The conditions for charger detection:
1275 * 1. Set the PHY in normal mode to keep the UTMI_CLK on.
1276 * 2. Set the utmi_opmode in non-driving mode.
1277 * 3. Set the utmi_xcvrselect to FS speed.
1278 * 4. Set the utmi_termselect to FS speed.
1279 * 5. Enable the DP/DM pulldown resistor.
1280 */
1281 switch (rphy->chg_state) {
1282 case USB_CHG_STATE_UNDEFINED:
1283 mutex_lock(&rport->mutex);
1284 /* Store the PHY current suspend configuration */
1285 phy_sus_reg = &rport->port_cfg->phy_sus;
1286 ret = regmap_read(base, phy_sus_reg->offset, &rphy->phy_sus_cfg);
1287 if (ret) {
1288 dev_err(&rport->phy->dev, "Fail to read phy_sus reg offset 0x%x, ret %d\n", phy_sus_reg->offset, ret);
1289 mutex_unlock(&rport->mutex);
1290 return;
1291 }
1292
1293 /* Set the PHY in charger detection mode */
1294 property_enable(base, &rphy->phy_cfg->chg_det.chg_mode, true);
1295 /* Start DCD processing stage 1 */
1296 rockchip_chg_enable_dcd(rphy, true);
1297 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1298 rphy->dcd_retries = 0;
1299 rphy->primary_retries = 0;
1300 delay = CHG_DCD_POLL_TIME;
1301 break;
1302 case USB_CHG_STATE_WAIT_FOR_DCD:
1303 /* get data contact detection status */
1304 is_dcd = property_enabled(rphy->grf, &rphy->phy_cfg->chg_det.dp_det);
1305 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
1306 /* stage 2 */
1307 if (is_dcd || tmout) {
1308 /* stage 4 */
1309 /* Turn off DCD circuitry */
1310 rockchip_chg_enable_dcd(rphy, false);
1311 /* Voltage Source on DP, Probe on DM */
1312 rockchip_chg_enable_primary_det(rphy, true);
1313 delay = CHG_PRIMARY_DET_TIME;
1314 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
1315 } else {
1316 /* stage 3 */
1317 delay = CHG_DCD_POLL_TIME;
1318 }
1319 break;
1320 case USB_CHG_STATE_DCD_DONE:
1321 vout = property_enabled(rphy->grf, &rphy->phy_cfg->chg_det.cp_det);
1322 rockchip_chg_enable_primary_det(rphy, false);
1323 if (vout) {
1324 /* Voltage Source on DM, Probe on DP */
1325 rockchip_chg_enable_secondary_det(rphy, true);
1326 delay = CHG_SECONDARY_DET_TIME;
1327 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1328 } else {
1329 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
1330 /* floating charger found */
1331 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
1332 rphy->chg_state = USB_CHG_STATE_DETECTED;
1333 delay = 0;
1334 } else {
1335 if (rphy->primary_retries < 0x02) {
1336 /* Turn off DCD circuitry */
1337 rockchip_chg_enable_dcd(rphy, false);
1338 /* Voltage Source on DP, Probe on DM */
1339 rockchip_chg_enable_primary_det(rphy, true);
1340 delay = CHG_PRIMARY_DET_TIME;
1341 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
1342 rphy->primary_retries++;
1343 /* break USB_CHG_STATE_DCD_DONE */
1344 break;
1345 }
1346 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
1347 rphy->chg_state = USB_CHG_STATE_DETECTED;
1348 delay = 0;
1349 }
1350 }
1351 break;
1352 case USB_CHG_STATE_PRIMARY_DONE:
1353 vout = property_enabled(rphy->grf, &rphy->phy_cfg->chg_det.dcp_det);
1354 /* Turn off voltage source */
1355 rockchip_chg_enable_secondary_det(rphy, false);
1356 if (vout) {
1357 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
1358 } else {
1359 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
1360 }
1361 fallthrough;
1362 case USB_CHG_STATE_SECONDARY_DONE:
1363 rphy->chg_state = USB_CHG_STATE_DETECTED;
1364 fallthrough;
1365 case USB_CHG_STATE_DETECTED:
1366 if (rphy->phy_cfg->chg_det.chg_mode.offset != rport->port_cfg->phy_sus.offset) {
1367 property_enable(base, &rphy->phy_cfg->chg_det.chg_mode, false);
1368 }
1369
1370 /* Restore the PHY suspend configuration */
1371 phy_sus_reg = &rport->port_cfg->phy_sus;
1372 mask = GENMASK(phy_sus_reg->bitend, phy_sus_reg->bitstart);
1373 ret = regmap_write(base, phy_sus_reg->offset, (rphy->phy_sus_cfg | (mask << BIT_WRITEABLE_SHIFT)));
1374 if (ret) {
1375 dev_err(&rport->phy->dev, "Fail to set phy_sus reg offset 0x%x, ret %d\n", phy_sus_reg->offset, ret);
1376 }
1377 mutex_unlock(&rport->mutex);
1378 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1379 dev_dbg(&rport->phy->dev, "charger = %s\n", chg_to_string(rphy->chg_type));
1380 return;
1381 default:
1382 mutex_unlock(&rport->mutex);
1383 return;
1384 }
1385
1386 /*
1387 * Hold the mutex lock during the whole charger
1388 * detection stage, and release it after detect
1389 * the charger type.
1390 */
1391 schedule_delayed_work(&rport->chg_work, delay);
1392 }
1393
1394 /*
1395 * The function manage host-phy port state and suspend/resume phy port
1396 * to save power.
1397 *
1398 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
1399 * devices is disconnect or not. Besides, we do not need care it is FS/LS
1400 * disconnected or HS disconnected, actually, we just only need get the
1401 * device is disconnected at last through rearm the delayed work,
1402 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
1403 *
1404 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
1405 * some clk related APIs, so do not invoke it from interrupt context directly.
1406 */
rockchip_usb2phy_sm_work(struct work_struct * work)1407 static void rockchip_usb2phy_sm_work(struct work_struct *work)
1408 {
1409 struct rockchip_usb2phy_port *rport = container_of(work, struct rockchip_usb2phy_port, sm_work.work);
1410 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1411 unsigned int sh, ul, uhd, state;
1412 unsigned int ul_mask, uhd_mask;
1413 int ret;
1414
1415 if (!rport->port_cfg->utmi_ls.offset ||
1416 (!rport->port_cfg->utmi_hstdet.offset && !rport->port_cfg->disfall_en.offset)) {
1417 dev_dbg(&rport->phy->dev, "some property may not be specified\n");
1418 return;
1419 }
1420
1421 mutex_lock(&rport->mutex);
1422
1423 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
1424 if (ret < 0) {
1425 goto next_schedule;
1426 }
1427
1428 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend, rport->port_cfg->utmi_ls.bitstart);
1429
1430 if (rport->port_cfg->utmi_hstdet.offset) {
1431 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
1432 if (ret < 0) {
1433 goto next_schedule;
1434 }
1435
1436 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend, rport->port_cfg->utmi_hstdet.bitstart);
1437
1438 sh = rport->port_cfg->utmi_hstdet.bitend - rport->port_cfg->utmi_hstdet.bitstart + 1;
1439 /* stitch on utmi_ls and utmi_hstdet as phy state */
1440 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
1441 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
1442 } else {
1443 state = ((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << 1 | rport->host_disconnect;
1444 }
1445
1446 switch (state) {
1447 case PHY_STATE_HS_ONLINE:
1448 dev_dbg(&rport->phy->dev, "HS online\n");
1449 break;
1450 case PHY_STATE_FS_LS_ONLINE:
1451 /*
1452 * For FS/LS device, the online state share with connect state
1453 * from utmi_ls and utmi_hstdet register, so we distinguish
1454 * them via suspended flag.
1455 *
1456 * Plus, there are two cases, one is D- Line pull-up, and D+
1457 * line pull-down, the state is 4; another is D+ line pull-up,
1458 * and D- line pull-down, the state is 2.
1459 */
1460 if (!rport->suspended) {
1461 /* D- line pull-up, D+ line pull-down */
1462 dev_dbg(&rport->phy->dev, "FS/LS online\n");
1463 break;
1464 }
1465 fallthrough;
1466 case PHY_STATE_CONNECT:
1467 if (rport->suspended) {
1468 dev_dbg(&rport->phy->dev, "Connected\n");
1469 mutex_unlock(&rport->mutex);
1470 rockchip_usb2phy_power_on(rport->phy);
1471 mutex_lock(&rport->mutex);
1472 rport->suspended = false;
1473 } else {
1474 /* D+ line pull-up, D- line pull-down */
1475 dev_dbg(&rport->phy->dev, "FS/LS online\n");
1476 }
1477 break;
1478 case PHY_STATE_DISCONNECT:
1479 if (!rport->suspended) {
1480 dev_dbg(&rport->phy->dev, "Disconnected\n");
1481 mutex_unlock(&rport->mutex);
1482 rockchip_usb2phy_power_off(rport->phy);
1483 mutex_lock(&rport->mutex);
1484 rport->suspended = true;
1485 }
1486
1487 /*
1488 * activate the linestate detection to get the next device
1489 * plug-in irq.
1490 */
1491 rockchip_usb2phy_enable_line_irq(rphy, rport, true);
1492
1493 /*
1494 * we don't need to rearm the delayed work when the phy port
1495 * is suspended.
1496 */
1497 mutex_unlock(&rport->mutex);
1498 return;
1499 default:
1500 dev_dbg(&rport->phy->dev, "unknown phy state %d\n", state);
1501 break;
1502 }
1503
1504 next_schedule:
1505 mutex_unlock(&rport->mutex);
1506 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
1507 }
1508
rockchip_usb2phy_linestate_irq(int irq,void * data)1509 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
1510 {
1511 struct rockchip_usb2phy_port *rport = data;
1512 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1513
1514 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st)) {
1515 return IRQ_NONE;
1516 }
1517
1518 dev_dbg(&rport->phy->dev, "linestate interrupt\n");
1519
1520 mutex_lock(&rport->mutex);
1521
1522 /* disable linestate detect irq and clear its status */
1523 rockchip_usb2phy_enable_line_irq(rphy, rport, false);
1524
1525 mutex_unlock(&rport->mutex);
1526
1527 /*
1528 * In this case for host phy port, a new device is plugged in,
1529 * meanwhile, if the phy port is suspended, we need rearm the work to
1530 * resume it and mange its states; otherwise, we do nothing about that.
1531 */
1532 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST) {
1533 rockchip_usb2phy_sm_work(&rport->sm_work.work);
1534 }
1535
1536 return IRQ_HANDLED;
1537 }
1538
rockchip_usb2phy_bvalid_irq(int irq,void * data)1539 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
1540 {
1541 struct rockchip_usb2phy_port *rport = data;
1542 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1543
1544 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) {
1545 return IRQ_NONE;
1546 }
1547
1548 mutex_lock(&rport->mutex);
1549
1550 /* clear bvalid detect irq pending status */
1551 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
1552
1553 mutex_unlock(&rport->mutex);
1554
1555 if (rport->bypass_uart_en) {
1556 rockchip_usb_bypass_uart(rport, false);
1557 }
1558
1559 cancel_delayed_work_sync(&rport->otg_sm_work);
1560 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1561
1562 return IRQ_HANDLED;
1563 }
1564
rockchip_usb2phy_id_irq(int irq,void * data)1565 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1566 {
1567 struct rockchip_usb2phy_port *rport = data;
1568 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1569 bool cable_vbus_state = false;
1570
1571 if (!property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st) &&
1572 !property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st)) {
1573 return IRQ_NONE;
1574 }
1575
1576 mutex_lock(&rport->mutex);
1577
1578 /* clear id fall or rise detect irq pending status */
1579 if (property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st)) {
1580 property_enable(rphy->grf, &rport->port_cfg->idfall_det_clr, true);
1581 cable_vbus_state = true;
1582 } else if (property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st)) {
1583 property_enable(rphy->grf, &rport->port_cfg->idrise_det_clr, true);
1584 cable_vbus_state = false;
1585 }
1586
1587 extcon_set_state(rphy->edev, EXTCON_USB_HOST, cable_vbus_state);
1588 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, cable_vbus_state);
1589
1590 extcon_sync(rphy->edev, EXTCON_USB_HOST);
1591 extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1592
1593 rockchip_set_vbus_power(rport, cable_vbus_state);
1594
1595 mutex_unlock(&rport->mutex);
1596
1597 return IRQ_HANDLED;
1598 }
1599
rockchip_usb2phy_host_disc_irq(int irq,void * data)1600 static irqreturn_t rockchip_usb2phy_host_disc_irq(int irq, void *data)
1601 {
1602 struct rockchip_usb2phy_port *rport = data;
1603 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1604
1605 if (!property_enabled(rphy->grf, &rport->port_cfg->disfall_st) &&
1606 !property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) {
1607 return IRQ_NONE;
1608 }
1609
1610 mutex_lock(&rport->mutex);
1611
1612 /* clear disconnect fall or rise detect irq pending status */
1613 if (property_enabled(rphy->grf, &rport->port_cfg->disfall_st)) {
1614 property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
1615 rport->host_disconnect = false;
1616 } else if (property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) {
1617 property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
1618 rport->host_disconnect = true;
1619 }
1620
1621 mutex_unlock(&rport->mutex);
1622
1623 return IRQ_HANDLED;
1624 }
1625
rockchip_usb2phy_otg_mux_irq(int irq,void * data)1626 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
1627 {
1628 irqreturn_t ret = IRQ_NONE;
1629
1630 ret = rockchip_usb2phy_id_irq(irq, data);
1631 ret |= rockchip_usb2phy_bvalid_irq(irq, data);
1632 ret |= rockchip_usb2phy_linestate_irq(irq, data);
1633
1634 return ret;
1635 }
1636
rockchip_usb2phy_irq(int irq,void * data)1637 static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
1638 {
1639 struct rockchip_usb2phy *rphy = data;
1640 struct rockchip_usb2phy_port *rport;
1641 irqreturn_t ret = IRQ_NONE;
1642 unsigned int index;
1643 bool force_mode;
1644
1645 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1646 rport = &rphy->ports[index];
1647 if (!rport->phy) {
1648 continue;
1649 }
1650
1651 if (rport->port_id == USB2PHY_PORT_HOST && rport->port_cfg->disfall_en.offset) {
1652 ret = rockchip_usb2phy_host_disc_irq(irq, rport);
1653 }
1654
1655 /* Handle linestate irq for both otg port and host port */
1656 ret = rockchip_usb2phy_linestate_irq(irq, rport);
1657
1658 /*
1659 * Handle bvalid irq and id irq for otg port which
1660 * is assigned to otg controller.
1661 */
1662 if (rport->port_id == USB2PHY_PORT_OTG && rport->mode != USB_DR_MODE_UNKNOWN) {
1663 if (rport->mode == USB_DR_MODE_HOST) {
1664 /*
1665 * If otg port work as usb host mode and
1666 * force_mode is true, it means that the
1667 * otg port is forced to host mode by the
1668 * grf plug iddig indicator via the sys
1669 * interface "otg_mode". We need to handle
1670 * the bvalid irq and id irq in this case.
1671 */
1672 force_mode = property_enabled(rphy->grf, &rport->port_cfg->iddig_en);
1673 if (!force_mode) {
1674 continue;
1675 }
1676 }
1677
1678 if (!rport->vbus_always_on) {
1679 ret |= rockchip_usb2phy_bvalid_irq(irq, rport);
1680 }
1681
1682 ret |= rockchip_usb2phy_id_irq(irq, rport);
1683 }
1684 }
1685
1686 return ret;
1687 }
1688
rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1689 static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport,
1690 struct device_node *child_np)
1691 {
1692 int ret;
1693
1694 /*
1695 * If the usb2 phy used combined irq for otg and host port,
1696 * don't need to init otg and host port irq separately.
1697 */
1698 if (rphy->irq > 0) {
1699 return 0;
1700 }
1701
1702 /*
1703 * Some SoCs (e.g. RV1108) use one combined irq for all of
1704 * the irqs of otg port. So probe the otg-mux interrupt first,
1705 * if not found, then init the regular irqs one by one.
1706 */
1707 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
1708 if (rport->otg_mux_irq > 0) {
1709 ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, NULL, rockchip_usb2phy_otg_mux_irq, IRQF_ONESHOT,
1710 "rockchip_usb2phy_otg", rport);
1711 if (ret) {
1712 dev_err(rphy->dev, "failed to request otg-mux irq handle\n");
1713 }
1714
1715 return ret;
1716 }
1717
1718 /* Init linestate irq for both otg port and host port */
1719 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1720 if (rport->ls_irq <= 0) {
1721 dev_err(rphy->dev, "no linestate irq provided\n");
1722 return -EINVAL;
1723 }
1724
1725 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, rockchip_usb2phy_linestate_irq, IRQF_ONESHOT,
1726 "rockchip_usb2phy_ls", rport);
1727 if (ret) {
1728 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1729 return ret;
1730 }
1731
1732 /*
1733 * If it's host port or it's otg port but only support
1734 * host mode, return immediately without init the bvalid
1735 * and id irqs/
1736 */
1737 if (rport->port_id == USB2PHY_PORT_HOST || rport->mode == USB_DR_MODE_HOST || rport->mode == USB_DR_MODE_UNKNOWN) {
1738 return ret;
1739 }
1740
1741 /* Init the bvalid irq for otg port */
1742 if (!rport->vbus_always_on) {
1743 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1744 if (rport->bvalid_irq <= 0) {
1745 dev_err(rphy->dev, "no bvalid irq provided\n");
1746 return -EINVAL;
1747 }
1748
1749 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL, rockchip_usb2phy_bvalid_irq, IRQF_ONESHOT,
1750 "rockchip_usb2phy_bvalid", rport);
1751 if (ret) {
1752 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1753 return ret;
1754 }
1755 }
1756
1757 /* Init the id irq for otg port */
1758 if (rphy->edev_self) {
1759 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1760 if (rport->id_irq <= 0) {
1761 dev_err(rphy->dev, "no otg id irq provided\n");
1762 return -EINVAL;
1763 }
1764
1765 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL, rockchip_usb2phy_id_irq, IRQF_ONESHOT,
1766 "rockchip_usb2phy_id", rport);
1767 if (ret) {
1768 dev_err(rphy->dev, "failed to request otg-id irq handle\n");
1769 return ret;
1770 }
1771 }
1772
1773 return ret;
1774 }
1775
rockchip_usb2phy_host_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1776 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport,
1777 struct device_node *child_np)
1778 {
1779 int ret;
1780 struct regmap *base = get_reg_base(rphy);
1781
1782 rport->port_id = USB2PHY_PORT_HOST;
1783 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1784
1785 /* enter lower power state when suspend */
1786 rport->low_power_en = of_property_read_bool(child_np, "rockchip,low-power-mode");
1787
1788 mutex_init(&rport->mutex);
1789 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1790
1791 ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1792 if (ret) {
1793 dev_err(rphy->dev, "failed to init irq for host port\n");
1794 return ret;
1795 }
1796
1797 /*
1798 * Let us put phy-port into suspend mode here for saving power
1799 * consumption, and usb controller will resume it during probe
1800 * time if needed.
1801 */
1802 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
1803 if (ret) {
1804 return ret;
1805 }
1806 rport->suspended = true;
1807
1808 return 0;
1809 }
1810
rockchip_otg_event(struct notifier_block * nb,unsigned long event,void * ptr)1811 static int rockchip_otg_event(struct notifier_block *nb, unsigned long event, void *ptr)
1812 {
1813 struct rockchip_usb2phy_port *rport = container_of(nb, struct rockchip_usb2phy_port, event_nb);
1814
1815 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1816
1817 return NOTIFY_DONE;
1818 }
1819
rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1820 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport,
1821 struct device_node *child_np)
1822 {
1823 int ret;
1824 int iddig;
1825 struct regmap *base = get_reg_base(rphy);
1826
1827 rport->port_id = USB2PHY_PORT_OTG;
1828 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1829 rport->state = OTG_STATE_UNDEFINED;
1830 rport->vbus_attached = false;
1831 rport->vbus_enabled = false;
1832 rport->perip_connected = false;
1833 rport->prev_iddig = true;
1834
1835 mutex_init(&rport->mutex);
1836
1837 /* bypass uart function is only used in debug stage. */
1838 rport->bypass_uart_en = of_property_read_bool(child_np, "rockchip,bypass-uart");
1839 rport->vbus_always_on = of_property_read_bool(child_np, "rockchip,vbus-always-on");
1840 rport->utmi_avalid = of_property_read_bool(child_np, "rockchip,utmi-avalid");
1841
1842 /* enter lower power state when suspend */
1843 rport->low_power_en = of_property_read_bool(child_np, "rockchip,low-power-mode");
1844
1845 /* For type-c with vbus_det always pull up */
1846 rport->typec_vbus_det = of_property_read_bool(child_np, "rockchip,typec-vbus-det");
1847
1848 /* Get Vbus regulators */
1849 rport->vbus = devm_regulator_get_optional(&rport->phy->dev, "vbus");
1850 if (IS_ERR(rport->vbus)) {
1851 ret = PTR_ERR(rport->vbus);
1852 if (ret == -EPROBE_DEFER) {
1853 return ret;
1854 }
1855
1856 if (rport->mode == USB_DR_MODE_OTG) {
1857 dev_warn(&rport->phy->dev, "No vbus specified for otg port\n");
1858 }
1859 rport->vbus = NULL;
1860 }
1861
1862 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1863 iddig = property_enabled(rphy->grf, &rport->port_cfg->utmi_iddig);
1864 if (rphy->edev_self && (rport->mode == USB_DR_MODE_HOST || rport->mode == USB_DR_MODE_UNKNOWN || !iddig)) {
1865 /* Enable VBUS supply for otg port */
1866 extcon_set_state(rphy->edev, EXTCON_USB, false);
1867 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1868 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1869 ret = rockchip_set_vbus_power(rport, true);
1870 if (ret) {
1871 return ret;
1872 }
1873 }
1874
1875 ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1876 if (ret) {
1877 dev_err(rphy->dev, "failed to init irq for otg port\n");
1878 return ret;
1879 }
1880
1881 if (rport->vbus_always_on || rport->mode == USB_DR_MODE_HOST || rport->mode == USB_DR_MODE_UNKNOWN) {
1882 goto out;
1883 }
1884
1885 /* Select bvalid of usb phy as bvalid of usb controller */
1886 if (rport->port_cfg->bvalid_grf_con.enable != 0) {
1887 property_enable(base, &rport->port_cfg->bvalid_grf_con, false);
1888 }
1889
1890 wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1891 INIT_DELAYED_WORK(&rport->bypass_uart_work, rockchip_usb_bypass_uart_work);
1892 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1893 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1894
1895 if (!IS_ERR(rphy->edev)) {
1896 rport->event_nb.notifier_call = rockchip_otg_event;
1897
1898 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev, EXTCON_USB_HOST, &rport->event_nb);
1899 if (ret) {
1900 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1901 goto err;
1902 }
1903 }
1904
1905 out:
1906 /*
1907 * Let us put phy-port into suspend mode here for saving power
1908 * consumption, and usb controller will resume it during probe
1909 * time if needed.
1910 */
1911 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
1912 if (ret) {
1913 return ret;
1914 }
1915 rport->suspended = true;
1916
1917 return 0;
1918
1919 err:
1920 wake_lock_destroy(&rport->wakelock);
1921 return ret;
1922 }
1923
rockchip_usb2phy_probe(struct platform_device * pdev)1924 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1925 {
1926 struct device *dev = &pdev->dev;
1927 struct device_node *np = dev->of_node;
1928 struct device_node *child_np;
1929 struct phy_provider *provider;
1930 struct rockchip_usb2phy *rphy;
1931 struct resource *res;
1932 const struct rockchip_usb2phy_cfg *phy_cfgs;
1933 const struct of_device_id *match;
1934 unsigned int reg;
1935 unsigned int index;
1936 int ret;
1937
1938 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1939 if (!rphy) {
1940 return -ENOMEM;
1941 }
1942
1943 match = of_match_device(dev->driver->of_match_table, dev);
1944 if (!match || !match->data) {
1945 dev_err(dev, "phy configs are not assigned!\n");
1946 return -EINVAL;
1947 }
1948
1949 if (!dev->parent || !dev->parent->of_node) {
1950 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1951 if (!res) {
1952 dev_err(dev, "missing memory resource\n");
1953 return -ENODEV;
1954 }
1955
1956 rphy->phy_base = devm_ioremap_resource(dev, res);
1957 if (IS_ERR(rphy->phy_base)) {
1958 return PTR_ERR(rphy->phy_base);
1959 }
1960
1961 rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
1962 if (IS_ERR(rphy->grf)) {
1963 return PTR_ERR(rphy->grf);
1964 }
1965
1966 reg = res->start;
1967 } else {
1968 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1969 if (IS_ERR(rphy->grf)) {
1970 return PTR_ERR(rphy->grf);
1971 }
1972
1973 if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1974 rphy->usbgrf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,usbgrf");
1975 if (IS_ERR(rphy->usbgrf)) {
1976 return PTR_ERR(rphy->usbgrf);
1977 }
1978 } else {
1979 rphy->usbgrf = NULL;
1980 }
1981
1982 if (of_property_read_u32(np, "reg", ®)) {
1983 dev_err(dev, "missing reg property in %s node\n", np->name);
1984 return -EINVAL;
1985 }
1986 }
1987
1988 rphy->dev = dev;
1989 phy_cfgs = match->data;
1990 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1991 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1992 rphy->edev_self = false;
1993 rphy->irq = platform_get_irq(pdev, 0);
1994 platform_set_drvdata(pdev, rphy);
1995
1996 ret = rockchip_usb2phy_extcon_register(rphy);
1997 if (ret) {
1998 return ret;
1999 }
2000
2001 /* find out a proper config which can be matched with dt. */
2002 index = 0;
2003 do {
2004 if (phy_cfgs[index].reg == reg) {
2005 rphy->phy_cfg = &phy_cfgs[index];
2006 break;
2007 }
2008
2009 ++index;
2010 } while (phy_cfgs[index].reg);
2011
2012 if (!rphy->phy_cfg) {
2013 dev_err(dev, "no phy-config can be matched with %pOFn node\n", np);
2014 return -EINVAL;
2015 }
2016
2017 pm_runtime_set_active(dev);
2018 pm_runtime_enable(dev);
2019 pm_runtime_get_sync(dev);
2020
2021 rphy->phy_reset = devm_reset_control_get_optional(dev, "phy");
2022 if (IS_ERR(rphy->phy_reset)) {
2023 return PTR_ERR(rphy->phy_reset);
2024 }
2025
2026 rphy->clk = of_clk_get_by_name(np, "phyclk");
2027 if (!IS_ERR(rphy->clk)) {
2028 clk_prepare_enable(rphy->clk);
2029 } else {
2030 dev_info(&pdev->dev, "no phyclk specified\n");
2031 rphy->clk = NULL;
2032 }
2033
2034 if (rphy->phy_cfg->phy_tuning) {
2035 ret = rphy->phy_cfg->phy_tuning(rphy);
2036 if (ret) {
2037 goto disable_clks;
2038 }
2039 }
2040
2041 index = 0;
2042 for_each_available_child_of_node(np, child_np)
2043 {
2044 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
2045 struct phy *phy;
2046
2047 /* This driver aims to support both otg-port and host-port */
2048 if (!of_node_name_eq(child_np, "host-port") && !of_node_name_eq(child_np, "otg-port")) {
2049 goto next_child;
2050 }
2051
2052 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
2053 if (IS_ERR(phy)) {
2054 dev_err(dev, "failed to create phy\n");
2055 ret = PTR_ERR(phy);
2056 goto put_child;
2057 }
2058
2059 rport->phy = phy;
2060 phy_set_drvdata(rport->phy, rport);
2061
2062 /* initialize otg/host port separately */
2063 if (of_node_name_eq(child_np, "host-port")) {
2064 ret = rockchip_usb2phy_host_port_init(rphy, rport, child_np);
2065 if (ret) {
2066 goto put_child;
2067 }
2068 } else {
2069 ret = rockchip_usb2phy_otg_port_init(rphy, rport, child_np);
2070 if (ret) {
2071 goto put_child;
2072 }
2073 }
2074
2075 next_child:
2076 /* to prevent out of boundary */
2077 if (++index >= rphy->phy_cfg->num_ports) {
2078 break;
2079 }
2080 }
2081
2082 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2083 if (IS_ERR(provider)) {
2084 dev_err(dev, "Failed to register phy provider\n");
2085 ret = PTR_ERR(provider);
2086 goto put_child;
2087 }
2088
2089 /* Attributes */
2090 ret = sysfs_create_group(&dev->kobj, &usb2_phy_attr_group);
2091 if (ret) {
2092 dev_err(dev, "Cannot create sysfs group: %d\n", ret);
2093 goto put_child;
2094 }
2095
2096 ret = rockchip_usb2phy_clk480m_register(rphy);
2097 if (ret) {
2098 dev_err(dev, "failed to register 480m output clock\n");
2099 goto put_child;
2100 }
2101
2102 if (rphy->irq > 0) {
2103 ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL, rockchip_usb2phy_irq, IRQF_ONESHOT,
2104 "rockchip_usb2phy", rphy);
2105 if (ret) {
2106 dev_err(rphy->dev, "failed to request usb2 phy irq handle\n");
2107 goto put_child;
2108 }
2109 }
2110
2111 if (of_property_read_bool(np, "wakeup-source")) {
2112 device_init_wakeup(rphy->dev, true);
2113 } else {
2114 device_init_wakeup(rphy->dev, false);
2115 }
2116
2117 return 0;
2118
2119 put_child:
2120 of_node_put(child_np);
2121 disable_clks:
2122 pm_runtime_put_sync(dev);
2123 pm_runtime_disable(dev);
2124 if (rphy->clk) {
2125 clk_disable_unprepare(rphy->clk);
2126 clk_put(rphy->clk);
2127 }
2128 return ret;
2129 }
2130
rockchip_usb2phy_low_power_enable(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool value)2131 static int __maybe_unused rockchip_usb2phy_low_power_enable(struct rockchip_usb2phy *rphy,
2132 struct rockchip_usb2phy_port *rport, bool value)
2133 {
2134 int ret = 0;
2135
2136 if (!rport->low_power_en) {
2137 return ret;
2138 }
2139
2140 if (rport->port_id == USB2PHY_PORT_OTG) {
2141 dev_info(&rport->phy->dev, "set otg port low power state %d\n", value);
2142 ret = property_enable(rphy->grf, &rport->port_cfg->bypass_bc, value);
2143 if (ret) {
2144 return ret;
2145 }
2146
2147 ret = property_enable(rphy->grf, &rport->port_cfg->bypass_otg, value);
2148 if (ret) {
2149 return ret;
2150 }
2151
2152 ret = property_enable(rphy->grf, &rport->port_cfg->vbus_det_en, !value);
2153 } else if (rport->port_id == USB2PHY_PORT_HOST) {
2154 dev_info(&rport->phy->dev, "set host port low power state %d\n", value);
2155
2156 ret = property_enable(rphy->grf, &rport->port_cfg->bypass_host, value);
2157 }
2158
2159 return ret;
2160 }
2161
rk312x_usb2phy_tuning(struct rockchip_usb2phy * rphy)2162 static int rk312x_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2163 {
2164 int ret;
2165
2166 /* Turn off differential receiver in suspend mode */
2167 ret = regmap_write(rphy->grf, 0x298, 0x00040000);
2168 if (ret) {
2169 return ret;
2170 }
2171
2172 return 0;
2173 }
2174
rk3228_usb2phy_tuning(struct rockchip_usb2phy * rphy)2175 static int rk3228_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2176 {
2177 int ret = 0;
2178
2179 /* Open pre-emphasize in non-chirp state for PHY0 otg port */
2180 if (rphy->phy_cfg->reg == 0x760) {
2181 ret = regmap_write(rphy->grf, 0x76c, 0x00070004);
2182 }
2183
2184 return ret;
2185 }
2186
rk3308_usb2phy_tuning(struct rockchip_usb2phy * rphy)2187 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2188 {
2189 int ret;
2190
2191 /* Open pre-emphasize in non-chirp state for otg port */
2192 ret = regmap_write(rphy->grf, 0x0, 0x00070004);
2193 if (ret) {
2194 return ret;
2195 }
2196
2197 /* Open pre-emphasize in non-chirp state for host port */
2198 ret = regmap_write(rphy->grf, 0x30, 0x00070004);
2199 if (ret) {
2200 return ret;
2201 }
2202
2203 /* Turn off differential receiver in suspend mode */
2204 ret = regmap_write(rphy->grf, 0x18, 0x00040000);
2205 if (ret) {
2206 return ret;
2207 }
2208
2209 return 0;
2210 }
2211
rk3328_usb2phy_tuning(struct rockchip_usb2phy * rphy)2212 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2213 {
2214 int ret;
2215
2216 /* Open debug mode for tuning */
2217 ret = regmap_write(rphy->grf, 0x2c, 0xffff0400);
2218 if (ret) {
2219 return ret;
2220 }
2221
2222 /* Open pre-emphasize in non-chirp state for otg port */
2223 ret = regmap_write(rphy->grf, 0x0, 0x00070004);
2224 if (ret) {
2225 return ret;
2226 }
2227
2228 /* Open pre-emphasize in non-chirp state for host port */
2229 ret = regmap_write(rphy->grf, 0x30, 0x00070004);
2230 if (ret) {
2231 return ret;
2232 }
2233
2234 /* Turn off differential receiver in suspend mode */
2235 ret = regmap_write(rphy->grf, 0x18, 0x00040000);
2236 if (ret) {
2237 return ret;
2238 }
2239
2240 return 0;
2241 }
2242
rk3366_usb2phy_tuning(struct rockchip_usb2phy * rphy)2243 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2244 {
2245 unsigned int open_pre_emphasize = 0xffff851f;
2246 unsigned int eye_height_tuning = 0xffff68c8;
2247 unsigned int compensation_tuning = 0xffff026e;
2248 int ret = 0;
2249
2250 /* open HS pre-emphasize to expand HS slew rate for each port. */
2251 ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
2252 ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
2253 ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
2254 ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
2255
2256 /* compensate default tuning reference relate to ODT and etc. */
2257 ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
2258
2259 return ret;
2260 }
2261
rk3399_usb2phy_tuning(struct rockchip_usb2phy * rphy)2262 static int rk3399_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2263 {
2264 struct device_node *node = rphy->dev->of_node;
2265 int ret = 0;
2266
2267 if (rphy->phy_cfg->reg == 0xe450) {
2268 /*
2269 * Disable the pre-emphasize in eop state
2270 * and chirp state to avoid mis-trigger the
2271 * disconnect detection and also avoid hs
2272 * handshake fail for PHY0.
2273 */
2274 ret |= regmap_write(rphy->grf, 0x4480, GENMASK(0x11, 0x10) | 0x0);
2275 ret |= regmap_write(rphy->grf, 0x44b4, GENMASK(0x11, 0x10) | 0x0);
2276 } else {
2277 /*
2278 * Disable the pre-emphasize in eop state
2279 * and chirp state to avoid mis-trigger the
2280 * disconnect detection and also avoid hs
2281 * handshake fail for PHY1.
2282 */
2283 ret |= regmap_write(rphy->grf, 0x4500, GENMASK(0x11, 0x10) | 0x0);
2284 ret |= regmap_write(rphy->grf, 0x4534, GENMASK(0x11, 0x10) | 0x0);
2285 }
2286
2287 if (!of_property_read_bool(node, "rockchip,u2phy-tuning")) {
2288 return ret;
2289 }
2290
2291 if (rphy->phy_cfg->reg == 0xe450) {
2292 /*
2293 * Set max ODT compensation voltage and
2294 * current tuning reference for PHY0.
2295 */
2296 ret |= regmap_write(rphy->grf, 0x448c, GENMASK(0x17, 0x10) | 0xe3);
2297
2298 /* Set max pre-emphasis level for PHY0 */
2299 ret |= regmap_write(rphy->grf, 0x44b0, GENMASK(0x12, 0x10) | 0x07);
2300
2301 /*
2302 * Set PHY0 A port squelch trigger point to 125mv
2303 */
2304 ret |= regmap_write(rphy->grf, 0x4480, GENMASK(0x1e, 0x1e) | 0x4000);
2305 } else {
2306 /*
2307 * Set max ODT compensation voltage and
2308 * current tuning reference for PHY1.
2309 */
2310 ret |= regmap_write(rphy->grf, 0x450c, GENMASK(0x17, 0x10) | 0xe3);
2311
2312 /* Set max pre-emphasis level for PHY1 */
2313 ret |= regmap_write(rphy->grf, 0x4530, GENMASK(0x12, 0x10) | 0x07);
2314
2315 /*
2316 * Set PHY1 A port squelch trigger point to 125mv
2317 */
2318 ret |= regmap_write(rphy->grf, 0x4500, GENMASK(0x1e, 0x1e) | 0x4000);
2319 }
2320
2321 return ret;
2322 }
2323
rk3568_usb2phy_tuning(struct rockchip_usb2phy * rphy)2324 static int rk3568_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2325 {
2326 u32 reg;
2327 int ret = 0;
2328
2329 reg = readl(rphy->phy_base + 0x30);
2330 /* turn off differential reciver in suspend mode */
2331 writel(reg & ~BIT(0x2), rphy->phy_base + 0x30);
2332
2333 reg = readl(rphy->phy_base);
2334 /* Enable otg port pre-emphasis during non-chirp phase */
2335 reg &= ~(0x07 << 0);
2336 reg |= (0x04 << 0);
2337 writel(reg, rphy->phy_base);
2338
2339 reg = readl(rphy->phy_base + 0x0400);
2340 /* Enable host port pre-emphasis during non-chirp phase */
2341 reg &= ~(0x07 << 0);
2342 reg |= (0x04 << 0);
2343 writel(reg, rphy->phy_base + 0x0400);
2344
2345 if (rphy->phy_cfg->reg == 0xfe8a0000) {
2346 /* Set otg port HS eye height to 437.5mv(default is 400mv) */
2347 reg = readl(rphy->phy_base + 0x30);
2348 reg &= ~(0x07 << 0x4);
2349 reg |= (0x06 << 0x4);
2350 writel(reg, rphy->phy_base + 0x30);
2351
2352 /*
2353 * Set the bvalid filter time to 10ms
2354 * based on the usb2 phy grf pclk 100MHz.
2355 */
2356 ret |= regmap_write(rphy->grf, 0x0048, FILTER_COUNTER);
2357
2358 /*
2359 * Set the id filter time to 10ms based
2360 * on the usb2 phy grf pclk 100MHz.
2361 */
2362 ret |= regmap_write(rphy->grf, 0x004c, FILTER_COUNTER);
2363 }
2364
2365 return ret;
2366 }
2367
rk3568_vbus_detect_control(struct rockchip_usb2phy * rphy,bool en)2368 static int rk3568_vbus_detect_control(struct rockchip_usb2phy *rphy, bool en)
2369 {
2370 u32 reg;
2371
2372 if (en) {
2373 reg = readl(rphy->phy_base + 0x3c);
2374 /* Enable vbus voltage level detection function */
2375 writel(reg & ~BIT(0x7), rphy->phy_base + 0x3c);
2376 } else {
2377 reg = readl(rphy->phy_base + 0x3c);
2378 /* Disable vbus voltage level detection function */
2379 writel(reg | BIT(0x7), rphy->phy_base + 0x3c);
2380 }
2381
2382 return 0;
2383 }
2384
rk3588_usb2phy_tuning(struct rockchip_usb2phy * rphy)2385 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
2386 {
2387 int ret = 0;
2388
2389 /* Deassert SIDDQ to power on analog block */
2390 ret = regmap_write(rphy->grf, 0x0008, GENMASK(0x1d, 0x1d) | 0x0000);
2391 if (ret) {
2392 return ret;
2393 }
2394
2395 /* Do reset after exit IDDQ mode */
2396 ret = rockchip_usb2phy_reset(rphy);
2397 if (ret) {
2398 return ret;
2399 }
2400
2401 if (rphy->phy_cfg->reg == 0x0000) {
2402 /*
2403 * Set USB2 PHY0 suspend configuration for USB3_0
2404 * 1. Set utmi_termselect to 1'b1 (en FS terminations)
2405 * 2. Set utmi_xcvrselect to 2'b01 (FS transceiver)
2406 * 3. Set utmi_opmode to 2'b01 (no-driving)
2407 */
2408 ret |= regmap_write(rphy->grf, 0x000c, GENMASK(0x14, 0x10) | 0x0015);
2409
2410 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
2411 ret |= regmap_write(rphy->grf, 0x0004, GENMASK(0x1b, 0x18) | 0x0900);
2412
2413 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
2414 ret |= regmap_write(rphy->grf, 0x0008, GENMASK(0x14, 0x13) | 0x0010);
2415
2416 /* Pullup iddig pin for USB3_0 OTG mode */
2417 ret |= regmap_write(rphy->grf, 0x0010, GENMASK(0x11, 0x10) | 0x0003);
2418 } else if (rphy->phy_cfg->reg == 0x4000) {
2419 /*
2420 * Set USB2 PHY1 suspend configuration for USB3_1
2421 * 1. Set utmi_termselect to 1'b1 (en FS terminations)
2422 * 2. Set utmi_xcvrselect to 2'b01(FS transceiver)
2423 * 3. Set utmi_opmode to 2'b01 (no-driving)
2424 */
2425 ret |= regmap_write(rphy->grf, 0x000c, GENMASK(0x14, 0x10) | 0x0015);
2426
2427 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
2428 ret |= regmap_write(rphy->grf, 0x0004, GENMASK(0x1b, 0x18) | 0x0900);
2429
2430 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
2431 ret |= regmap_write(rphy->grf, 0x0008, GENMASK(0x14, 0x13) | 0x0010);
2432
2433 /* Pullup iddig pin for USB3_1 OTG mode */
2434 ret |= regmap_write(rphy->grf, 0x0010, GENMASK(0x11, 0x10) | 0x0003);
2435 } else if (rphy->phy_cfg->reg == 0x8000) {
2436 /*
2437 * Set USB2 PHY2 suspend configuration for USB2_0
2438 * 1. Set utmi_termselect to 1'b1 (en FS terminations)
2439 * 2. Set utmi_xcvrselect to 2'b01(FS transceiver)
2440 * 3. Set utmi_opmode to 2'b00 (normal)
2441 */
2442 ret |= regmap_write(rphy->grf, 0x000c, GENMASK(0x14, 0x10) | 0x0014);
2443
2444 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
2445 ret |= regmap_write(rphy->grf, 0x0004, GENMASK(0x1b, 0x18) | 0x0900);
2446
2447 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
2448 ret |= regmap_write(rphy->grf, 0x0008, GENMASK(0x14, 0x13) | 0x0010);
2449 } else if (rphy->phy_cfg->reg == 0xc000) {
2450 /*
2451 * Set USB2 PHY3 suspend configuration for USB2_1
2452 * 1. Set utmi_termselect to 1'b1 (en FS terminations)
2453 * 2. Set utmi_xcvrselect to 2'b01(FS transceiver)
2454 * 3. Set utmi_opmode to 2'b00 (normal)
2455 */
2456 ret |= regmap_write(rphy->grf, 0x000c, GENMASK(0x14, 0x10) | 0x0014);
2457
2458 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
2459 ret |= regmap_write(rphy->grf, 0x0004, GENMASK(0x1b, 0x18) | 0x0900);
2460
2461 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
2462 ret |= regmap_write(rphy->grf, 0x0008, GENMASK(0x14, 0x13) | 0x0010);
2463 }
2464
2465 return ret;
2466 }
2467
2468 #ifdef CONFIG_PM_SLEEP
rockchip_usb2phy_pm_suspend(struct device * dev)2469 static int rockchip_usb2phy_pm_suspend(struct device *dev)
2470 {
2471 struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
2472 struct rockchip_usb2phy_port *rport;
2473 unsigned int index;
2474 int ret = 0;
2475 bool wakeup_enable = false;
2476
2477 if (device_may_wakeup(rphy->dev)) {
2478 wakeup_enable = true;
2479 }
2480
2481 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
2482 rport = &rphy->ports[index];
2483 if (!rport->phy) {
2484 continue;
2485 }
2486
2487 if (rport->port_id == USB2PHY_PORT_OTG && (rport->id_irq > 0 || rphy->irq > 0)) {
2488 mutex_lock(&rport->mutex);
2489 rport->prev_iddig = property_enabled(rphy->grf, &rport->port_cfg->utmi_iddig);
2490 ret = rockchip_usb2phy_enable_id_irq(rphy, rport, false);
2491 mutex_unlock(&rport->mutex);
2492 if (ret) {
2493 dev_err(rphy->dev, "failed to disable id irq\n");
2494 return ret;
2495 }
2496 }
2497
2498 if (rport->port_id == USB2PHY_PORT_OTG && wakeup_enable && rport->bvalid_irq > 0) {
2499 enable_irq_wake(rport->bvalid_irq);
2500 }
2501
2502 /* activate the linestate to detect the next interrupt. */
2503 mutex_lock(&rport->mutex);
2504 ret = rockchip_usb2phy_enable_line_irq(rphy, rport, true);
2505 mutex_unlock(&rport->mutex);
2506 if (ret) {
2507 dev_err(rphy->dev, "failed to enable linestate irq\n");
2508 return ret;
2509 }
2510
2511 if (wakeup_enable && rport->ls_irq > 0) {
2512 enable_irq_wake(rport->ls_irq);
2513 }
2514
2515 /* enter low power state */
2516 rockchip_usb2phy_low_power_enable(rphy, rport, true);
2517 }
2518
2519 return ret;
2520 }
2521
rockchip_usb2phy_pm_resume(struct device * dev)2522 static int rockchip_usb2phy_pm_resume(struct device *dev)
2523 {
2524 struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
2525 struct rockchip_usb2phy_port *rport;
2526 unsigned int index;
2527 bool iddig;
2528 int ret = 0;
2529 bool wakeup_enable = false;
2530
2531 if (device_may_wakeup(rphy->dev)) {
2532 wakeup_enable = true;
2533 }
2534
2535 if (rphy->phy_cfg->phy_tuning) {
2536 ret = rphy->phy_cfg->phy_tuning(rphy);
2537 }
2538
2539 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
2540 rport = &rphy->ports[index];
2541 if (!rport->phy) {
2542 continue;
2543 }
2544
2545 if (rport->port_id == USB2PHY_PORT_OTG && (rport->id_irq > 0 || rphy->irq > 0)) {
2546 mutex_lock(&rport->mutex);
2547 iddig = property_enabled(rphy->grf, &rport->port_cfg->utmi_iddig);
2548 ret = rockchip_usb2phy_enable_id_irq(rphy, rport, true);
2549 mutex_unlock(&rport->mutex);
2550 if (ret) {
2551 dev_err(rphy->dev, "failed to enable id irq\n");
2552 return ret;
2553 }
2554
2555 if (iddig != rport->prev_iddig) {
2556 dev_dbg(&rport->phy->dev, "iddig changed during resume\n");
2557 rport->prev_iddig = iddig;
2558 extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !iddig);
2559 extcon_set_state_sync(rphy->edev, EXTCON_USB_VBUS_EN, !iddig);
2560 ret = rockchip_set_vbus_power(rport, !iddig);
2561 if (ret) {
2562 return ret;
2563 }
2564 }
2565 }
2566
2567 if (rport->port_id == USB2PHY_PORT_OTG && wakeup_enable && rport->bvalid_irq > 0) {
2568 disable_irq_wake(rport->bvalid_irq);
2569 }
2570
2571 if (wakeup_enable && rport->ls_irq > 0) {
2572 disable_irq_wake(rport->ls_irq);
2573 }
2574
2575 /* exit low power state */
2576 rockchip_usb2phy_low_power_enable(rphy, rport, false);
2577 }
2578
2579 return ret;
2580 }
2581
2582 static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
2583 SET_SYSTEM_SLEEP_PM_OPS(rockchip_usb2phy_pm_suspend, rockchip_usb2phy_pm_resume)};
2584
2585 #define ROCKCHIP_USB2PHY_DEV_PM (&rockchip_usb2phy_dev_pm_ops)
2586 #else
2587 #define ROCKCHIP_USB2PHY_DEV_PM NULL
2588 #endif /* CONFIG_PM_SLEEP */
2589
2590 static const struct rockchip_usb2phy_cfg
2591 rk1808_phy_cfgs[] = {{
2592 .reg = 0x100,
2593 .num_ports = 2,
2594 .clkout_ctl = {0x108, 4, 4, 1, 0},
2595 .port_cfgs = {[USB2PHY_PORT_OTG] =
2596 {
2597 .phy_sus = {0x0100, 8, 0, 0, 0x1d1},
2598 .bvalid_det_en = {0x0110, 2, 2, 0, 1},
2599 .bvalid_det_st = {0x0114, 2, 2, 0, 1},
2600 .bvalid_det_clr = {0x0118, 2, 2, 0, 1},
2601 .bypass_dm_en = {0x0108, 2, 2, 0, 1},
2602 .bypass_sel = {0x0108, 3, 3, 0, 1},
2603 .iddig_output = {0x0100, 10, 10, 0, 1},
2604 .iddig_en = {0x0100, 9, 9, 0, 1},
2605 .idfall_det_en = {0x0110, 5, 5, 0, 1},
2606 .idfall_det_st = {0x0114, 5, 5, 0, 1},
2607 .idfall_det_clr = {0x0118, 5, 5, 0, 1},
2608 .idrise_det_en = {0x0110, 4, 4, 0, 1},
2609 .idrise_det_st = {0x0114, 4, 4, 0, 1},
2610 .idrise_det_clr = {0x0118, 4, 4, 0, 1},
2611 .ls_det_en = {0x0110, 0, 0, 0, 1},
2612 .ls_det_st = {0x0114, 0, 0, 0, 1},
2613 .ls_det_clr = {0x0118, 0, 0, 0, 1},
2614 .utmi_avalid = {0x0120, 10, 10, 0, 1},
2615 .utmi_bvalid = {0x0120, 9, 9, 0, 1},
2616 .utmi_iddig = {0x0120, 6, 6, 0, 1},
2617 .utmi_ls = {0x0120, 5, 4, 0, 1},
2618 .vbus_det_en = {0x001c, 15, 15, 1, 0},
2619 },
2620 [USB2PHY_PORT_HOST] =
2621 {
2622 .phy_sus = {0x104, 8, 0, 0, 0x1d1},
2623 .ls_det_en = {0x110, 1, 1, 0, 1},
2624 .ls_det_st = {0x114, 1, 1, 0, 1},
2625 .ls_det_clr = {0x118, 1, 1, 0, 1},
2626 .utmi_ls = {0x120, 17, 16, 0, 1},
2627 .utmi_hstdet = {0x120, 19, 19, 0, 1}
2628 }
2629 },
2630 .chg_det =
2631 {
2632 .chg_mode = {0x0100, 8, 0, 0, 0x1d7},
2633 .cp_det = {0x0120, 24, 24, 0, 1},
2634 .dcp_det = {0x0120, 23, 23, 0, 1},
2635 .dp_det = {0x0120, 25, 25, 0, 1},
2636 .idm_sink_en = {0x0108, 8, 8, 0, 1},
2637 .idp_sink_en = {0x0108, 7, 7, 0, 1},
2638 .idp_src_en = {0x0108, 9, 9, 0, 1},
2639 .rdm_pdwn_en = {0x0108, 10, 10, 0, 1},
2640 .vdm_src_en = {0x0108, 12, 12, 0, 1},
2641 .vdp_src_en = {0x0108, 11, 11, 0, 1},
2642 },
2643 },
2644 {}
2645 };
2646
2647 static const struct rockchip_usb2phy_cfg
2648 rk312x_phy_cfgs[] = {{
2649 .reg = 0x17c,
2650 .num_ports = 2,
2651 .phy_tuning = rk312x_usb2phy_tuning,
2652 .clkout_ctl = {0x0190, 15, 15, 1, 0},
2653 .port_cfgs = {[USB2PHY_PORT_OTG] =
2654 {
2655 .phy_sus = {0x017c, 8, 0, 0, 0x1d1},
2656 .bvalid_det_en = {0x017c, 14, 14, 0, 1},
2657 .bvalid_det_st = {0x017c, 15, 15, 0, 1},
2658 .bvalid_det_clr = {0x017c, 15, 15, 0, 1},
2659 .bypass_dm_en = {0x0190, 12, 12, 0, 1},
2660 .bypass_sel = {0x0190, 13, 13, 0, 1},
2661 .iddig_output = {0x017c, 10, 10, 0, 1},
2662 .iddig_en = {0x017c, 9, 9, 0, 1},
2663 .idfall_det_en = {0x01a0, 2, 2, 0, 1},
2664 .idfall_det_st = {0x01a0, 3, 3, 0, 1},
2665 .idfall_det_clr = {0x01a0, 3, 3, 0, 1},
2666 .idrise_det_en = {0x01a0, 0, 0, 0, 1},
2667 .idrise_det_st = {0x01a0, 1, 1, 0, 1},
2668 .idrise_det_clr = {0x01a0, 1, 1, 0, 1},
2669 .ls_det_en = {0x017c, 12, 12, 0, 1},
2670 .ls_det_st = {0x017c, 13, 13, 0, 1},
2671 .ls_det_clr = {0x017c, 13, 13, 0, 1},
2672 .utmi_bvalid = {0x014c, 5, 5, 0, 1},
2673 .utmi_iddig = {0x014c, 8, 8, 0, 1},
2674 .utmi_ls = {0x014c, 7, 6, 0, 1},
2675 },
2676 [USB2PHY_PORT_HOST] =
2677 {
2678 .phy_sus = {0x0194, 8, 0, 0, 0x1d1},
2679 .ls_det_en = {0x0194, 14, 14, 0, 1},
2680 .ls_det_st = {0x0194, 15, 15, 0, 1},
2681 .ls_det_clr = {0x0194, 15, 15, 0, 1}}},
2682 .chg_det =
2683 {
2684 .chg_mode = {0x017c, 8, 0, 0, 0x1d7},
2685 .cp_det = {0x02c0, 6, 6, 0, 1},
2686 .dcp_det = {0x02c0, 5, 5, 0, 1},
2687 .dp_det = {0x02c0, 7, 7, 0, 1},
2688 .idm_sink_en = {0x0184, 8, 8, 0, 1},
2689 .idp_sink_en = {0x0184, 7, 7, 0, 1},
2690 .idp_src_en = {0x0184, 9, 9, 0, 1},
2691 .rdm_pdwn_en = {0x0184, 10, 10, 0, 1},
2692 .vdm_src_en = {0x0184, 12, 12, 0, 1},
2693 .vdp_src_en = {0x0184, 11, 11, 0, 1},
2694 },
2695 },
2696 {}
2697 };
2698
2699 static const struct rockchip_usb2phy_cfg
2700 rk3228_phy_cfgs[] = {
2701 {
2702 .reg = 0x760,
2703 .num_ports = 2,
2704 .phy_tuning = rk3228_usb2phy_tuning,
2705 .clkout_ctl = {0x0768, 4, 4, 1, 0},
2706 .port_cfgs = {[USB2PHY_PORT_OTG] =
2707 {
2708 .phy_sus = {0x0760, 8, 0, 0, 0x1d1},
2709 .bvalid_det_en = {0x0680, 3, 3, 0, 1},
2710 .bvalid_det_st = {0x0690, 3, 3, 0, 1},
2711 .bvalid_det_clr = {0x06a0, 3, 3, 0, 1},
2712 .iddig_output = {0x0760, 10, 10, 0, 1},
2713 .iddig_en = {0x0760, 9, 9, 0, 1},
2714 .idfall_det_en = {0x0680, 6, 6, 0, 1},
2715 .idfall_det_st = {0x0690, 6, 6, 0, 1},
2716 .idfall_det_clr = {0x06a0, 6, 6, 0, 1},
2717 .idrise_det_en = {0x0680, 5, 5, 0, 1},
2718 .idrise_det_st = {0x0690, 5, 5, 0, 1},
2719 .idrise_det_clr = {0x06a0, 5, 5, 0, 1},
2720 .ls_det_en = {0x0680, 2, 2, 0, 1},
2721 .ls_det_st = {0x0690, 2, 2, 0, 1},
2722 .ls_det_clr = {0x06a0, 2, 2, 0, 1},
2723 .utmi_bvalid = {0x0480, 4, 4, 0, 1},
2724 .utmi_iddig = {0x0480, 1, 1, 0, 1},
2725 .utmi_ls = {0x0480, 3, 2, 0, 1},
2726 .vbus_det_en = {0x0788, 15, 15, 1, 0},
2727 },
2728 [USB2PHY_PORT_HOST] =
2729 {
2730 .phy_sus = {0x0764, 8, 0, 0, 0x1d1},
2731 .ls_det_en = {0x0680, 4, 4, 0, 1},
2732 .ls_det_st = {0x0690, 4, 4, 0, 1},
2733 .ls_det_clr = {0x06a0, 4, 4, 0, 1}}},
2734 .chg_det =
2735 {
2736 .chg_mode = {0x0760, 8, 0, 0, 0x1d7},
2737 .cp_det = {0x0884, 4, 4, 0, 1},
2738 .dcp_det = {0x0884, 3, 3, 0, 1},
2739 .dp_det = {0x0884, 5, 5, 0, 1},
2740 .idm_sink_en = {0x0768, 8, 8, 0, 1},
2741 .idp_sink_en = {0x0768, 7, 7, 0, 1},
2742 .idp_src_en = {0x0768, 9, 9, 0, 1},
2743 .rdm_pdwn_en = {0x0768, 10, 10, 0, 1},
2744 .vdm_src_en = {0x0768, 12, 12, 0, 1},
2745 .vdp_src_en = {0x0768, 11, 11, 0, 1},
2746 },
2747 },
2748 {
2749 .reg = 0x800,
2750 .num_ports = 2,
2751 .clkout_ctl = {0x0808, 4, 4, 1, 0},
2752 .port_cfgs = {
2753 [USB2PHY_PORT_OTG] = {
2754 .phy_sus = {0x804, 8, 0, 0, 0x1d1},
2755 .ls_det_en = {0x0684, 1, 1, 0, 1},
2756 .ls_det_st = {0x0694, 1, 1, 0, 1},
2757 .ls_det_clr = {0x06a4, 1, 1, 0, 1}
2758 },
2759 [USB2PHY_PORT_HOST] = {
2760 .phy_sus = {0x800, 8, 0, 0, 0x1d1},
2761 .ls_det_en = {0x0684, 0, 0, 0, 1},
2762 .ls_det_st = {0x0694, 0, 0, 0, 1},
2763 .ls_det_clr = {0x06a4, 0, 0, 0, 1}
2764 }
2765 },
2766 },
2767 {}
2768 };
2769
2770 static const struct rockchip_usb2phy_cfg
2771 rk3308_phy_cfgs[] = {
2772 {
2773 .reg = 0x100,
2774 .num_ports = 2,
2775 .phy_tuning = rk3308_usb2phy_tuning,
2776 .clkout_ctl = {0x0108, 4, 4, 1, 0},
2777 .port_cfgs = {
2778 [USB2PHY_PORT_OTG] = {
2779 .phy_sus = {0x0100, 8, 0, 0, 0x1d1},
2780 .bvalid_det_en = {0x3020, 2, 2, 0, 1},
2781 .bvalid_det_st = {0x3024, 2, 2, 0, 1},
2782 .bvalid_det_clr = {0x3028, 2, 2, 0, 1},
2783 .iddig_output = {0x0100, 10, 10, 0, 1},
2784 .iddig_en = {0x0100, 9, 9, 0, 1},
2785 .idfall_det_en = {0x3020, 5, 5, 0, 1},
2786 .idfall_det_st = {0x3024, 5, 5, 0, 1},
2787 .idfall_det_clr = {0x3028, 5, 5, 0, 1},
2788 .idrise_det_en = {0x3020, 4, 4, 0, 1},
2789 .idrise_det_st = {0x3024, 4, 4, 0, 1},
2790 .idrise_det_clr = {0x3028, 4, 4, 0, 1},
2791 .ls_det_en = {0x3020, 0, 0, 0, 1},
2792 .ls_det_st = {0x3024, 0, 0, 0, 1},
2793 .ls_det_clr = {0x3028, 0, 0, 0, 1},
2794 .utmi_avalid = {0x0120, 10, 10, 0, 1},
2795 .utmi_bvalid = {0x0120, 9, 9, 0, 1},
2796 .utmi_iddig = {0x0120, 6, 6, 0, 1},
2797 .utmi_ls = {0x0120, 5, 4, 0, 1},
2798 .vbus_det_en = {0x001c, 15, 15, 1, 0},
2799 },
2800 [USB2PHY_PORT_HOST] = {
2801 .phy_sus = {0x0104, 8, 0, 0, 0x1d1},
2802 .ls_det_en = {0x3020, 1, 1, 0, 1},
2803 .ls_det_st = {0x3024, 1, 1, 0, 1},
2804 .ls_det_clr = {0x3028, 1, 1, 0, 1},
2805 .utmi_ls = {0x120, 17, 16, 0, 1},
2806 .utmi_hstdet = {0x120, 19, 19, 0, 1}
2807 }
2808 },
2809 .chg_det = {
2810 .chg_mode = {0x0100, 8, 0, 0, 0x1d7},
2811 .cp_det = {0x0120, 24, 24, 0, 1},
2812 .dcp_det = {0x0120, 23, 23, 0, 1},
2813 .dp_det = {0x0120, 25, 25, 0, 1},
2814 .idm_sink_en = {0x0108, 8, 8, 0, 1},
2815 .idp_sink_en = {0x0108, 7, 7, 0, 1},
2816 .idp_src_en = {0x0108, 9, 9, 0, 1},
2817 .rdm_pdwn_en = {0x0108, 10, 10, 0, 1},
2818 .vdm_src_en = {0x0108, 12, 12, 0, 1},
2819 .vdp_src_en = {0x0108, 11, 11, 0, 1},
2820 },
2821 },
2822 {}
2823 };
2824
2825 static const struct rockchip_usb2phy_cfg
2826 rk3328_phy_cfgs[] = {
2827 {
2828 .reg = 0x100,
2829 .num_ports = 2,
2830 .phy_tuning = rk3328_usb2phy_tuning,
2831 .clkout_ctl = {0x108, 4, 4, 1, 0},
2832 .port_cfgs = {
2833 [USB2PHY_PORT_OTG] = {
2834 .phy_sus = {0x0100, 8, 0, 0, 0x1d1},
2835 .bvalid_det_en = {0x0110, 2, 2, 0, 1},
2836 .bvalid_det_st = {0x0114, 2, 2, 0, 1},
2837 .bvalid_det_clr = {0x0118, 2, 2, 0, 1},
2838 .bypass_bc = {0x0008, 14, 14, 0, 1},
2839 .bypass_otg = {0x0018, 15, 15, 1, 0},
2840 .iddig_output = {0x0100, 10, 10, 0, 1},
2841 .iddig_en = {0x0100, 9, 9, 0, 1},
2842 .idfall_det_en = {0x0110, 5, 5, 0, 1},
2843 .idfall_det_st = {0x0114, 5, 5, 0, 1},
2844 .idfall_det_clr = {0x0118, 5, 5, 0, 1},
2845 .idrise_det_en = {0x0110, 4, 4, 0, 1},
2846 .idrise_det_st = {0x0114, 4, 4, 0, 1},
2847 .idrise_det_clr = {0x0118, 4, 4, 0, 1},
2848 .ls_det_en = {0x0110, 0, 0, 0, 1},
2849 .ls_det_st = {0x0114, 0, 0, 0, 1},
2850 .ls_det_clr = {0x0118, 0, 0, 0, 1},
2851 .utmi_avalid = {0x0120, 10, 10, 0, 1},
2852 .utmi_bvalid = {0x0120, 9, 9, 0, 1},
2853 .utmi_iddig = {0x0120, 6, 6, 0, 1},
2854 .utmi_ls = {0x0120, 5, 4, 0, 1},
2855 .vbus_det_en = {0x001c, 15, 15, 1, 0},
2856 },
2857 [USB2PHY_PORT_HOST] = {
2858 .phy_sus = {0x104, 8, 0, 0, 0x1d1},
2859 .bypass_host = {0x048, 15, 15, 1, 0},
2860 .ls_det_en = {0x110, 1, 1, 0, 1},
2861 .ls_det_st = {0x114, 1, 1, 0, 1},
2862 .ls_det_clr = {0x118, 1, 1, 0, 1},
2863 .utmi_ls = {0x120, 17, 16, 0, 1},
2864 .utmi_hstdet = {0x120, 19, 19, 0, 1}
2865 }
2866 },
2867 .chg_det = {
2868 .chg_mode = {0x0100, 8, 0, 0, 0x1d7},
2869 .cp_det = {0x0120, 24, 24, 0, 1},
2870 .dcp_det = {0x0120, 23, 23, 0, 1},
2871 .dp_det = {0x0120, 25, 25, 0, 1},
2872 .idm_sink_en = {0x0108, 8, 8, 0, 1},
2873 .idp_sink_en = {0x0108, 7, 7, 0, 1},
2874 .idp_src_en = {0x0108, 9, 9, 0, 1},
2875 .rdm_pdwn_en = {0x0108, 10, 10, 0, 1},
2876 .vdm_src_en = {0x0108, 12, 12, 0, 1},
2877 .vdp_src_en = {0x0108, 11, 11, 0, 1},
2878 },
2879 },
2880 {}
2881 };
2882
2883 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
2884 {
2885 .reg = 0x700,
2886 .num_ports = 2,
2887 .phy_tuning = rk3366_usb2phy_tuning,
2888 .clkout_ctl = {0x0724, 15, 15, 1, 0},
2889 .port_cfgs = {
2890 [USB2PHY_PORT_HOST] = {
2891 .phy_sus = {0x0728, 8, 0, 0, 0x1d1},
2892 .ls_det_en = {0x0680, 4, 4, 0, 1},
2893 .ls_det_st = {0x0690, 4, 4, 0, 1},
2894 .ls_det_clr = {0x06a0, 4, 4, 0, 1},
2895 .utmi_ls = {0x049c, 14, 13, 0, 1},
2896 .utmi_hstdet = {0x049c, 12, 12, 0, 1}
2897 }
2898 },
2899 },
2900 {}
2901 };
2902
2903 static const struct rockchip_usb2phy_cfg
2904 rk3368_phy_cfgs[] = {
2905 {
2906 .reg = 0x700,
2907 .num_ports = 2,
2908 .clkout_ctl = {0x0724, 15, 15, 1, 0},
2909 .port_cfgs = {
2910 [USB2PHY_PORT_OTG] = {
2911 .phy_sus = {0x0700, 8, 0, 0, 0x1d1},
2912 .bvalid_det_en = {0x0680, 3, 3, 0, 1},
2913 .bvalid_det_st = {0x0690, 3, 3, 0, 1},
2914 .bvalid_det_clr = {0x06a0, 3, 3, 0, 1},
2915 .iddig_output = {0x0700, 10, 10, 0, 1},
2916 .iddig_en = {0x0700, 9, 9, 0, 1},
2917 .idfall_det_en = {0x0680, 6, 6, 0, 1},
2918 .idfall_det_st = {0x0690, 6, 6, 0, 1},
2919 .idfall_det_clr = {0x06a0, 6, 6, 0, 1},
2920 .idrise_det_en = {0x0680, 5, 5, 0, 1},
2921 .idrise_det_st = {0x0690, 5, 5, 0, 1},
2922 .idrise_det_clr = {0x06a0, 5, 5, 0, 1},
2923 .ls_det_en = {0x0680, 2, 2, 0, 1},
2924 .ls_det_st = {0x0690, 2, 2, 0, 1},
2925 .ls_det_clr = {0x06a0, 2, 2, 0, 1},
2926 .utmi_bvalid = {0x04bc, 23, 23, 0, 1},
2927 .utmi_iddig = {0x04bc, 26, 26, 0, 1},
2928 .utmi_ls = {0x04bc, 25, 24, 0, 1},
2929 .vbus_det_en = {0x079c, 15, 15, 1, 0},
2930 },
2931 [USB2PHY_PORT_HOST] = {
2932 .phy_sus = {0x0728, 15, 0, 0, 0x1d1},
2933 .ls_det_en = {0x0680, 4, 4, 0, 1},
2934 .ls_det_st = {0x0690, 4, 4, 0, 1},
2935 .ls_det_clr = {0x06a0, 4, 4, 0, 1}
2936 }
2937 },
2938 .chg_det = {
2939 .chg_mode = {0x0700, 8, 0, 0, 0x1d7},
2940 .cp_det = {0x04b8, 30, 30, 0, 1},
2941 .dcp_det = {0x04b8, 29, 29, 0, 1},
2942 .dp_det = {0x04b8, 31, 31, 0, 1},
2943 .idm_sink_en = {0x0718, 8, 8, 0, 1},
2944 .idp_sink_en = {0x0718, 7, 7, 0, 1},
2945 .idp_src_en = {0x0718, 9, 9, 0, 1},
2946 .rdm_pdwn_en = {0x0718, 10, 10, 0, 1},
2947 .vdm_src_en = {0x0718, 12, 12, 0, 1},
2948 .vdp_src_en = {0x0718, 11, 11, 0, 1},
2949 },
2950 },
2951 {}
2952 };
2953
2954 static const struct rockchip_usb2phy_cfg
2955 rk3399_phy_cfgs[] = {
2956 {
2957 .reg = 0xe450,
2958 .num_ports = 2,
2959 .phy_tuning = rk3399_usb2phy_tuning,
2960 .clkout_ctl = {0xe450, 4, 4, 1, 0},
2961 .port_cfgs = {
2962 [USB2PHY_PORT_OTG] =
2963 {
2964 .phy_sus = {0xe454, 8, 0, 0x052, 0x1d1},
2965 .bvalid_det_en = {0xe3c0, 3, 3, 0, 1},
2966 .bvalid_det_st = {0xe3e0, 3, 3, 0, 1},
2967 .bvalid_det_clr = {0xe3d0, 3, 3, 0, 1},
2968 .bypass_dm_en = {0xe450, 2, 2, 0, 1},
2969 .bypass_sel = {0xe450, 3, 3, 0, 1},
2970 .iddig_output = {0xe454, 10, 10, 0, 1},
2971 .iddig_en = {0xe454, 9, 9, 0, 1},
2972 .idfall_det_en = {0xe3c0, 5, 5, 0, 1},
2973 .idfall_det_st = {0xe3e0, 5, 5, 0, 1},
2974 .idfall_det_clr = {0xe3d0, 5, 5, 0, 1},
2975 .idrise_det_en = {0xe3c0, 4, 4, 0, 1},
2976 .idrise_det_st = {0xe3e0, 4, 4, 0, 1},
2977 .idrise_det_clr = {0xe3d0, 4, 4, 0, 1},
2978 .ls_det_en = {0xe3c0, 2, 2, 0, 1},
2979 .ls_det_st = {0xe3e0, 2, 2, 0, 1},
2980 .ls_det_clr = {0xe3d0, 2, 2, 0, 1},
2981 .utmi_avalid = {0xe2ac, 7, 7, 0, 1},
2982 .utmi_bvalid = {0xe2ac, 12, 12, 0, 1},
2983 .utmi_iddig = {0xe2ac, 8, 8, 0, 1},
2984 .utmi_ls = {0xe2ac, 14, 13, 0, 1},
2985 .vbus_det_en = {0x449c, 15, 15, 1, 0},
2986 },
2987 [USB2PHY_PORT_HOST] = {
2988 .phy_sus = {0xe458, 1, 0, 0x2, 0x1},
2989 .ls_det_en = {0xe3c0, 6, 6, 0, 1},
2990 .ls_det_st = {0xe3e0, 6, 6, 0, 1},
2991 .ls_det_clr = {0xe3d0, 6, 6, 0, 1},
2992 .utmi_ls = {0xe2ac, 22, 21, 0, 1},
2993 .utmi_hstdet = {0xe2ac, 23, 23, 0, 1}
2994 }
2995 },
2996 .chg_det = {
2997 .chg_mode = {0xe454, 8, 0, 0, 0x1d7},
2998 .cp_det = {0xe2ac, 2, 2, 0, 1},
2999 .dcp_det = {0xe2ac, 1, 1, 0, 1},
3000 .dp_det = {0xe2ac, 0, 0, 0, 1},
3001 .idm_sink_en = {0xe450, 8, 8, 0, 1},
3002 .idp_sink_en = {0xe450, 7, 7, 0, 1},
3003 .idp_src_en = {0xe450, 9, 9, 0, 1},
3004 .rdm_pdwn_en = {0xe450, 10, 10, 0, 1},
3005 .vdm_src_en = {0xe450, 12, 12, 0, 1},
3006 .vdp_src_en = {0xe450, 11, 11, 0, 1},
3007 },
3008 },
3009 {
3010 .reg = 0xe460,
3011 .num_ports = 2,
3012 .phy_tuning = rk3399_usb2phy_tuning,
3013 .clkout_ctl = {0xe460, 4, 4, 1, 0},
3014 .port_cfgs = {
3015 [USB2PHY_PORT_OTG] = {
3016 .phy_sus = {0xe464, 8, 0, 0x052, 0x1d1},
3017 .bvalid_det_en = {0xe3c0, 8, 8, 0, 1},
3018 .bvalid_det_st = {0xe3e0, 8, 8, 0, 1},
3019 .bvalid_det_clr = {0xe3d0, 8, 8, 0, 1},
3020 .iddig_output = {0xe464, 10, 10, 0, 1},
3021 .iddig_en = {0xe464, 9, 9, 0, 1},
3022 .idfall_det_en = {0xe3c0, 10, 10, 0, 1},
3023 .idfall_det_st = {0xe3e0, 10, 10, 0, 1},
3024 .idfall_det_clr = {0xe3d0, 10, 10, 0, 1},
3025 .idrise_det_en = {0xe3c0, 9, 9, 0, 1},
3026 .idrise_det_st = {0xe3e0, 9, 9, 0, 1},
3027 .idrise_det_clr = {0xe3d0, 9, 9, 0, 1},
3028 .ls_det_en = {0xe3c0, 7, 7, 0, 1},
3029 .ls_det_st = {0xe3e0, 7, 7, 0, 1},
3030 .ls_det_clr = {0xe3d0, 7, 7, 0, 1},
3031 .utmi_avalid = {0xe2ac, 10, 10, 0, 1},
3032 .utmi_bvalid = {0xe2ac, 16, 16, 0, 1},
3033 .utmi_iddig = {0xe2ac, 11, 11, 0, 1},
3034 .utmi_ls = {0xe2ac, 18, 17, 0, 1},
3035 .vbus_det_en = {0x451c, 15, 15, 1, 0},
3036 },
3037 [USB2PHY_PORT_HOST] = {
3038 .phy_sus = {0xe468, 1, 0, 0x2, 0x1},
3039 .ls_det_en = {0xe3c0, 11, 11, 0, 1},
3040 .ls_det_st = {0xe3e0, 11, 11, 0, 1},
3041 .ls_det_clr = {0xe3d0, 11, 11, 0, 1},
3042 .utmi_ls = {0xe2ac, 26, 25, 0, 1},
3043 .utmi_hstdet = {0xe2ac, 27, 27, 0, 1}
3044 }
3045 },
3046 .chg_det = {
3047 .chg_mode = {0xe464, 8, 0, 0, 0x1d7},
3048 .cp_det = {0xe2ac, 5, 5, 0, 1},
3049 .dcp_det = {0xe2ac, 4, 4, 0, 1},
3050 .dp_det = {0xe2ac, 3, 3, 0, 1},
3051 .idm_sink_en = {0xe460, 8, 8, 0, 1},
3052 .idp_sink_en = {0xe460, 7, 7, 0, 1},
3053 .idp_src_en = {0xe460, 9, 9, 0, 1},
3054 .rdm_pdwn_en = {0xe460, 10, 10, 0, 1},
3055 .vdm_src_en = {0xe460, 12, 12, 0, 1},
3056 .vdp_src_en = {0xe460, 11, 11, 0, 1},
3057 },
3058 },
3059 {}
3060 };
3061
3062 static const struct rockchip_usb2phy_cfg
3063 rk3568_phy_cfgs[] = {
3064 {
3065 .reg = 0xfe8a0000,
3066 .num_ports = 2,
3067 .phy_tuning = rk3568_usb2phy_tuning,
3068 .vbus_detect = rk3568_vbus_detect_control,
3069 .clkout_ctl = {0x0008, 4, 4, 1, 0},
3070 .port_cfgs = {
3071 [USB2PHY_PORT_OTG] = {
3072 .phy_sus = {0x0000, 8, 0, 0, 0x1d1},
3073 .bvalid_det_en = {0x0080, 2, 2, 0, 1},
3074 .bvalid_det_st = {0x0084, 2, 2, 0, 1},
3075 .bvalid_det_clr = {0x0088, 2, 2, 0, 1},
3076 .bvalid_grf_con = {0x0008, 15, 14, 0, 3},
3077 .bypass_dm_en = {0x0008, 2, 2, 0, 1},
3078 .bypass_sel = {0x0008, 3, 3, 0, 1},
3079 .iddig_output = {0x0000, 10, 10, 0, 1},
3080 .iddig_en = {0x0000, 9, 9, 0, 1},
3081 .idfall_det_en = {0x0080, 5, 5, 0, 1},
3082 .idfall_det_st = {0x0084, 5, 5, 0, 1},
3083 .idfall_det_clr = {0x0088, 5, 5, 0, 1},
3084 .idrise_det_en = {0x0080, 4, 4, 0, 1},
3085 .idrise_det_st = {0x0084, 4, 4, 0, 1},
3086 .idrise_det_clr = {0x0088, 4, 4, 0, 1},
3087 .ls_det_en = {0x0080, 0, 0, 0, 1},
3088 .ls_det_st = {0x0084, 0, 0, 0, 1},
3089 .ls_det_clr = {0x0088, 0, 0, 0, 1},
3090 .utmi_avalid = {0x00c0, 10, 10, 0, 1},
3091 .utmi_bvalid = {0x00c0, 9, 9, 0, 1},
3092 .utmi_iddig = {0x00c0, 6, 6, 0, 1},
3093 .utmi_ls = {0x00c0, 5, 4, 0, 1},
3094 },
3095 [USB2PHY_PORT_HOST] = {
3096 .phy_sus = {0x0004, 8, 0, 0x1d2, 0x1d2},
3097 .ls_det_en = {0x0080, 1, 1, 0, 1},
3098 .ls_det_st = {0x0084, 1, 1, 0, 1},
3099 .ls_det_clr = {0x0088, 1, 1, 0, 1},
3100 .utmi_ls = {0x00c0, 17, 16, 0, 1},
3101 .utmi_hstdet = {0x00c0, 19, 19, 0, 1}
3102 }
3103 },
3104 .chg_det = {
3105 .chg_mode = {0x0000, 8, 0, 0, 0x1d7},
3106 .cp_det = {0x00c0, 24, 24, 0, 1},
3107 .dcp_det = {0x00c0, 23, 23, 0, 1},
3108 .dp_det = {0x00c0, 25, 25, 0, 1},
3109 .idm_sink_en = {0x0008, 8, 8, 0, 1},
3110 .idp_sink_en = {0x0008, 7, 7, 0, 1},
3111 .idp_src_en = {0x0008, 9, 9, 0, 1},
3112 .rdm_pdwn_en = {0x0008, 10, 10, 0, 1},
3113 .vdm_src_en = {0x0008, 12, 12, 0, 1},
3114 .vdp_src_en = {0x0008, 11, 11, 0, 1},
3115 },
3116 },
3117 {
3118 .reg = 0xfe8b0000,
3119 .num_ports = 2,
3120 .phy_tuning = rk3568_usb2phy_tuning,
3121 .clkout_ctl = {0x0008, 4, 4, 1, 0},
3122 .port_cfgs = {
3123 [USB2PHY_PORT_OTG] = {
3124 .phy_sus = {0x0000, 8, 0, 0x1d2, 0x1d1},
3125 .ls_det_en = {0x0080, 0, 0, 0, 1},
3126 .ls_det_st = {0x0084, 0, 0, 0, 1},
3127 .ls_det_clr = {0x0088, 0, 0, 0, 1},
3128 .utmi_ls = {0x00c0, 5, 4, 0, 1},
3129 .utmi_hstdet = {0x00c0, 7, 7, 0, 1}},
3130 [USB2PHY_PORT_HOST] = {
3131 .phy_sus = {0x0004, 8, 0, 0x1d2, 0x1d1},
3132 .ls_det_en = {0x0080, 1, 1, 0, 1},
3133 .ls_det_st = {0x0084, 1, 1, 0, 1},
3134 .ls_det_clr = {0x0088, 1, 1, 0, 1},
3135 .utmi_ls = {0x00c0, 17, 16, 0, 1},
3136 .utmi_hstdet = {0x00c0, 19, 19, 0, 1}
3137 }
3138 },
3139 },
3140 {}
3141 };
3142
3143 static const struct rockchip_usb2phy_cfg
3144 rk3588_phy_cfgs[] = {
3145 {
3146 .reg = 0x0000,
3147 .num_ports = 1,
3148 .phy_tuning = rk3588_usb2phy_tuning,
3149 .clkout_ctl = {0x0000, 0, 0, 1, 0},
3150 .port_cfgs = {[USB2PHY_PORT_OTG] =
3151 {
3152 .phy_sus = {0x000c, 11, 11, 0, 1},
3153 .bvalid_det_en = {0x0080, 1, 1, 0, 1},
3154 .bvalid_det_st = {0x0084, 1, 1, 0, 1},
3155 .bvalid_det_clr = {0x0088, 1, 1, 0, 1},
3156 .bvalid_grf_con = {0x0010, 3, 2, 0, 3},
3157 .bypass_dm_en = {0x000c, 5, 5, 0, 1},
3158 .bypass_sel = {0x000c, 6, 6, 0, 1},
3159 .iddig_output = {0x0010, 0, 0, 0, 1},
3160 .iddig_en = {0x0010, 1, 1, 0, 1},
3161 .idfall_det_en = {0x0080, 4, 4, 0, 1},
3162 .idfall_det_st = {0x0084, 4, 4, 0, 1},
3163 .idfall_det_clr = {0x0088, 4, 4, 0, 1},
3164 .idrise_det_en = {0x0080, 3, 3, 0, 1},
3165 .idrise_det_st = {0x0084, 3, 3, 0, 1},
3166 .idrise_det_clr = {0x0088, 3, 3, 0, 1},
3167 .ls_det_en = {0x0080, 0, 0, 0, 1},
3168 .ls_det_st = {0x0084, 0, 0, 0, 1},
3169 .ls_det_clr = {0x0088, 0, 0, 0, 1},
3170 .disfall_en = {0x0080, 6, 6, 0, 1},
3171 .disfall_st = {0x0084, 6, 6, 0, 1},
3172 .disfall_clr = {0x0088, 6, 6, 0, 1},
3173 .disrise_en = {0x0080, 5, 5, 0, 1},
3174 .disrise_st = {0x0084, 5, 5, 0, 1},
3175 .disrise_clr = {0x0088, 5, 5, 0, 1},
3176 .utmi_avalid = {0x00c0, 7, 7, 0, 1},
3177 .utmi_bvalid = {0x00c0, 6, 6, 0, 1},
3178 .utmi_iddig = {0x00c0, 5, 5, 0, 1},
3179 .utmi_ls = {0x00c0, 10, 9, 0, 1},
3180 }},
3181 .chg_det =
3182 {
3183 .chg_mode = {0x0008, 2, 2, 0, 1},
3184 .cp_det = {0x00c0, 0, 0, 0, 1},
3185 .dcp_det = {0x00c0, 0, 0, 0, 1},
3186 .dp_det = {0x00c0, 1, 1, 1, 0},
3187 .idm_sink_en = {0x0008, 5, 5, 1, 0},
3188 .idp_sink_en = {0x0008, 5, 5, 0, 1},
3189 .idp_src_en = {0x0008, 14, 14, 0, 1},
3190 .rdm_pdwn_en = {0x0008, 14, 14, 0, 1},
3191 .vdm_src_en = {0x0008, 7, 6, 0, 3},
3192 .vdp_src_en = {0x0008, 7, 6, 0, 3},
3193 },
3194 },
3195 {
3196 .reg = 0x4000,
3197 .num_ports = 1,
3198 .phy_tuning = rk3588_usb2phy_tuning,
3199 .clkout_ctl = {0x0000, 0, 0, 1, 0},
3200 .port_cfgs =
3201 { /* Select suspend control from controller */
3202 [USB2PHY_PORT_OTG] = {
3203 .phy_sus = {0x000c, 11, 11, 0, 0},
3204 .bvalid_det_en = {0x0080, 1, 1, 0, 1},
3205 .bvalid_det_st = {0x0084, 1, 1, 0, 1},
3206 .bvalid_det_clr = {0x0088, 1, 1, 0, 1},
3207 .bypass_dm_en = {0x000c, 5, 5, 0, 1},
3208 .bypass_sel = {0x000c, 6, 6, 0, 1},
3209 .iddig_output = {0x0010, 0, 0, 0, 1},
3210 .iddig_en = {0x0010, 1, 1, 0, 1},
3211 .idfall_det_en = {0x0080, 4, 4, 0, 1},
3212 .idfall_det_st = {0x0084, 4, 4, 0, 1},
3213 .idfall_det_clr = {0x0088, 4, 4, 0, 1},
3214 .idrise_det_en = {0x0080, 3, 3, 0, 1},
3215 .idrise_det_st = {0x0084, 3, 3, 0, 1},
3216 .idrise_det_clr = {0x0088, 3, 3, 0, 1},
3217 .ls_det_en = {0x0080, 0, 0, 0, 1},
3218 .ls_det_st = {0x0084, 0, 0, 0, 1},
3219 .ls_det_clr = {0x0088, 0, 0, 0, 1},
3220 .disfall_en = {0x0080, 6, 6, 0, 1},
3221 .disfall_st = {0x0084, 6, 6, 0, 1},
3222 .disfall_clr = {0x0088, 6, 6, 0, 1},
3223 .disrise_en = {0x0080, 5, 5, 0, 1},
3224 .disrise_st = {0x0084, 5, 5, 0, 1},
3225 .disrise_clr = {0x0088, 5, 5, 0, 1},
3226 .utmi_avalid = {0x00c0, 7, 7, 0, 1},
3227 .utmi_bvalid = {0x00c0, 6, 6, 0, 1},
3228 .utmi_iddig = {0x00c0, 5, 5, 0, 1},
3229 .utmi_ls = {0x00c0, 10, 9, 0, 1},
3230 }
3231 },
3232 .chg_det = {
3233 .chg_mode = {0x0008, 2, 2, 0, 1},
3234 .cp_det = {0x00c0, 0, 0, 0, 1},
3235 .dcp_det = {0x00c0, 0, 0, 0, 1},
3236 .dp_det = {0x00c0, 1, 1, 1, 0},
3237 .idm_sink_en = {0x0008, 5, 5, 1, 0},
3238 .idp_sink_en = {0x0008, 5, 5, 0, 1},
3239 .idp_src_en = {0x0008, 14, 14, 0, 1},
3240 .rdm_pdwn_en = {0x0008, 14, 14, 0, 1},
3241 .vdm_src_en = {0x0008, 7, 6, 0, 3},
3242 .vdp_src_en = {0x0008, 7, 6, 0, 3},
3243 },
3244 },
3245 {
3246 .reg = 0x8000,
3247 .num_ports = 1,
3248 .phy_tuning = rk3588_usb2phy_tuning,
3249 .clkout_ctl = {0x0000, 0, 0, 1, 0},
3250 .port_cfgs = {
3251 [USB2PHY_PORT_HOST] = {
3252 .phy_sus = {0x0008, 2, 2, 0, 1},
3253 .ls_det_en = {0x0080, 0, 0, 0, 1},
3254 .ls_det_st = {0x0084, 0, 0, 0, 1},
3255 .ls_det_clr = {0x0088, 0, 0, 0, 1},
3256 .disfall_en = {0x0080, 6, 6, 0, 1},
3257 .disfall_st = {0x0084, 6, 6, 0, 1},
3258 .disfall_clr = {0x0088, 6, 6, 0, 1},
3259 .disrise_en = {0x0080, 5, 5, 0, 1},
3260 .disrise_st = {0x0084, 5, 5, 0, 1},
3261 .disrise_clr = {0x0088, 5, 5, 0, 1},
3262 .utmi_ls = {0x00c0, 10, 9, 0, 1},
3263 }
3264 },
3265 },
3266 {
3267 .reg = 0xc000,
3268 .num_ports = 1,
3269 .phy_tuning = rk3588_usb2phy_tuning,
3270 .clkout_ctl = {0x0000, 0, 0, 1, 0},
3271 .port_cfgs = {
3272 [USB2PHY_PORT_HOST] = {
3273 .phy_sus = {0x0008, 2, 2, 0, 1},
3274 .ls_det_en = {0x0080, 0, 0, 0, 1},
3275 .ls_det_st = {0x0084, 0, 0, 0, 1},
3276 .ls_det_clr = {0x0088, 0, 0, 0, 1},
3277 .disfall_en = {0x0080, 6, 6, 0, 1},
3278 .disfall_st = {0x0084, 6, 6, 0, 1},
3279 .disfall_clr = {0x0088, 6, 6, 0, 1},
3280 .disrise_en = {0x0080, 5, 5, 0, 1},
3281 .disrise_st = {0x0084, 5, 5, 0, 1},
3282 .disrise_clr = {0x0088, 5, 5, 0, 1},
3283 .utmi_ls = {0x00c0, 10, 9, 0, 1},
3284 }
3285 },
3286 },
3287 {}
3288 };
3289
3290 static const struct rockchip_usb2phy_cfg
3291 rv1108_phy_cfgs[] = {
3292 {
3293 .reg = 0x100,
3294 .num_ports = 2,
3295 .clkout_ctl = {0x108, 4, 4, 1, 0},
3296 .port_cfgs = {
3297 [USB2PHY_PORT_OTG] = {
3298 .phy_sus = {0x0100, 15, 0, 0, 0x1d1},
3299 .bvalid_det_en = {0x0680, 3, 3, 0, 1},
3300 .bvalid_det_st = {0x0690, 3, 3, 0, 1},
3301 .bvalid_det_clr = {0x06a0, 3, 3, 0, 1},
3302 .ls_det_en = {0x0680, 2, 2, 0, 1},
3303 .ls_det_st = {0x0690, 2, 2, 0, 1},
3304 .ls_det_clr = {0x06a0, 2, 2, 0, 1},
3305 .utmi_bvalid = {0x0804, 10, 10, 0, 1},
3306 .utmi_ls = {0x0804, 13, 12, 0, 1},
3307 },
3308 [USB2PHY_PORT_HOST] = {
3309 .phy_sus = {0x0104, 15, 0, 0, 0x1d1},
3310 .ls_det_en = {0x0680, 4, 4, 0, 1},
3311 .ls_det_st = {0x0690, 4, 4, 0, 1},
3312 .ls_det_clr = {0x06a0, 4, 4, 0, 1},
3313 .utmi_ls = {0x0804, 9, 8, 0, 1},
3314 .utmi_hstdet = {0x0804, 7, 7, 0, 1}
3315 }
3316 },
3317 .chg_det = {
3318 .chg_mode = {0x0100, 8, 0, 0, 0x1d7},
3319 .cp_det = {0x0804, 1, 1, 0, 1},
3320 .dcp_det = {0x0804, 0, 0, 0, 1},
3321 .dp_det = {0x0804, 2, 2, 0, 1},
3322 .idm_sink_en = {0x0108, 8, 8, 0, 1},
3323 .idp_sink_en = {0x0108, 7, 7, 0, 1},
3324 .idp_src_en = {0x0108, 9, 9, 0, 1},
3325 .rdm_pdwn_en = {0x0108, 10, 10, 0, 1},
3326 .vdm_src_en = {0x0108, 12, 12, 0, 1},
3327 .vdp_src_en = {0x0108, 11, 11, 0, 1},
3328 },
3329 },
3330 {}
3331 };
3332
3333 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
3334 {.compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs},
3335 {.compatible = "rockchip,rk1808-usb2phy", .data = &rk1808_phy_cfgs},
3336 {.compatible = "rockchip,rk3128-usb2phy", .data = &rk312x_phy_cfgs},
3337 {.compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs},
3338 {.compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs},
3339 {.compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs},
3340 {.compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs},
3341 {.compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs},
3342 {.compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs},
3343 {.compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs},
3344 {.compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs},
3345 {.compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs},
3346 {}};
3347 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
3348
3349 static struct platform_driver rockchip_usb2phy_driver = {
3350 .probe = rockchip_usb2phy_probe,
3351 .driver =
3352 {
3353 .name = "rockchip-usb2phy",
3354 .pm = ROCKCHIP_USB2PHY_DEV_PM,
3355 .of_match_table = rockchip_usb2phy_dt_match,
3356 },
3357 };
3358 module_platform_driver(rockchip_usb2phy_driver);
3359
3360 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
3361 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
3362 MODULE_LICENSE("GPL v2");
3363