1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Generic Register Files setup
4 *
5 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
6 */
7
8 #include <linux/err.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14
15 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16))
16
17 struct rockchip_grf_value {
18 const char *desc;
19 u32 reg;
20 u32 val;
21 };
22
23 struct rockchip_grf_info {
24 const struct rockchip_grf_value *values;
25 int num_values;
26 };
27
28 #define PX30_GRF_SOC_CON5 0x414
29
30 static const struct rockchip_grf_value px30_defaults[] __initconst = {
31 /*
32 * Postponing auto jtag/sdmmc switching by 5 seconds.
33 * The counter value is calculated based on 24MHz clock.
34 */
35 {"jtag switching delay", PX30_GRF_SOC_CON5, 0x7270E00},
36 };
37
38 static const struct rockchip_grf_info px30_grf __initconst = {
39 .values = px30_defaults,
40 .num_values = ARRAY_SIZE(px30_defaults),
41 };
42
43 #define RK3036_GRF_SOC_CON0 0x140
44
45 static const struct rockchip_grf_value rk3036_defaults[] __initconst = {
46 /*
47 * Disable auto jtag/sdmmc switching that causes issues with the
48 * clock-framework and the mmc controllers making them unreliable.
49 */
50 {"jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11)},
51 };
52
53 static const struct rockchip_grf_info rk3036_grf __initconst = {
54 .values = rk3036_defaults,
55 .num_values = ARRAY_SIZE(rk3036_defaults),
56 };
57
58 #define RK3128_GRF_SOC_CON0 0x140
59
60 static const struct rockchip_grf_value rk3128_defaults[] __initconst = {
61 {"jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8)},
62 };
63
64 static const struct rockchip_grf_info rk3128_grf __initconst = {
65 .values = rk3128_defaults,
66 .num_values = ARRAY_SIZE(rk3128_defaults),
67 };
68
69 #define RK3228_GRF_SOC_CON6 0x418
70
71 static const struct rockchip_grf_value rk3228_defaults[] __initconst = {
72 {"jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8)},
73 };
74
75 static const struct rockchip_grf_info rk3228_grf __initconst = {
76 .values = rk3228_defaults,
77 .num_values = ARRAY_SIZE(rk3228_defaults),
78 };
79
80 #define RK3288_GRF_SOC_CON0 0x244
81 #define RK3288_GRF_SOC_CON2 0x24c
82
83 static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
84 {"jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12)},
85 {"pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0)},
86 };
87
88 static const struct rockchip_grf_info rk3288_grf __initconst = {
89 .values = rk3288_defaults,
90 .num_values = ARRAY_SIZE(rk3288_defaults),
91 };
92
93 #define RK3328_GRF_SOC_CON4 0x410
94
95 static const struct rockchip_grf_value rk3328_defaults[] __initconst = {
96 {"jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12)},
97 };
98
99 static const struct rockchip_grf_info rk3328_grf __initconst = {
100 .values = rk3328_defaults,
101 .num_values = ARRAY_SIZE(rk3328_defaults),
102 };
103
104 #define RK3308_GRF_SOC_CON3 0x30c
105
106 static const struct rockchip_grf_value rk3308_defaults[] __initconst = {
107 {"uart dma mask", RK3308_GRF_SOC_CON3, HIWORD_UPDATE(0, 0x1f, 10)},
108 };
109
110 static const struct rockchip_grf_info rk3308_grf __initconst = {
111 .values = rk3308_defaults,
112 .num_values = ARRAY_SIZE(rk3308_defaults),
113 };
114
115 #define RK3368_GRF_SOC_CON15 0x43c
116
117 static const struct rockchip_grf_value rk3368_defaults[] __initconst = {
118 {"jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13)},
119 };
120
121 static const struct rockchip_grf_info rk3368_grf __initconst = {
122 .values = rk3368_defaults,
123 .num_values = ARRAY_SIZE(rk3368_defaults),
124 };
125
126 #define RK3399_GRF_SOC_CON7 0xe21c
127
128 static const struct rockchip_grf_value rk3399_defaults[] __initconst = {
129 {"jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12)},
130 };
131
132 static const struct rockchip_grf_info rk3399_grf __initconst = {
133 .values = rk3399_defaults,
134 .num_values = ARRAY_SIZE(rk3399_defaults),
135 };
136
137 #define DELAY_ONE_SECOND 0x16E3600
138
139 #define RV1126_GRF1_SDDETFLT_CON 0x10254
140 #define RV1126_GRF1_UART2RX_LOW_CON 0x10258
141 #define RV1126_GRF1_IOFUNC_CON1 0x10264
142 #define RV1126_GRF1_IOFUNC_CON3 0x1026C
143 #define RV1126_JTAG_GROUP0 0x0 /* mux to sdmmc */
144 #define RV1126_JTAG_GROUP1 0x1 /* mux to uart2 */
145 #define FORCE_JTAG_ENABLE 0x1
146 #define FORCE_JTAG_DISABLE 0x0
147
148 static const struct rockchip_grf_value rv1126_defaults[] __initconst = {
149 {"jtag group0 force", RV1126_GRF1_IOFUNC_CON3, HIWORD_UPDATE(FORCE_JTAG_DISABLE, 1, 4)},
150 {"jtag group1 force", RV1126_GRF1_IOFUNC_CON3, HIWORD_UPDATE(FORCE_JTAG_DISABLE, 1, 5)},
151 {"jtag group1 tms low delay", RV1126_GRF1_UART2RX_LOW_CON, DELAY_ONE_SECOND},
152 {"switch to jtag groupx", RV1126_GRF1_IOFUNC_CON1, HIWORD_UPDATE(RV1126_JTAG_GROUP0, 1, 15)},
153 {"jtag group0 switching delay", RV1126_GRF1_SDDETFLT_CON, DELAY_ONE_SECOND * 5},
154 };
155
156 static const struct rockchip_grf_info rv1126_grf __initconst = {
157 .values = rv1126_defaults,
158 .num_values = ARRAY_SIZE(rv1126_defaults),
159 };
160
161 static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
162 {
163 .compatible = "rockchip,px30-grf",
164 .data = (void *)&px30_grf,
165 },
166 {
167 .compatible = "rockchip,rk3036-grf",
168 .data = (void *)&rk3036_grf,
169 },
170 {
171 .compatible = "rockchip,rk3128-grf",
172 .data = (void *)&rk3128_grf,
173 },
174 {
175 .compatible = "rockchip,rk3228-grf",
176 .data = (void *)&rk3228_grf,
177 },
178 {
179 .compatible = "rockchip,rk3288-grf",
180 .data = (void *)&rk3288_grf,
181 },
182 {
183 .compatible = "rockchip,rk3308-grf",
184 .data = (void *)&rk3308_grf,
185 },
186 {
187 .compatible = "rockchip,rk3328-grf",
188 .data = (void *)&rk3328_grf,
189 },
190 {
191 .compatible = "rockchip,rk3368-grf",
192 .data = (void *)&rk3368_grf,
193 },
194 {
195 .compatible = "rockchip,rk3399-grf",
196 .data = (void *)&rk3399_grf,
197 },
198 {
199 .compatible = "rockchip,rv1126-grf",
200 .data = (void *)&rv1126_grf,
201 },
202 {},
203 };
204
rockchip_grf_init(void)205 static int __init rockchip_grf_init(void)
206 {
207 const struct rockchip_grf_info *grf_info;
208 const struct of_device_id *match;
209 struct device_node *np;
210 struct regmap *grf;
211 int ret, i;
212
213 np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match, &match);
214 if (!np) {
215 return -ENODEV;
216 }
217 if (!match || !match->data) {
218 pr_err("%s: missing grf data\n", __func__);
219 return -EINVAL;
220 }
221
222 grf_info = match->data;
223
224 grf = syscon_node_to_regmap(np);
225 if (IS_ERR(grf)) {
226 pr_err("%s: could not get grf syscon\n", __func__);
227 return PTR_ERR(grf);
228 }
229
230 for (i = 0; i < grf_info->num_values; i++) {
231 const struct rockchip_grf_value *val = &grf_info->values[i];
232
233 pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__, val->desc, val->reg, val->val);
234 ret = regmap_write(grf, val->reg, val->val);
235 if (ret < 0) {
236 pr_err("%s: write to %#6x failed with %d\n", __func__, val->reg, ret);
237 }
238 }
239
240 return 0;
241 }
242 postcore_initcall(rockchip_grf_init);
243
244 MODULE_DESCRIPTION("Rockchip GRF");
245 MODULE_LICENSE("GPL");
246