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1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *     http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 #ifndef WATCHDOG_H_
19 #define WATCHDOG_H_
20 #include "analog.h"
21 #include "gpio.h"
22 
23 /**
24  * @brief     start watchdog.
25  * @return    none
26  */
wd_start(void)27 static inline void wd_start(void)
28 {
29     BM_SET(reg_tmr_ctrl2, FLD_TMR_WD_EN);
30 }
31 
32 /**
33  * @brief     stop watchdog.
34  * @return    none
35  */
wd_stop(void)36 static inline void wd_stop(void)
37 {
38     BM_CLR(reg_tmr_ctrl2, FLD_TMR_WD_EN);
39 }
40 
41 /**
42  * @brief     clear watchdog.
43  * @return    none
44  */
wd_clear(void)45 static inline void wd_clear(void)
46 {
47     reg_tmr_sta = FLD_TMR_STA_WD | FLD_TMR_WD_CNT_CLR;
48 }
49 
50 /**
51  * @brief     clear watchdog timer tick cnt.
52  * @return    none
53  */
wd_clear_cnt(void)54 static inline void wd_clear_cnt(void)
55 {
56     reg_tmr_sta = FLD_TMR_WD_CNT_CLR;
57 }
58 
59 /**
60  * @brief     This function set the watchdog trigger time.
61  * 			  Because the lower 8bit of the wd timer register will always be 0, there will be an error ,
62 			  The time error = (0x00~0xff)/(APB clock frequency)
63  * @param[in] period_ms - The watchdog trigger time. Unit is  millisecond
64  * @return    none
65  * @attention  The clock source of watchdog comes from pclk, when pclk changes it needs to be reconfigured.
66  */
wd_set_interval_ms(unsigned int period_ms)67 static inline void wd_set_interval_ms(unsigned int period_ms)
68 {
69     static unsigned int tmp_period_ms = 0;
70     tmp_period_ms = period_ms * sys_clk.pclk * 1000;
71     reg_wt_target = tmp_period_ms;
72 }
73 
74 #endif
75