1 /*
2 * Copyright (c) 2022 Winner Microelectronics Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 /**
17 * @file wm_gpio.c
18 *
19 * @brief GPIO Driver Module
20 *
21 * @author dave
22 *
23 * Copyright (c) 2014 Winner Microelectronics Co., Ltd.
24 */
25 #include "wm_gpio.h"
26 #include "wm_regs.h"
27 #include "wm_irq.h"
28 #include "wm_osal.h"
29 #include "tls_common.h"
30 #include "wm_debug.h"
31 #include "wm_pmu.h"
32 #include "wm_gpio_afsel.h"
33
34 #ifndef WM_SWD_ENABLE
35 #define WM_SWD_ENABLE 1
36 #endif
wm_hspi_gpio_config(uint8_t numsel)37 void wm_hspi_gpio_config(uint8_t numsel)
38 {
39 switch (numsel) {
40 case 0:
41 tls_io_cfg_set(WM_IO_PB_06, WM_IO_OPTION3); /* CK */
42 tls_io_cfg_set(WM_IO_PB_07, WM_IO_OPTION3); /* INT */
43 tls_io_cfg_set(WM_IO_PB_09, WM_IO_OPTION3); /* CS */
44 tls_io_cfg_set(WM_IO_PB_10, WM_IO_OPTION3); /* DI */
45 tls_io_cfg_set(WM_IO_PB_11, WM_IO_OPTION3); /* DO */
46 break;
47
48 case 1: // W801
49 tls_io_cfg_set(WM_IO_PB_12, WM_IO_OPTION1); /* CK */
50 tls_io_cfg_set(WM_IO_PB_13, WM_IO_OPTION1); /* INT */
51 tls_io_cfg_set(WM_IO_PB_14, WM_IO_OPTION1); /* CS */
52 tls_io_cfg_set(WM_IO_PB_15, WM_IO_OPTION1); /* DI */
53 tls_io_cfg_set(WM_IO_PB_16, WM_IO_OPTION1); /* DO */
54 break;
55
56 default:
57 TLS_DBGPRT_ERR("highspeed spi gpio config error!");
58 break;
59 }
60 }
61
wm_spi_ck_config(enum tls_io_name io_name)62 void wm_spi_ck_config(enum tls_io_name io_name)
63 {
64 switch (io_name) {
65 case WM_IO_PB_01:
66 tls_io_cfg_set(io_name, WM_IO_OPTION2);
67 break;
68
69 case WM_IO_PB_02:
70 tls_io_cfg_set(io_name, WM_IO_OPTION2);
71 break;
72
73 case WM_IO_PB_15: // w801
74 tls_io_cfg_set(io_name, WM_IO_OPTION3);
75 break;
76
77 case WM_IO_PB_24: // w801
78 tls_io_cfg_set(io_name, WM_IO_OPTION1);
79 break;
80
81 default:
82 TLS_DBGPRT_ERR("spi ck afsel config error!");
83 return;
84 }
85 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_LSPI);
86 }
87
wm_spi_cs_config(enum tls_io_name io_name)88 void wm_spi_cs_config(enum tls_io_name io_name)
89 {
90 switch (io_name) {
91 case WM_IO_PA_00:
92 tls_io_cfg_set(io_name, WM_IO_OPTION2);
93 break;
94
95 case WM_IO_PB_04:
96 tls_io_cfg_set(io_name, WM_IO_OPTION1);
97 break;
98
99 case WM_IO_PB_14: // w801
100 tls_io_cfg_set(io_name, WM_IO_OPTION3);
101 break;
102
103 case WM_IO_PB_23: // w801
104 tls_io_cfg_set(io_name, WM_IO_OPTION1);
105 break;
106
107 default:
108 TLS_DBGPRT_ERR("spi cs afsel config error!");
109 break;
110 }
111 }
112
wm_spi_di_config(enum tls_io_name io_name)113 void wm_spi_di_config(enum tls_io_name io_name)
114 {
115 switch (io_name) {
116 case WM_IO_PB_00:
117 tls_io_cfg_set(io_name, WM_IO_OPTION2);
118 break;
119
120 case WM_IO_PB_03:
121 tls_io_cfg_set(io_name, WM_IO_OPTION2);
122 break;
123
124 case WM_IO_PB_16: // w801
125 tls_io_cfg_set(io_name, WM_IO_OPTION3);
126 break;
127
128 case WM_IO_PB_25: // w801
129 tls_io_cfg_set(io_name, WM_IO_OPTION1);
130 break;
131
132 default:
133 TLS_DBGPRT_ERR("spi di afsel config error!");
134 break;
135 }
136 }
137
wm_spi_do_config(enum tls_io_name io_name)138 void wm_spi_do_config(enum tls_io_name io_name)
139 {
140 switch (io_name) {
141 case WM_IO_PA_07:
142 tls_io_cfg_set(io_name, WM_IO_OPTION2);
143 break;
144
145 case WM_IO_PB_05:
146 tls_io_cfg_set(io_name, WM_IO_OPTION1);
147 break;
148
149 case WM_IO_PB_17: // w801
150 tls_io_cfg_set(io_name, WM_IO_OPTION3);
151 break;
152
153 case WM_IO_PB_26: // w801
154 tls_io_cfg_set(io_name, WM_IO_OPTION1);
155 break;
156
157 default:
158 TLS_DBGPRT_ERR("spi do afsel config error!");
159 break;
160 }
161 }
162
wm_sdio_host_config(uint8_t numsel)163 void wm_sdio_host_config(uint8_t numsel)
164 {
165 switch (numsel) {
166 case 0:
167 tls_io_cfg_set(WM_IO_PB_06, WM_IO_OPTION2); /* CK */
168 tls_io_cfg_set(WM_IO_PB_07, WM_IO_OPTION2); /* CMD */
169 tls_io_cfg_set(WM_IO_PB_08, WM_IO_OPTION2); /* D0 */
170 tls_io_cfg_set(WM_IO_PB_09, WM_IO_OPTION2); /* D1 */
171 tls_io_cfg_set(WM_IO_PB_10, WM_IO_OPTION2); /* D2 */
172 tls_io_cfg_set(WM_IO_PB_11, WM_IO_OPTION2); /* D3 */
173 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_SDIO_MASTER);
174 break;
175
176 case 1: // w801
177 tls_io_cfg_set(WM_IO_PA_09, WM_IO_OPTION1); /* CK */
178 tls_io_cfg_set(WM_IO_PA_10, WM_IO_OPTION1); /* CMD */
179 tls_io_cfg_set(WM_IO_PA_11, WM_IO_OPTION1); /* D0 */
180 tls_io_cfg_set(WM_IO_PA_12, WM_IO_OPTION1); /* D1 */
181 tls_io_cfg_set(WM_IO_PA_13, WM_IO_OPTION1); /* D2 */
182 tls_io_cfg_set(WM_IO_PA_14, WM_IO_OPTION1); /* D3 */
183 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_SDIO_MASTER);
184 break;
185
186 default:
187 TLS_DBGPRT_ERR("sdio host afsel config error!");
188 break;
189 }
190 }
191
wm_sdio_slave_config(uint8_t numsel)192 void wm_sdio_slave_config(uint8_t numsel)
193 {
194 switch (numsel) {
195 case 0:
196 tls_io_cfg_set(WM_IO_PB_06, WM_IO_OPTION4); /* CK */
197 tls_io_cfg_set(WM_IO_PB_07, WM_IO_OPTION4); /* CMD */
198 tls_io_cfg_set(WM_IO_PB_08, WM_IO_OPTION4); /* D0 */
199 tls_io_cfg_set(WM_IO_PB_09, WM_IO_OPTION4); /* D1 */
200 tls_io_cfg_set(WM_IO_PB_10, WM_IO_OPTION4); /* D2 */
201 tls_io_cfg_set(WM_IO_PB_11, WM_IO_OPTION4); /* D3 */
202 break;
203
204 default:
205 TLS_DBGPRT_ERR("sdio slave afsel config error!");
206 break;
207 }
208 }
209
wm_psram_config(uint8_t numsel)210 void wm_psram_config(uint8_t numsel)
211 {
212 switch (numsel) {
213 case 0:
214 tls_io_cfg_set(WM_IO_PB_00, WM_IO_OPTION4); /* CK */
215 tls_io_cfg_set(WM_IO_PB_01, WM_IO_OPTION4); /* CS */
216 tls_io_cfg_set(WM_IO_PB_02, WM_IO_OPTION4); /* D0 */
217 tls_io_cfg_set(WM_IO_PB_03, WM_IO_OPTION4); /* D1 */
218 tls_io_cfg_set(WM_IO_PB_04, WM_IO_OPTION4); /* D2 */
219 tls_io_cfg_set(WM_IO_PB_05, WM_IO_OPTION4); /* D3 */
220 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_PSRAM);
221 break;
222
223 case 1: // w801
224 tls_io_cfg_set(WM_IO_PA_15, WM_IO_OPTION1); /* CK */
225 tls_io_cfg_set(WM_IO_PB_27, WM_IO_OPTION1); /* CS */
226 tls_io_cfg_set(WM_IO_PB_02, WM_IO_OPTION4); /* D0 */
227 tls_io_cfg_set(WM_IO_PB_03, WM_IO_OPTION4); /* D1 */
228 tls_io_cfg_set(WM_IO_PB_04, WM_IO_OPTION4); /* D2 */
229 tls_io_cfg_set(WM_IO_PB_05, WM_IO_OPTION4); /* D3 */
230 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_PSRAM);
231 break;
232
233 default:
234 TLS_DBGPRT_ERR("psram afsel config error!");
235 break;
236 }
237 }
wm_uart0_tx_config(enum tls_io_name io_name)238 void wm_uart0_tx_config(enum tls_io_name io_name)
239 {
240 switch (io_name) {
241 case WM_IO_PB_19:
242 tls_io_cfg_set(io_name, WM_IO_OPTION1);
243 break;
244
245 case WM_IO_PB_27:
246 tls_io_cfg_set(io_name, WM_IO_OPTION2);
247 break;
248
249 default:
250 TLS_DBGPRT_ERR("uart0 tx afsel config error!");
251 return;
252 }
253 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART0);
254 }
255
wm_uart0_rx_config(enum tls_io_name io_name)256 void wm_uart0_rx_config(enum tls_io_name io_name)
257 {
258 switch (io_name) {
259 case WM_IO_PB_20:
260 tls_io_cfg_set(io_name, WM_IO_OPTION1);
261 tls_bitband_write(HR_GPIOB_DATA_PULLEN, 20, 0);
262 break;
263
264 default:
265 TLS_DBGPRT_ERR("uart0 rx afsel config error!");
266 return;
267 }
268 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART0);
269 }
270
wm_uart1_tx_config(enum tls_io_name io_name)271 void wm_uart1_tx_config(enum tls_io_name io_name)
272 {
273 switch (io_name) {
274 case WM_IO_PB_06:
275 tls_io_cfg_set(io_name, WM_IO_OPTION1);
276 break;
277
278 default:
279 TLS_DBGPRT_ERR("uart1 tx afsel config error!");
280 return;
281 }
282 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART1);
283 }
284
wm_uart1_rx_config(enum tls_io_name io_name)285 void wm_uart1_rx_config(enum tls_io_name io_name)
286 {
287 switch (io_name) {
288 case WM_IO_PB_07:
289 tls_io_cfg_set(io_name, WM_IO_OPTION1);
290 tls_bitband_write(HR_GPIOB_DATA_PULLEN, 7, 0);
291 break;
292
293 case WM_IO_PB_16:
294 tls_io_cfg_set(io_name, WM_IO_OPTION4);
295 tls_bitband_write(HR_GPIOB_DATA_PULLEN, 16, 0);
296 break;
297
298 default:
299 TLS_DBGPRT_ERR("uart1 rx afsel config error!");
300 return;
301 }
302 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART1);
303 }
304
wm_uart1_rts_config(enum tls_io_name io_name)305 void wm_uart1_rts_config(enum tls_io_name io_name)
306 {
307 switch (io_name) {
308 case WM_IO_PB_19:
309 tls_io_cfg_set(io_name, WM_IO_OPTION3);
310 break;
311 case WM_IO_PA_02:
312 tls_io_cfg_set(io_name, WM_IO_OPTION1);
313 break;
314
315 default:
316 TLS_DBGPRT_ERR("uart1 rts afsel config error!");
317 return;
318 }
319 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART1);
320 }
321
wm_uart1_cts_config(enum tls_io_name io_name)322 void wm_uart1_cts_config(enum tls_io_name io_name)
323 {
324 switch (io_name) {
325 case WM_IO_PB_20:
326 tls_io_cfg_set(io_name, WM_IO_OPTION3);
327 break;
328 case WM_IO_PA_03:
329 tls_io_cfg_set(io_name, WM_IO_OPTION1);
330 break;
331 default:
332 TLS_DBGPRT_ERR("uart1 cts afsel config error!");
333 return;
334 }
335 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART1);
336 }
337
wm_uart2_tx_scio_config(enum tls_io_name io_name)338 void wm_uart2_tx_scio_config(enum tls_io_name io_name)
339 {
340 switch (io_name) {
341 case WM_IO_PB_02:
342 tls_io_cfg_set(io_name, WM_IO_OPTION3);
343 break;
344 case WM_IO_PA_02:
345 tls_io_cfg_set(io_name, WM_IO_OPTION2);
346 break;
347
348 default:
349 TLS_DBGPRT_ERR("uart2 tx afsel config error!");
350 return;
351 }
352 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART2);
353 }
354
wm_uart2_rx_config(enum tls_io_name io_name)355 void wm_uart2_rx_config(enum tls_io_name io_name)
356 {
357 switch (io_name) {
358 case WM_IO_PB_03:
359 tls_io_cfg_set(io_name, WM_IO_OPTION3);
360 tls_bitband_write(HR_GPIOB_DATA_PULLEN, 3, 0);
361 break;
362 case WM_IO_PA_03:
363 tls_io_cfg_set(io_name, WM_IO_OPTION2);
364 tls_bitband_write(HR_GPIOA_DATA_PULLEN, 3, 0);
365 break;
366
367 default:
368 TLS_DBGPRT_ERR("uart2 rx afsel config error!");
369 return;
370 }
371 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART2);
372 }
373
wm_uart2_rts_scclk_config(enum tls_io_name io_name)374 void wm_uart2_rts_scclk_config(enum tls_io_name io_name)
375 {
376 switch (io_name) {
377 case WM_IO_PB_04:
378 tls_io_cfg_set(io_name, WM_IO_OPTION2);
379 break;
380 case WM_IO_PA_05:
381 tls_io_cfg_set(io_name, WM_IO_OPTION2);
382 break;
383
384 default:
385 TLS_DBGPRT_ERR("uart2 rts afsel config error!");
386 return;
387 }
388 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART2);
389 }
390
wm_uart2_cts_config(enum tls_io_name io_name)391 void wm_uart2_cts_config(enum tls_io_name io_name)
392 {
393 switch (io_name) {
394 case WM_IO_PB_05:
395 tls_io_cfg_set(io_name, WM_IO_OPTION2);
396 break;
397 case WM_IO_PA_06:
398 tls_io_cfg_set(io_name, WM_IO_OPTION2);
399 break;
400
401 default:
402 TLS_DBGPRT_ERR("uart2 cts afsel config error!");
403 return;
404 }
405 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART2);
406 }
407
wm_uart3_tx_config(enum tls_io_name io_name)408 void wm_uart3_tx_config(enum tls_io_name io_name)
409 {
410 switch (io_name) {
411 case WM_IO_PB_00:
412 tls_io_cfg_set(io_name, WM_IO_OPTION3);
413 break;
414 case WM_IO_PA_05:
415 tls_io_cfg_set(io_name, WM_IO_OPTION1);
416 break;
417
418 default:
419 TLS_DBGPRT_ERR("uart3 tx afsel config error!");
420 return;
421 }
422 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART3);
423 }
424
wm_uart3_rx_config(enum tls_io_name io_name)425 void wm_uart3_rx_config(enum tls_io_name io_name)
426 {
427 switch (io_name) {
428 case WM_IO_PB_01:
429 tls_io_cfg_set(io_name, WM_IO_OPTION3);
430 tls_bitband_write(HR_GPIOB_DATA_PULLEN, 1, 0);
431 break;
432 case WM_IO_PA_06:
433 tls_io_cfg_set(io_name, WM_IO_OPTION1);
434 tls_bitband_write(HR_GPIOA_DATA_PULLEN, 6, 0);
435 break;
436
437 default:
438 TLS_DBGPRT_ERR("uart3 rx afsel config error!");
439 return;
440 }
441 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART3);
442 }
443
wm_uart3_rts_config(enum tls_io_name io_name)444 void wm_uart3_rts_config(enum tls_io_name io_name)
445 {
446 switch (io_name) {
447 case WM_IO_PA_02:
448 tls_io_cfg_set(io_name, WM_IO_OPTION4);
449 break;
450
451 default:
452 TLS_DBGPRT_ERR("uart1 rts afsel config error!");
453 return;
454 }
455 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART3);
456 }
457
wm_uart3_cts_config(enum tls_io_name io_name)458 void wm_uart3_cts_config(enum tls_io_name io_name)
459 {
460 switch (io_name) {
461 case WM_IO_PA_03:
462 tls_io_cfg_set(io_name, WM_IO_OPTION4);
463 break;
464 default:
465 TLS_DBGPRT_ERR("uart1 cts afsel config error!");
466 return;
467 }
468 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART3);
469 }
470
wm_uart4_tx_config(enum tls_io_name io_name)471 void wm_uart4_tx_config(enum tls_io_name io_name)
472 {
473 switch (io_name) {
474 case WM_IO_PB_04:
475 tls_io_cfg_set(io_name, WM_IO_OPTION3);
476 break;
477 case WM_IO_PA_08:
478 tls_io_cfg_set(io_name, WM_IO_OPTION2);
479 break;
480
481 default:
482 TLS_DBGPRT_ERR("uart4 tx afsel config error!");
483 return;
484 }
485 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART4);
486 }
487
wm_uart4_rx_config(enum tls_io_name io_name)488 void wm_uart4_rx_config(enum tls_io_name io_name)
489 {
490 switch (io_name) {
491 case WM_IO_PB_05:
492 tls_io_cfg_set(io_name, WM_IO_OPTION3);
493 tls_bitband_write(HR_GPIOB_DATA_PULLEN, 5, 0);
494 break;
495 case WM_IO_PA_09:
496 tls_io_cfg_set(io_name, WM_IO_OPTION2);
497 tls_bitband_write(HR_GPIOA_DATA_PULLEN, 9, 0);
498 break;
499
500 default:
501 TLS_DBGPRT_ERR("uart4 rx afsel config error!");
502 return;
503 }
504 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART4);
505 }
506
wm_uart4_rts_config(enum tls_io_name io_name)507 void wm_uart4_rts_config(enum tls_io_name io_name)
508 {
509 switch (io_name) {
510 case WM_IO_PA_05:
511 tls_io_cfg_set(io_name, WM_IO_OPTION4);
512 break;
513 case WM_IO_PA_10:
514 tls_io_cfg_set(io_name, WM_IO_OPTION2);
515 break;
516
517 default:
518 TLS_DBGPRT_ERR("uart1 rts afsel config error!");
519 return;
520 }
521 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART4);
522 }
523
wm_uart4_cts_config(enum tls_io_name io_name)524 void wm_uart4_cts_config(enum tls_io_name io_name)
525 {
526 switch (io_name) {
527 case WM_IO_PA_06:
528 tls_io_cfg_set(io_name, WM_IO_OPTION4);
529 break;
530 case WM_IO_PA_11:
531 tls_io_cfg_set(io_name, WM_IO_OPTION2);
532 break;
533 default:
534 TLS_DBGPRT_ERR("uart1 cts afsel config error!");
535 return;
536 }
537 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART4);
538 }
539
wm_uart5_tx_config(enum tls_io_name io_name)540 void wm_uart5_tx_config(enum tls_io_name io_name)
541 {
542 switch (io_name) {
543 case WM_IO_PA_12:
544 tls_io_cfg_set(io_name, WM_IO_OPTION2);
545 break;
546 case WM_IO_PA_08:
547 tls_io_cfg_set(io_name, WM_IO_OPTION3);
548 break;
549 case WM_IO_PB_18:
550 tls_io_cfg_set(io_name, WM_IO_OPTION1);
551 break;
552
553 default:
554 TLS_DBGPRT_ERR("uart4 tx afsel config error!");
555 return;
556 }
557 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART5);
558 }
559
wm_uart5_rx_config(enum tls_io_name io_name)560 void wm_uart5_rx_config(enum tls_io_name io_name)
561 {
562 switch (io_name) {
563 case WM_IO_PA_13:
564 tls_io_cfg_set(io_name, WM_IO_OPTION2);
565 tls_bitband_write(HR_GPIOA_DATA_PULLEN, 13, 0);
566 break;
567 case WM_IO_PA_09:
568 tls_io_cfg_set(io_name, WM_IO_OPTION3);
569 tls_bitband_write(HR_GPIOA_DATA_PULLEN, 9, 0);
570 break;
571 case WM_IO_PB_17:
572 tls_io_cfg_set(io_name, WM_IO_OPTION1);
573 tls_bitband_write(HR_GPIOB_DATA_PULLEN, 17, 0);
574 break;
575 default:
576 TLS_DBGPRT_ERR("uart4 rx afsel config error!");
577 return;
578 }
579 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART5);
580 }
581
wm_uart5_rts_config(enum tls_io_name io_name)582 void wm_uart5_rts_config(enum tls_io_name io_name)
583 {
584 switch (io_name) {
585 case WM_IO_PB_12:
586 tls_io_cfg_set(io_name, WM_IO_OPTION3);
587 break;
588 case WM_IO_PA_14:
589 tls_io_cfg_set(io_name, WM_IO_OPTION2);
590 break;
591
592 default:
593 TLS_DBGPRT_ERR("uart1 rts afsel config error!");
594 return;
595 }
596 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART5);
597 }
598
wm_uart5_cts_config(enum tls_io_name io_name)599 void wm_uart5_cts_config(enum tls_io_name io_name)
600 {
601 switch (io_name) {
602 case WM_IO_PB_13:
603 tls_io_cfg_set(io_name, WM_IO_OPTION3);
604 break;
605 case WM_IO_PA_15:
606 tls_io_cfg_set(io_name, WM_IO_OPTION2);
607 break;
608 default:
609 TLS_DBGPRT_ERR("uart1 cts afsel config error!");
610 return;
611 }
612 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_UART5);
613 }
614
wm_i2s_ck_config(enum tls_io_name io_name)615 void wm_i2s_ck_config(enum tls_io_name io_name)
616 {
617 switch (io_name) {
618 case WM_IO_PA_04:
619 tls_io_cfg_set(io_name, WM_IO_OPTION4);
620 break;
621
622 case WM_IO_PB_08:
623 tls_io_cfg_set(io_name, WM_IO_OPTION1);
624 break;
625
626 case WM_IO_PA_08:
627 tls_io_cfg_set(io_name, WM_IO_OPTION4);
628 break;
629
630 case WM_IO_PB_12:
631 tls_io_cfg_set(io_name, WM_IO_OPTION4);
632 break;
633
634 default:
635 TLS_DBGPRT_ERR("i2s master ck afsel config error!");
636 return;
637 }
638 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_I2S);
639 }
640
wm_i2s_ws_config(enum tls_io_name io_name)641 void wm_i2s_ws_config(enum tls_io_name io_name)
642 {
643 switch (io_name) {
644 case WM_IO_PA_01:
645 tls_io_cfg_set(io_name, WM_IO_OPTION4);
646 break;
647
648 case WM_IO_PB_09:
649 tls_io_cfg_set(io_name, WM_IO_OPTION1);
650 break;
651
652 case WM_IO_PA_09:
653 tls_io_cfg_set(io_name, WM_IO_OPTION4);
654 break;
655
656 case WM_IO_PB_13:
657 tls_io_cfg_set(io_name, WM_IO_OPTION4);
658 break;
659
660 default:
661 return;
662 }
663 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_I2S);
664 }
665
wm_i2s_do_config(enum tls_io_name io_name)666 void wm_i2s_do_config(enum tls_io_name io_name)
667 {
668 switch (io_name) {
669 case WM_IO_PA_00:
670 tls_io_cfg_set(io_name, WM_IO_OPTION4);
671 break;
672
673 case WM_IO_PB_11:
674 tls_io_cfg_set(io_name, WM_IO_OPTION1);
675 break;
676
677 case WM_IO_PA_10:
678 tls_io_cfg_set(io_name, WM_IO_OPTION4);
679 break;
680
681 case WM_IO_PB_14:
682 tls_io_cfg_set(io_name, WM_IO_OPTION4);
683 break;
684
685 default:
686 TLS_DBGPRT_ERR("i2s master do afsel config error!");
687 return;
688 }
689 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_I2S);
690 }
691
wm_i2s_di_config(enum tls_io_name io_name)692 void wm_i2s_di_config(enum tls_io_name io_name)
693 {
694 switch (io_name) {
695 case WM_IO_PA_07:
696 tls_io_cfg_set(io_name, WM_IO_OPTION4);
697 break;
698
699 case WM_IO_PB_10:
700 tls_io_cfg_set(io_name, WM_IO_OPTION1);
701 break;
702
703 case WM_IO_PA_11:
704 tls_io_cfg_set(io_name, WM_IO_OPTION4);
705 break;
706
707 case WM_IO_PB_15:
708 tls_io_cfg_set(io_name, WM_IO_OPTION4);
709 break;
710
711 default:
712 TLS_DBGPRT_ERR("i2s slave di afsel config error!");
713 return;
714 }
715 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_I2S);
716 }
717
wm_i2s_mclk_config(enum tls_io_name io_name)718 void wm_i2s_mclk_config(enum tls_io_name io_name)
719 {
720 switch (io_name) {
721 case WM_IO_PA_00:
722 tls_io_cfg_set(io_name, WM_IO_OPTION1);
723 break;
724
725 case WM_IO_PA_07:
726 tls_io_cfg_set(io_name, WM_IO_OPTION3);
727 break;
728
729 case WM_IO_PB_17:
730 tls_io_cfg_set(io_name, WM_IO_OPTION4);
731 break;
732
733 default:
734 TLS_DBGPRT_ERR("i2s mclk afsel config error!");
735 return;
736 }
737 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_I2S);
738 }
739
wm_i2s_extclk_config(enum tls_io_name io_name)740 void wm_i2s_extclk_config(enum tls_io_name io_name)
741 {
742 switch (io_name) {
743 case WM_IO_PA_07:
744 tls_io_cfg_set(io_name, WM_IO_OPTION3);
745 break;
746 case WM_IO_PB_17:
747 tls_io_cfg_set(io_name, WM_IO_OPTION4);
748 break;
749
750 default:
751 TLS_DBGPRT_ERR("i2s extclk afsel config error!");
752 return;
753 }
754 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_I2S);
755 }
756
wm_i2c_scl_config(enum tls_io_name io_name)757 void wm_i2c_scl_config(enum tls_io_name io_name)
758 {
759 switch (io_name) {
760 case WM_IO_PA_01:
761 tls_gpio_cfg(io_name, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH);
762 tls_io_cfg_set(io_name, WM_IO_OPTION2);
763 break;
764
765 case WM_IO_PB_20:
766 tls_gpio_cfg(io_name, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH);
767 tls_io_cfg_set(io_name, WM_IO_OPTION4);
768 break;
769
770 default:
771 TLS_DBGPRT_ERR("i2c scl afsel config error!");
772 return;
773 }
774 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_I2C);
775 }
776
wm_i2c_sda_config(enum tls_io_name io_name)777 void wm_i2c_sda_config(enum tls_io_name io_name)
778 {
779 switch (io_name) {
780 case WM_IO_PA_04:
781 tls_gpio_cfg(io_name, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH);
782 tls_io_cfg_set(io_name, WM_IO_OPTION2);
783 break;
784
785 case WM_IO_PB_19:
786 tls_gpio_cfg(io_name, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH);
787 tls_io_cfg_set(io_name, WM_IO_OPTION4);
788 break;
789
790 default:
791 TLS_DBGPRT_ERR("i2c sda afsel config error!");
792 return;
793 }
794 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_I2C);
795 }
796
wm_pwm0_config(enum tls_io_name io_name)797 void wm_pwm0_config(enum tls_io_name io_name)
798 {
799 switch (io_name) {
800 case WM_IO_PB_00:
801 tls_io_cfg_set(io_name, WM_IO_OPTION1);
802 break;
803
804 case WM_IO_PB_19:
805 tls_io_cfg_set(io_name, WM_IO_OPTION2);
806 break;
807
808 case WM_IO_PB_12:
809 tls_io_cfg_set(io_name, WM_IO_OPTION2);
810 break;
811
812 case WM_IO_PA_02:
813 tls_io_cfg_set(io_name, WM_IO_OPTION3);
814 break;
815
816 case WM_IO_PA_10:
817 tls_io_cfg_set(io_name, WM_IO_OPTION3);
818 break;
819
820 default:
821 TLS_DBGPRT_ERR("pwm0 afsel config error!");
822 return;
823 }
824 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_PWM);
825 }
826
wm_pwm1_config(enum tls_io_name io_name)827 void wm_pwm1_config(enum tls_io_name io_name)
828 {
829 switch (io_name) {
830 case WM_IO_PB_01:
831 tls_io_cfg_set(io_name, WM_IO_OPTION1);
832 break;
833
834 case WM_IO_PB_20:
835 tls_io_cfg_set(io_name, WM_IO_OPTION2);
836 break;
837
838 case WM_IO_PA_03:
839 tls_io_cfg_set(io_name, WM_IO_OPTION3);
840 break;
841 case WM_IO_PA_11:
842 tls_io_cfg_set(io_name, WM_IO_OPTION3);
843 break;
844 case WM_IO_PB_13:
845 tls_io_cfg_set(io_name, WM_IO_OPTION2);
846 break;
847
848 default:
849 TLS_DBGPRT_ERR("pwm1 afsel config error!");
850 return;
851 }
852 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_PWM);
853 }
854
wm_pwm2_config(enum tls_io_name io_name)855 void wm_pwm2_config(enum tls_io_name io_name)
856 {
857 switch (io_name) {
858 case WM_IO_PA_00:
859 tls_io_cfg_set(io_name, WM_IO_OPTION3);
860 break;
861
862 case WM_IO_PB_02:
863 tls_io_cfg_set(io_name, WM_IO_OPTION1);
864 break;
865
866 case WM_IO_PA_12:
867 tls_io_cfg_set(io_name, WM_IO_OPTION3);
868 break;
869
870 case WM_IO_PB_14:
871 tls_io_cfg_set(io_name, WM_IO_OPTION2);
872 break;
873
874 case WM_IO_PB_24:
875 tls_io_cfg_set(io_name, WM_IO_OPTION2);
876 break;
877
878 default:
879 TLS_DBGPRT_ERR("pwm2 afsel config error!");
880 return;
881 }
882 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_PWM);
883 }
884
wm_pwm3_config(enum tls_io_name io_name)885 void wm_pwm3_config(enum tls_io_name io_name)
886 {
887 switch (io_name) {
888 case WM_IO_PA_01:
889 tls_io_cfg_set(io_name, WM_IO_OPTION3);
890 break;
891
892 case WM_IO_PB_03:
893 tls_io_cfg_set(io_name, WM_IO_OPTION1);
894 break;
895
896 case WM_IO_PA_13:
897 tls_io_cfg_set(io_name, WM_IO_OPTION3);
898 break;
899
900 case WM_IO_PB_15:
901 tls_io_cfg_set(io_name, WM_IO_OPTION2);
902 break;
903
904 case WM_IO_PB_25:
905 tls_io_cfg_set(io_name, WM_IO_OPTION2);
906 break;
907
908 default:
909 TLS_DBGPRT_ERR("pwm3 afsel config error!");
910 return;
911 }
912 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_PWM);
913 }
914
wm_pwm4_config(enum tls_io_name io_name)915 void wm_pwm4_config(enum tls_io_name io_name)
916 {
917 switch (io_name) {
918 case WM_IO_PA_04:
919 tls_io_cfg_set(io_name, WM_IO_OPTION3);
920 break;
921
922 case WM_IO_PA_07:
923 tls_io_cfg_set(io_name, WM_IO_OPTION1);
924 break;
925 case WM_IO_PA_14:
926 tls_io_cfg_set(io_name, WM_IO_OPTION3);
927 break;
928 case WM_IO_PB_16:
929 tls_io_cfg_set(io_name, WM_IO_OPTION2);
930 break;
931 case WM_IO_PB_26:
932 tls_io_cfg_set(io_name, WM_IO_OPTION2);
933 break;
934
935 default:
936 TLS_DBGPRT_ERR("pwm4 afsel config error!");
937 return;
938 }
939 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_PWM);
940 }
941
wm_pwmbrk_config(enum tls_io_name io_name)942 void wm_pwmbrk_config(enum tls_io_name io_name)
943 {
944 switch (io_name) {
945 case WM_IO_PB_08:
946 tls_io_cfg_set(io_name, WM_IO_OPTION3);
947 break;
948 case WM_IO_PA_05:
949 tls_io_cfg_set(io_name, WM_IO_OPTION3);
950 break;
951 case WM_IO_PA_08:
952 tls_io_cfg_set(io_name, WM_IO_OPTION1);
953 break;
954
955 case WM_IO_PA_15:
956 tls_io_cfg_set(io_name, WM_IO_OPTION3);
957 break;
958
959 case WM_IO_PB_17:
960 tls_io_cfg_set(io_name, WM_IO_OPTION2);
961 break;
962
963 default:
964 TLS_DBGPRT_ERR("pwmbrk afsel config error!");
965 return;
966 }
967 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_PWM);
968 }
969
wm_swd_config(bool enable)970 void wm_swd_config(bool enable)
971 {
972 if (enable) {
973 tls_io_cfg_set(WM_IO_PA_01, WM_IO_OPTION1);
974 tls_io_cfg_set(WM_IO_PA_04, WM_IO_OPTION1);
975 } else {
976 tls_io_cfg_set(WM_IO_PA_01, WM_IO_OPTION5);
977 tls_io_cfg_set(WM_IO_PA_04, WM_IO_OPTION5);
978 }
979 }
980
wm_adc_config(u8 Channel)981 void wm_adc_config(u8 Channel)
982 {
983 switch (Channel) {
984 case 0:
985 tls_io_cfg_set(WM_IO_PA_01, WM_IO_OPTION6);
986 break;
987
988 case 1:
989 tls_io_cfg_set(WM_IO_PA_04, WM_IO_OPTION6);
990 break;
991
992 case 2:
993 tls_io_cfg_set(WM_IO_PA_03, WM_IO_OPTION6);
994 break;
995
996 case 3:
997 tls_io_cfg_set(WM_IO_PA_02, WM_IO_OPTION6);
998 break;
999
1000 default:
1001 return;
1002 }
1003 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_SDADC);
1004 }
1005
wm_touch_sensor_config(enum tls_io_name io_name)1006 void wm_touch_sensor_config(enum tls_io_name io_name)
1007 {
1008 switch (io_name) {
1009 case WM_IO_PA_07: /* touch sensor 1 */
1010 case WM_IO_PA_09: /* touch sensor 2 */
1011 case WM_IO_PA_10: /* touch sensor 3 */
1012 case WM_IO_PB_00: /* touch sensor 4 */
1013 case WM_IO_PB_01: /* touch sensor 5 */
1014 case WM_IO_PB_02: /* touch sensor 6 */
1015 case WM_IO_PB_03: /* touch sensor 7 */
1016 case WM_IO_PB_04: /* touch sensor 8 */
1017 case WM_IO_PB_05: /* touch sensor 9 */
1018 case WM_IO_PB_06: /* touch sensor 10 */
1019 case WM_IO_PB_07: /* touch sensor 11 */
1020 case WM_IO_PB_08: /* touch sensor 12 */
1021 case WM_IO_PB_09: /* touch sensor 13 */
1022 case WM_IO_PA_12: /* touch sensor 14 */
1023 case WM_IO_PA_14: /* touch sensor 15 */
1024 tls_io_cfg_set(io_name, WM_IO_OPTION7);
1025 break;
1026 default:
1027 return;
1028 }
1029 tls_open_peripheral_clock(TLS_PERIPHERAL_TYPE_TOUCH_SENSOR);
1030 }
1031
wm_gpio_af_disable(void)1032 void wm_gpio_af_disable(void)
1033 {
1034 tls_reg_write32(HR_GPIOA_DATA_DIR, 0x0);
1035 tls_reg_write32(HR_GPIOB_DATA_DIR, 0x0);
1036
1037 #if WM_SWD_ENABLE
1038 tls_reg_write32(HR_GPIOA_AFSEL, 0x12); /* PA1:JTAG_CK,PA4:JTAG_SWO */
1039 #else
1040 tls_reg_write32(HR_GPIOA_AFSEL, 0x0);
1041 #endif
1042 tls_reg_write32(HR_GPIOB_AFSEL, 0x0);
1043
1044 tls_reg_write32(HR_GPIOA_DATA_PULLEN, 0xffff);
1045 tls_reg_write32(HR_GPIOB_DATA_PULLEN, 0xffffffff);
1046 }