1/* ESP32 Linker Script Memory Layout 2 3 This file describes the memory layout (memory blocks) as virtual 4 memory addresses. 5 6 esp32.project.ld contains output sections to link compiler output 7 into these memory blocks. 8 9 *** 10 11 This linker script is passed through the C preprocessor to include 12 configuration options. 13 14 Please use preprocessor features sparingly! Restrict 15 to simple macros with numeric values, and/or #if/#endif blocks. 16*/ 17#include "sdkconfig.h" 18 19/* If BT is not built at all */ 20#ifndef CONFIG_BT_RESERVE_DRAM 21#define CONFIG_BT_RESERVE_DRAM 0 22#endif 23 24#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC 25#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) 26#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) 27#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) 28#else 29#define ESP_BOOTLOADER_RESERVE_RTC 0 30#endif 31 32#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE) 33 34ASSERT((CONFIG_ESP32_FIXED_STATIC_RAM_SIZE <= 0x2c200), 35 "Fixed static ram data does not fit.") 36 37#define DRAM0_0_SEG_LEN CONFIG_ESP32_FIXED_STATIC_RAM_SIZE 38 39#else 40#define DRAM0_0_SEG_LEN 0x2c200 41#endif 42 43MEMORY 44{ 45 /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length 46 of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but 47 are connected to the data port of the CPU and eg allow bytewise access. */ 48 49 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ 50 iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 51 52#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS 53 /* Even though the segment name is iram, it is actually mapped to flash 54 */ 55 iram0_2_seg (RX) : org = 0x400D0020, len = 0x330000-0x20 56 57 /* 58 (0x20 offset above is a convenience for the app binary image generation. 59 Flash cache has 64KB pages. The .bin file which is flashed to the chip 60 has a 0x18 byte file header, and each segment has a 0x08 byte segment 61 header. Setting this offset makes it simple to meet the flash cache MMU's 62 constraint that (paddr % 64KB == vaddr % 64KB).) 63 */ 64#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS 65 66 67 /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. 68 69 Enabling Bluetooth & Trace Memory features in menuconfig will decrease 70 the amount of RAM available. 71 72 Note: Length of this section *should* be 0x50000, and this extra DRAM is available 73 in heap at runtime. However due to static ROM memory usage at this 176KB mark, the 74 additional static memory temporarily cannot be used. 75 */ 76 dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM, 77 len = DRAM0_0_SEG_LEN - CONFIG_BT_RESERVE_DRAM 78 79#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS 80 /* Flash mapped constant data */ 81 drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20 82 83 /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ 84#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS 85 86 /* RTC fast memory (executable). Persists over deep sleep. 87 */ 88 rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 89 90 /* RTC fast memory (same block as above), viewed from data bus */ 91 rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC 92 93 /* RTC slow memory (data accessible). Persists over deep sleep. 94 95 Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled. 96 */ 97 rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM, 98 len = 0x2000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM 99 100 /* external memory ,including data and text */ 101 extern_ram_seg(RWX) : org = 0x3F800000, 102 len = 0x400000 103} 104 105#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE) 106/* static data ends at defined address */ 107_static_data_end = 0x3FFB0000 + DRAM0_0_SEG_LEN; 108#else 109_static_data_end = _bss_end; 110#endif 111 112/* Heap ends at top of dram0_0_seg */ 113_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM; 114 115_data_seg_org = ORIGIN(rtc_data_seg); 116 117/* The lines below define location alias for .rtc.data section based on Kconfig option. 118 When the option is not defined then use slow memory segment 119 else the data will be placed in fast memory segment */ 120#ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM 121REGION_ALIAS("rtc_data_location", rtc_slow_seg ); 122#else 123REGION_ALIAS("rtc_data_location", rtc_data_seg ); 124#endif 125 126#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS 127 REGION_ALIAS("default_code_seg", iram0_2_seg); 128#else 129 REGION_ALIAS("default_code_seg", iram0_0_seg); 130#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS 131 132#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS 133 REGION_ALIAS("default_rodata_seg", drom0_0_seg); 134#else 135 REGION_ALIAS("default_rodata_seg", dram0_0_seg); 136#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS 137 138/** 139 * If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must 140 * also be first in the segment. 141 */ 142#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS 143 ASSERT(_rodata_start == ORIGIN(default_rodata_seg), 144 ".flash.appdesc section must be placed at the beginning of the rodata segment.") 145#endif 146