1 /* 2 * Copyright (c) 2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 /* 9 * Note: 10 * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, 11 * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that 12 * expected SoC function can be enabled on these IOs. 13 * 14 */ 15 #include "board.h" 16 init_uart_pins(UART_Type * ptr)17void init_uart_pins(UART_Type *ptr) 18 { 19 if (ptr == HPM_UART0) { 20 HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; 21 HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; 22 /* PY port IO needs to configure PIOC */ 23 HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07; 24 HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06; 25 } else if (ptr == HPM_UART1) { 26 HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_UART1_TXD; 27 HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_UART1_RXD; 28 } else if (ptr == HPM_UART2) { 29 HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD; 30 HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD; 31 } else if (ptr == HPM_PUART) { 32 HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART_RXD; 33 HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART_TXD; 34 } 35 } 36 init_i2c_pins_as_gpio(I2C_Type * ptr)37void init_i2c_pins_as_gpio(I2C_Type *ptr) 38 { 39 if (ptr == HPM_I2C0) { 40 /* I2C0 */ 41 HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_GPIO_B_22; 42 HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23; 43 } else { 44 while (1) { 45 } 46 } 47 } 48 init_i2c_pins(I2C_Type * ptr)49void init_i2c_pins(I2C_Type *ptr) 50 { 51 if (ptr == HPM_I2C0) { 52 HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_I2C0_SCL 53 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 54 HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_I2C0_SDA 55 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 56 HPM_IOC->PAD[IOC_PAD_PB22].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 57 HPM_IOC->PAD[IOC_PAD_PB23].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 58 } else if (ptr == HPM_I2C3) { 59 HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_I2C3_SCL 60 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 61 HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_I2C3_SDA 62 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 63 HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 64 HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 65 } else { 66 while (1) { 67 } 68 } 69 } 70 init_sdm_pins(void)71void init_sdm_pins(void) 72 { 73 /* channel 3 */ 74 HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_SDM0_CLK_3; 75 HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_SDM0_DAT_3; 76 } 77 init_gpio_pins(void)78void init_gpio_pins(void) 79 { 80 /* configure pad setting: pull enable and pull up, schmitt trigger enable */ 81 /* enable schmitt trigger to eliminate jitter of pin used as button */ 82 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); 83 84 /* Button */ 85 #ifdef USING_GPIO0_FOR_GPIOZ 86 HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; 87 HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; 88 /* PZ port IO needs to configure BIOC as well */ 89 HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02; 90 #endif 91 } 92 init_spi_pins(SPI_Type * ptr)93void init_spi_pins(SPI_Type *ptr) 94 { 95 if (ptr == HPM_SPI1) { 96 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SPI1_CSN; 97 HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI; 98 HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO; 99 HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); 100 } 101 } 102 init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)103void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) 104 { 105 if (ptr == HPM_SPI1) { 106 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_GPIO_B_02; 107 HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI; 108 HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO; 109 HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); 110 } 111 } 112 init_pins(void)113void init_pins(void) 114 { 115 #ifdef BOARD_CONSOLE_BASE 116 init_uart_pins(BOARD_CONSOLE_BASE); 117 #endif 118 } 119 init_gptmr_pins(GPTMR_Type * ptr)120void init_gptmr_pins(GPTMR_Type *ptr) 121 { 122 if (ptr == HPM_GPTMR2) { 123 HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0; 124 HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0; 125 HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_GPTMR2_COMP_1; 126 } 127 } 128 init_hall_trgm_pins(void)129void init_hall_trgm_pins(void) 130 { 131 HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_TRGM0_P_06; 132 HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_TRGM0_P_07; 133 HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PB28_FUNC_CTL_TRGM0_P_08; 134 } 135 init_qei_trgm_pins(void)136void init_qei_trgm_pins(void) 137 { 138 HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_TRGM0_P_06; 139 HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_TRGM0_P_07; 140 } 141 init_butn_pins(void)142void init_butn_pins(void) 143 { 144 /* HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; */ 145 /* HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; */ 146 } 147 init_acmp_pins(void)148void init_acmp_pins(void) 149 { 150 /* configure to CMP1_INN5 function */ 151 HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 152 /* configure to ACMP_COMP_1 function */ 153 HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_ACMP_COMP_1; 154 } 155 init_pwm_pins(PWM_Type * ptr)156void init_pwm_pins(PWM_Type *ptr) 157 { 158 if (ptr == HPM_PWM0) { 159 HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_PWM0_P_5; 160 HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_PWM0_P_3; 161 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_PWM0_P_1; 162 HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_PWM0_P_4; 163 HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_PWM0_P_2; 164 HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_PWM0_P_0; 165 } 166 } 167 init_hrpwm_pins(PWM_Type * ptr)168void init_hrpwm_pins(PWM_Type *ptr) 169 { 170 if (ptr == HPM_PWM1) { 171 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_PWM1_P_0; 172 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_PWM1_P_2; 173 } 174 } 175 init_adc_pins(void)176void init_adc_pins(void) 177 { 178 HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_BUS:ADC0.INA1 */ 179 HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.INA12/ADC1.INA8/ADC2.INA4 */ 180 HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.INA13/ADC1.INA9/ADC2.INA5 */ 181 HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.INA11/ADC1.INA7.ADC2.INA3 */ 182 } 183 init_adc_bldc_pins(void)184void init_adc_bldc_pins(void) 185 { 186 HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 187 HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 188 HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 189 } 190 init_usb_pins(void)191void init_usb_pins(void) 192 { 193 HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; 194 HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); 195 } 196 init_can_pins(MCAN_Type * ptr)197void init_can_pins(MCAN_Type *ptr) 198 { 199 if (ptr == HPM_MCAN0) { 200 HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_CAN0_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 201 HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_CAN0_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 202 HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_CAN0_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 203 204 HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); 205 HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); 206 HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); 207 } 208 } 209 init_clk_obs_pins(void)210void init_clk_obs_pins(void) 211 { 212 /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */ 213 } 214 init_led_pins_as_gpio(void)215void init_led_pins_as_gpio(void) 216 { 217 HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; 218 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_GPIO_B_01; 219 HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_GPIO_A_27; 220 } 221 init_dac_pins(DAC_Type * ptr)222void init_dac_pins(DAC_Type *ptr) 223 { 224 if (ptr == HPM_DAC0) { 225 HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC0.OUT */ 226 } else if (ptr == HPM_DAC1) { 227 HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC1.OUT */ 228 } 229 } 230 init_trgmux_pins(uint32_t pin)231void init_trgmux_pins(uint32_t pin) 232 { 233 /* all trgmux pin ALT_SELECT fixed to 16*/ 234 HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); 235 } 236 init_pla_pins(void)237void init_pla_pins(void) 238 { 239 HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_TRGM0_P_05; 240 } 241 init_pla_tamagawa_pins(void)242void init_pla_tamagawa_pins(void) 243 { 244 HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_GPIO_B_30; 245 HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PB31_FUNC_CTL_GPIO_B_31; 246 HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_TRGM0_P_01; 247 HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_TRGM0_P_02; 248 HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_TRGM0_P_03; 249 HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_SPI2_CSN; 250 HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI; 251 HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO; 252 HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK; 253 } 254 init_lin_pins(LIN_Type * ptr)255void init_lin_pins(LIN_Type *ptr) 256 { 257 /** enable open drain and pull up */ 258 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); 259 if (ptr == HPM_LIN0) { 260 HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_LIN0_TXD; 261 HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl; 262 HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_LIN0_RXD; 263 HPM_IOC->PAD[IOC_PAD_PA11].PAD_CTL = pad_ctl; 264 HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_LIN0_TREN; 265 HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = pad_ctl; 266 } else if (ptr == HPM_LIN2) { 267 HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_LIN2_RXD; 268 HPM_IOC->PAD[IOC_PAD_PA07].PAD_CTL = pad_ctl; 269 HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_LIN2_TXD; 270 HPM_IOC->PAD[IOC_PAD_PA06].PAD_CTL = pad_ctl; 271 /* missing TREN pin */ 272 } 273 } 274 init_motor_over_zero_sensorless_adc_pins(void)275void init_motor_over_zero_sensorless_adc_pins(void) 276 { 277 HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 278 HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 279 HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 280 } 281 init_led_pins_as_pwm(void)282void init_led_pins_as_pwm(void) 283 { 284 /* Blue */ 285 HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM0_P_7; 286 /* Green */ 287 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_PWM1_P_1; 288 /* Red */ 289 HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM3_P_07; 290 } 291