1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_IOC_H 10 #define HPM_IOC_H 11 12 typedef struct { 13 struct { 14 __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ 15 __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ 16 } PAD[456]; 17 } IOC_Type; 18 19 20 /* Bitfield definition for register of struct array PAD: FUNC_CTL */ 21 /* 22 * LOOP_BACK (RW) 23 * 24 * force input on 25 * 0: disable 26 * 1: enable 27 */ 28 #define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) 29 #define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) 30 #define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) 31 #define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) 32 33 /* 34 * ANALOG (RW) 35 * 36 * select analog pin in pad 37 * 0: disable 38 * 1: enable 39 */ 40 #define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) 41 #define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) 42 #define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) 43 #define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) 44 45 /* 46 * ALT_SELECT (RW) 47 * 48 * alt select 49 * 0: ALT0 50 * 1: ALT1 51 * ... 52 * 31:ALT31 53 */ 54 #define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) 55 #define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) 56 #define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) 57 #define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) 58 59 /* Bitfield definition for register of struct array PAD: PAD_CTL */ 60 /* 61 * HYS (RW) 62 * 63 * schmitt trigger enable 64 * 0: disable 65 * 1: enable 66 */ 67 #define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) 68 #define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) 69 #define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) 70 #define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) 71 72 /* 73 * PRS (RW) 74 * 75 * select pull up/down internal resistance strength: 76 * For pull down, only have 100 Kohm resistance 77 * For pull up: 78 * 00: 100 KOhm 79 * 01: 47 KOhm 80 * 10: 22 KOhm 81 * 11: 22 KOhm 82 */ 83 #define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) 84 #define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) 85 #define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) 86 #define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) 87 88 /* 89 * PS (RW) 90 * 91 * pull select 92 * 0: pull down 93 * 1: pull up 94 */ 95 #define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) 96 #define IOC_PAD_PAD_CTL_PS_SHIFT (18U) 97 #define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) 98 #define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) 99 100 /* 101 * PE (RW) 102 * 103 * pull enable 104 * 0: pull disable 105 * 1: pull enable 106 */ 107 #define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) 108 #define IOC_PAD_PAD_CTL_PE_SHIFT (17U) 109 #define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) 110 #define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) 111 112 /* 113 * KE (RW) 114 * 115 * keeper capability enable 116 * 0: keeper disable 117 * 1: keeper enable 118 */ 119 #define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) 120 #define IOC_PAD_PAD_CTL_KE_SHIFT (16U) 121 #define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) 122 #define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) 123 124 /* 125 * OD (RW) 126 * 127 * open drain 128 * 0: open drain disable 129 * 1: open drain enable 130 */ 131 #define IOC_PAD_PAD_CTL_OD_MASK (0x100U) 132 #define IOC_PAD_PAD_CTL_OD_SHIFT (8U) 133 #define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) 134 #define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) 135 136 /* 137 * SR (RW) 138 * 139 * slew rate 140 * 0: Slow slew rate 141 * 1: Fast slew rate 142 */ 143 #define IOC_PAD_PAD_CTL_SR_MASK (0x40U) 144 #define IOC_PAD_PAD_CTL_SR_SHIFT (6U) 145 #define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) 146 #define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) 147 148 /* 149 * SPD (RW) 150 * 151 * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise 152 * 00: Slow frequency slew rate(50Mhz) 153 * 01: Medium frequency slew rate(100 Mhz) 154 * 10: Fast frequency slew rate(150 Mhz) 155 * 11: Max frequency slew rate(200Mhz) 156 */ 157 #define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) 158 #define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) 159 #define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) 160 #define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) 161 162 /* 163 * DS (RW) 164 * 165 * drive strength 166 * 1.8V Mode: 167 * 000: 260 Ohm 168 * 001: 260 Ohm 169 * 010: 130 Ohm 170 * 011: 88 Ohm 171 * 100: 65 Ohm 172 * 101: 52 Ohm 173 * 110: 43 Ohm 174 * 111: 37 Ohm 175 * 3.3V Mode: 176 * 000: 157 Ohm 177 * 001: 157 Ohm 178 * 010: 78 Ohm 179 * 011: 53 Ohm 180 * 100: 39 Ohm 181 * 101: 32 Ohm 182 * 110: 26 Ohm 183 * 111: 23 Ohm 184 */ 185 #define IOC_PAD_PAD_CTL_DS_MASK (0x7U) 186 #define IOC_PAD_PAD_CTL_DS_SHIFT (0U) 187 #define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) 188 #define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) 189 190 191 192 /* PAD register group index macro definition */ 193 #define IOC_PAD_PA00 (0UL) 194 #define IOC_PAD_PA01 (1UL) 195 #define IOC_PAD_PA02 (2UL) 196 #define IOC_PAD_PA03 (3UL) 197 #define IOC_PAD_PA04 (4UL) 198 #define IOC_PAD_PA05 (5UL) 199 #define IOC_PAD_PA06 (6UL) 200 #define IOC_PAD_PA07 (7UL) 201 #define IOC_PAD_PA08 (8UL) 202 #define IOC_PAD_PA09 (9UL) 203 #define IOC_PAD_PA10 (10UL) 204 #define IOC_PAD_PA11 (11UL) 205 #define IOC_PAD_PA12 (12UL) 206 #define IOC_PAD_PA13 (13UL) 207 #define IOC_PAD_PA14 (14UL) 208 #define IOC_PAD_PA15 (15UL) 209 #define IOC_PAD_PA16 (16UL) 210 #define IOC_PAD_PA17 (17UL) 211 #define IOC_PAD_PA18 (18UL) 212 #define IOC_PAD_PA19 (19UL) 213 #define IOC_PAD_PA20 (20UL) 214 #define IOC_PAD_PA21 (21UL) 215 #define IOC_PAD_PA22 (22UL) 216 #define IOC_PAD_PA23 (23UL) 217 #define IOC_PAD_PA24 (24UL) 218 #define IOC_PAD_PA25 (25UL) 219 #define IOC_PAD_PA26 (26UL) 220 #define IOC_PAD_PA27 (27UL) 221 #define IOC_PAD_PA28 (28UL) 222 #define IOC_PAD_PA29 (29UL) 223 #define IOC_PAD_PA30 (30UL) 224 #define IOC_PAD_PA31 (31UL) 225 #define IOC_PAD_PB00 (32UL) 226 #define IOC_PAD_PB01 (33UL) 227 #define IOC_PAD_PB02 (34UL) 228 #define IOC_PAD_PB03 (35UL) 229 #define IOC_PAD_PB04 (36UL) 230 #define IOC_PAD_PB05 (37UL) 231 #define IOC_PAD_PB06 (38UL) 232 #define IOC_PAD_PB07 (39UL) 233 #define IOC_PAD_PB08 (40UL) 234 #define IOC_PAD_PB09 (41UL) 235 #define IOC_PAD_PB10 (42UL) 236 #define IOC_PAD_PB11 (43UL) 237 #define IOC_PAD_PB12 (44UL) 238 #define IOC_PAD_PB13 (45UL) 239 #define IOC_PAD_PB14 (46UL) 240 #define IOC_PAD_PB15 (47UL) 241 #define IOC_PAD_PX00 (416UL) 242 #define IOC_PAD_PX01 (416UL) 243 #define IOC_PAD_PX02 (417UL) 244 #define IOC_PAD_PX03 (417UL) 245 #define IOC_PAD_PX04 (418UL) 246 #define IOC_PAD_PX05 (418UL) 247 #define IOC_PAD_PX06 (419UL) 248 #define IOC_PAD_PX07 (419UL) 249 #define IOC_PAD_PY00 (448UL) 250 #define IOC_PAD_PY01 (449UL) 251 #define IOC_PAD_PY02 (450UL) 252 #define IOC_PAD_PY03 (451UL) 253 #define IOC_PAD_PY04 (452UL) 254 #define IOC_PAD_PY05 (453UL) 255 #define IOC_PAD_PY06 (454UL) 256 #define IOC_PAD_PY07 (455UL) 257 258 259 #endif /* HPM_IOC_H */ 260