1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 6 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 7 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 8 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 34 * 35 * The EHCI 0.96 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 * 42 */ 43 44 #include "implementation/global_implementation.h" 45 #include "controller/ehci.h" 46 #include "controller/ehcireg.h" 47 48 49 #define EHCI_BUS2SC(bus) \ 50 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 51 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 52 53 #undef USB_DEBUG_VAR 54 #define USB_DEBUG_VAR ehcidebug 55 56 #ifdef LOSCFG_USB_DEBUG 57 static int ehcidebug = 0; 58 static int ehciiaadbug = 0; 59 static int ehcilostintrbug = 0; 60 61 static void ehci_dump_regs(ehci_softc_t *sc); 62 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 63 64 void 65 usb_ehci_debug_func(int level) 66 { 67 ehcidebug = level; 68 PRINTK("The level of usb ehci debug is %d\n", level); 69 } 70 DEBUG_MODULE(ehci, usb_ehci_debug_func); 71 #endif 72 73 SPIN_LOCK_INIT(g_usb_ehci_qh_spinlock); 74 75 #define EHCI_INTR_ENDPT 1 76 77 extern const struct usb_bus_methods ehci_bus_methods; 78 extern const struct usb_pipe_methods ehci_device_bulk_methods; 79 extern const struct usb_pipe_methods ehci_device_ctrl_methods; 80 extern const struct usb_pipe_methods ehci_device_intr_methods; 81 extern const struct usb_pipe_methods ehci_device_isoc_fs_methods; 82 extern const struct usb_pipe_methods ehci_device_isoc_hs_methods; 83 84 static void ehci_do_poll(struct usb_bus *); 85 static void ehci_device_done(struct usb_xfer *, usb_error_t); 86 static uint8_t ehci_check_transfer(struct usb_xfer *); 87 static void ehci_timeout(void *); 88 static void ehci_poll_timeout(void *); 89 90 static void ehci_root_intr(ehci_softc_t *sc); 91 92 struct ehci_std_temp { 93 ehci_softc_t *sc; 94 struct usb_page_cache *pc; 95 ehci_qtd_t *td; 96 ehci_qtd_t *td_next; 97 uint32_t average; 98 uint32_t qtd_status; 99 uint32_t len; 100 uint16_t max_frame_size; 101 uint8_t shortpkt; 102 uint8_t auto_data_toggle; 103 uint8_t setup_alt_next; 104 uint8_t last_frame; 105 }; 106 107 /* cb: usb_bus_mem_alloc_all_cb */ 108 /* usb_bus_mem_flush_all_cb */ 109 void 110 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 111 { 112 ehci_softc_t *sc = EHCI_BUS2SC(bus); 113 uint32_t i; 114 115 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 116 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 117 118 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 119 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 120 121 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 122 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 123 124 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 125 cb(bus, sc->sc_hw.intr_start_pc + i, 126 sc->sc_hw.intr_start_pg + i, 127 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 128 } 129 130 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 131 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 132 sc->sc_hw.isoc_hs_start_pg + i, 133 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 134 } 135 136 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 137 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 138 sc->sc_hw.isoc_fs_start_pg + i, 139 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 140 } 141 } 142 143 usb_error_t 144 ehci_reset(ehci_softc_t *sc) 145 { 146 uint32_t hcr; 147 int i; 148 149 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 150 for (i = 0; i < 100; i++) { 151 usb_pause_mtx(NULL, hz / 128); 152 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 153 if (!hcr) { 154 if (sc->sc_vendor_post_reset != NULL) 155 sc->sc_vendor_post_reset(sc); 156 return (USB_ERR_NORMAL_COMPLETION); 157 } 158 } 159 device_printf(sc->sc_bus.bdev, "Reset timeout\n"); 160 return (USB_ERR_IOERROR); 161 } 162 163 static usb_error_t 164 ehci_hcreset(ehci_softc_t *sc) 165 { 166 uint32_t hcr = 0; 167 int i; 168 169 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 170 for (i = 0; i < 100; i++) { 171 usb_pause_mtx(NULL, hz / 128); 172 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 173 if (hcr) 174 break; 175 } 176 if (!hcr) 177 /* 178 * Fall through and try reset anyway even though 179 * Table 2-9 in the EHCI spec says this will result 180 * in undefined behavior. 181 */ 182 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 183 184 return (ehci_reset(sc)); 185 } 186 187 static usb_error_t 188 ehci_init_sub(struct ehci_softc *sc) 189 { 190 struct usb_page_search buf_res; 191 uint32_t cparams; 192 uint32_t hcr = 0; 193 uint8_t i; 194 195 cparams = EREAD4(sc, EHCI_HCCPARAMS); 196 197 DPRINTF("cparams=0x%x\n", cparams); 198 199 if (EHCI_HCC_64BIT(cparams)) { 200 DPRINTF("HCC uses 64-bit structures\n"); 201 202 /* MUST clear segment register if 64 bit capable */ 203 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 204 } 205 206 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 207 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 208 209 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 210 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 211 212 /* enable interrupts */ 213 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 214 215 /* turn on controller */ 216 EOWRITE4(sc, EHCI_USBCMD, 217 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 218 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 219 EHCI_CMD_ASE | 220 EHCI_CMD_PSE | 221 EHCI_CMD_RS); 222 223 /* Take over port ownership */ 224 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 225 226 for (i = 0; i < 100; i++) { 227 usb_pause_mtx(NULL, hz / 128); 228 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 229 if (!hcr) { 230 break; 231 } 232 } 233 if (hcr) { 234 device_printf(sc->sc_bus.bdev, "run timeout\n"); 235 return (USB_ERR_IOERROR); 236 } 237 return (USB_ERR_NORMAL_COMPLETION); 238 } 239 240 usb_error_t 241 ehci_init(ehci_softc_t *sc) 242 { 243 struct usb_page_search buf_res; 244 struct ehci_qh_sub *qh_sub; 245 ehci_qh_t *qh_t; 246 uint32_t version; 247 uint32_t sparams; 248 uint32_t *pframes; 249 uint16_t i; 250 uint16_t x; 251 uint16_t y; 252 uint16_t bit; 253 usb_error_t err = USB_ERR_NORMAL_COMPLETION; 254 255 DPRINTF("start\n"); 256 257 callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 258 callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 259 260 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 261 262 #ifdef LOSCFG_USB_DEBUG 263 if (ehciiaadbug) 264 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 265 if (ehcilostintrbug) 266 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 267 if (ehcidebug > 2) { 268 ehci_dump_regs(sc); 269 } 270 #endif 271 272 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 273 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 274 version >> 8, version & 0xff); 275 276 sparams = EREAD4(sc, EHCI_HCSPARAMS); 277 DPRINTF("sparams=0x%x\n", sparams); 278 279 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 280 sc->sc_bus.usbrev = USB_REV_2_0; 281 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 282 /* Reset the controller */ 283 DPRINTF("%s: resetting\n", 284 device_get_nameunit(sc->sc_bus.bdev)); 285 err = ehci_hcreset(sc); 286 if (err) { 287 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 288 return (err); 289 } 290 } 291 292 /* 293 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 294 * bytes 2: 256*4 bytes 3: unknown 295 */ 296 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 297 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 298 return (USB_ERR_IOERROR); 299 } 300 /* set up the bus struct */ 301 sc->sc_bus.methods = &ehci_bus_methods; 302 303 sc->sc_eintrs = EHCI_NORMAL_INTRS; 304 305 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 306 qh_sub = (struct ehci_qh_sub *)buf_res.buffer; 307 308 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 309 310 /* init terminate TD */ 311 qh_sub->qtd_next = 312 htohc32(sc, EHCI_LINK_TERMINATE); 313 qh_sub->qtd_altnext = 314 htohc32(sc, EHCI_LINK_TERMINATE); 315 qh_sub->qtd_status = 316 htohc32(sc, EHCI_QTD_HALTED); 317 318 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 319 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 320 321 qh_t = (ehci_qh_t *)buf_res.buffer; 322 323 /* initialize page cache pointer */ 324 325 qh_t->page_cache = sc->sc_hw.intr_start_pc + i; 326 327 /* store a pointer to queue head */ 328 329 sc->sc_intr_p_last[i] = qh_t; 330 331 qh_t->qh_self = 332 htohc32(sc, buf_res.physaddr) | 333 htohc32(sc, EHCI_LINK_QH); 334 335 qh_t->qh_endp = 336 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 337 qh_t->qh_endphub = 338 htohc32(sc, EHCI_QH_SET_MULT(1)); 339 qh_t->qh_curqtd = 0; 340 341 qh_t->qh_qtd.qtd_next = 342 htohc32(sc, EHCI_LINK_TERMINATE); 343 qh_t->qh_qtd.qtd_altnext = 344 htohc32(sc, EHCI_LINK_TERMINATE); 345 qh_t->qh_qtd.qtd_status = 346 htohc32(sc, EHCI_QTD_HALTED); 347 } 348 349 /* 350 * the QHs are arranged to give poll intervals that are 351 * powers of 2 times 1ms 352 */ 353 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 354 while (bit) { 355 x = bit; 356 while (x & bit) { 357 ehci_qh_t *qh_x; 358 ehci_qh_t *qh_y; 359 360 y = (x ^ bit) | (bit / 2); 361 362 qh_x = sc->sc_intr_p_last[x]; 363 qh_y = sc->sc_intr_p_last[y]; 364 365 /* 366 * the next QH has half the poll interval 367 */ 368 qh_x->qh_link = qh_y->qh_self; 369 370 x++; 371 } 372 bit >>= 1; 373 } 374 375 qh_t = sc->sc_intr_p_last[0]; 376 377 /* the last (1ms) QH terminates */ 378 qh_t->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 379 380 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 381 ehci_sitd_t *sitd; 382 ehci_itd_t *itd; 383 384 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 385 sitd = (ehci_sitd_t *)buf_res.buffer; 386 387 /* initialize page cache pointer */ 388 389 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 390 391 /* store a pointer to the transfer descriptor */ 392 393 sc->sc_isoc_fs_p_last[i] = sitd; 394 395 /* initialize full speed isochronous */ 396 397 sitd->sitd_self = 398 htohc32(sc, buf_res.physaddr) | 399 htohc32(sc, EHCI_LINK_SITD); 400 401 sitd->sitd_back = 402 htohc32(sc, EHCI_LINK_TERMINATE); 403 404 sitd->sitd_next = 405 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 406 407 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 408 409 itd = (ehci_itd_t *)buf_res.buffer; 410 411 /* initialize page cache pointer */ 412 413 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 414 415 /* store a pointer to the transfer descriptor */ 416 417 sc->sc_isoc_hs_p_last[i] = itd; 418 419 /* initialize high speed isochronous */ 420 421 itd->itd_self = 422 htohc32(sc, buf_res.physaddr) | 423 htohc32(sc, EHCI_LINK_ITD); 424 425 itd->itd_next = 426 sitd->sitd_self; 427 } 428 429 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 430 431 pframes = (uint32_t *)buf_res.buffer; 432 433 /* 434 * execution order: 435 * pframes -> high speed isochronous -> 436 * full speed isochronous -> interrupt QH's 437 */ 438 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 439 pframes[i] = sc->sc_isoc_hs_p_last 440 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 441 } 442 443 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 444 445 qh_t = (ehci_qh_t *)buf_res.buffer; 446 447 /* initialize page cache pointer */ 448 449 qh_t->page_cache = &sc->sc_hw.async_start_pc; 450 451 /* store a pointer to the queue head */ 452 453 sc->sc_async_p_last = qh_t; 454 455 /* init dummy QH that starts the async list */ 456 457 qh_t->qh_self = 458 htohc32(sc, buf_res.physaddr) | 459 htohc32(sc, EHCI_LINK_QH); 460 461 /* fill the QH */ 462 qh_t->qh_endp = 463 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 464 qh_t->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 465 qh_t->qh_link = qh_t->qh_self; 466 qh_t->qh_curqtd = 0; 467 468 /* fill the overlay qTD */ 469 qh_t->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 470 qh_t->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 471 qh_t->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 472 473 /* flush all cache into memory */ 474 475 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 476 477 #ifdef LOSCFG_USB_DEBUG 478 if (ehcidebug) { 479 ehci_dump_sqh(sc, sc->sc_async_p_last); 480 } 481 #endif 482 483 /* finial setup */ 484 err = ehci_init_sub(sc); 485 486 if (!err) { 487 /* catch any lost interrupts */ 488 ehci_do_poll(&sc->sc_bus); 489 } 490 return (err); 491 } 492 493 /* 494 * shut down the controller when the system is going down 495 */ 496 void 497 ehci_detach(ehci_softc_t *sc) 498 { 499 USB_BUS_LOCK(&sc->sc_bus); 500 501 callout_stop(&sc->sc_tmo_pcd); 502 callout_stop(&sc->sc_tmo_poll); 503 504 EOWRITE4(sc, EHCI_USBINTR, 0); 505 USB_BUS_UNLOCK(&sc->sc_bus); 506 507 if (ehci_hcreset(sc)) { 508 DPRINTF("reset failed!\n"); 509 } 510 511 /* XXX let stray task complete */ 512 usb_pause_mtx(NULL, hz / 20); 513 514 callout_drain(&sc->sc_tmo_pcd); 515 callout_drain(&sc->sc_tmo_poll); 516 } 517 518 static void 519 ehci_suspend(ehci_softc_t *sc) 520 { 521 DPRINTF("stopping the HC\n"); 522 523 /* reset HC */ 524 (void)ehci_hcreset(sc); 525 } 526 527 static void 528 ehci_resume(ehci_softc_t *sc) 529 { 530 /* reset HC */ 531 (void)ehci_hcreset(sc); 532 533 /* setup HC */ 534 (void)ehci_init_sub(sc); 535 536 /* catch any lost interrupts */ 537 ehci_do_poll(&sc->sc_bus); 538 } 539 540 #ifdef LOSCFG_USB_DEBUG 541 static void 542 ehci_dump_regs(ehci_softc_t *sc) 543 { 544 uint32_t i; 545 546 i = EOREAD4(sc, EHCI_USBCMD); 547 PRINTK("cmd=0x%08x\n", i); 548 549 if (i & EHCI_CMD_ITC_1) 550 PRINTK(" EHCI_CMD_ITC_1\n"); 551 if (i & EHCI_CMD_ITC_2) 552 PRINTK(" EHCI_CMD_ITC_2\n"); 553 if (i & EHCI_CMD_ITC_4) 554 PRINTK(" EHCI_CMD_ITC_4\n"); 555 if (i & EHCI_CMD_ITC_8) 556 PRINTK(" EHCI_CMD_ITC_8\n"); 557 if (i & EHCI_CMD_ITC_16) 558 PRINTK(" EHCI_CMD_ITC_16\n"); 559 if (i & EHCI_CMD_ITC_32) 560 PRINTK(" EHCI_CMD_ITC_32\n"); 561 if (i & EHCI_CMD_ITC_64) 562 PRINTK(" EHCI_CMD_ITC_64\n"); 563 if (i & EHCI_CMD_ASPME) 564 PRINTK(" EHCI_CMD_ASPME\n"); 565 if (i & EHCI_CMD_ASPMC) 566 PRINTK(" EHCI_CMD_ASPMC\n"); 567 if (i & EHCI_CMD_LHCR) 568 PRINTK(" EHCI_CMD_LHCR\n"); 569 if (i & EHCI_CMD_IAAD) 570 PRINTK(" EHCI_CMD_IAAD\n"); 571 if (i & EHCI_CMD_ASE) 572 PRINTK(" EHCI_CMD_ASE\n"); 573 if (i & EHCI_CMD_PSE) 574 PRINTK(" EHCI_CMD_PSE\n"); 575 if (i & EHCI_CMD_FLS_M) 576 PRINTK(" EHCI_CMD_FLS_M\n"); 577 if (i & EHCI_CMD_HCRESET) 578 PRINTK(" EHCI_CMD_HCRESET\n"); 579 if (i & EHCI_CMD_RS) 580 PRINTK(" EHCI_CMD_RS\n"); 581 582 i = EOREAD4(sc, EHCI_USBSTS); 583 584 PRINTK("sts=0x%08x\n", i); 585 586 if (i & EHCI_STS_ASS) 587 PRINTK(" EHCI_STS_ASS\n"); 588 if (i & EHCI_STS_PSS) 589 PRINTK(" EHCI_STS_PSS\n"); 590 if (i & EHCI_STS_REC) 591 PRINTK(" EHCI_STS_REC\n"); 592 if (i & EHCI_STS_HCH) 593 PRINTK(" EHCI_STS_HCH\n"); 594 if (i & EHCI_STS_IAA) 595 PRINTK(" EHCI_STS_IAA\n"); 596 if (i & EHCI_STS_HSE) 597 PRINTK(" EHCI_STS_HSE\n"); 598 if (i & EHCI_STS_FLR) 599 PRINTK(" EHCI_STS_FLR\n"); 600 if (i & EHCI_STS_PCD) 601 PRINTK(" EHCI_STS_PCD\n"); 602 if (i & EHCI_STS_ERRINT) 603 PRINTK(" EHCI_STS_ERRINT\n"); 604 if (i & EHCI_STS_INT) 605 PRINTK(" EHCI_STS_INT\n"); 606 607 PRINTK("intr=0x%08x\n", 608 EOREAD4(sc, EHCI_USBINTR)); 609 PRINTK("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 610 EOREAD4(sc, EHCI_FRINDEX), 611 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 612 EOREAD4(sc, EHCI_PERIODICLISTBASE), 613 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 614 for (i = 1; i <= sc->sc_noport; i++) { 615 PRINTK("port %d status=0x%08x\n", i, 616 EOREAD4(sc, EHCI_PORTSC(i))); 617 } 618 } 619 620 static void 621 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 622 { 623 link = hc32toh(sc, link); 624 PRINTK("0x%08x", link); 625 if (link & EHCI_LINK_TERMINATE) 626 PRINTK("<T>"); 627 else { 628 PRINTK("<"); 629 if (type) { 630 switch (EHCI_LINK_TYPE(link)) { 631 case EHCI_LINK_ITD: 632 PRINTK("ITD"); 633 break; 634 case EHCI_LINK_QH: 635 PRINTK("QH"); 636 break; 637 case EHCI_LINK_SITD: 638 PRINTK("SITD"); 639 break; 640 case EHCI_LINK_FSTN: 641 PRINTK("FSTN"); 642 break; 643 } 644 } 645 PRINTK(">"); 646 } 647 } 648 649 static void 650 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 651 { 652 uint32_t s; 653 654 PRINTK(" next="); 655 ehci_dump_link(sc, qtd->qtd_next, 0); 656 PRINTK(" altnext="); 657 ehci_dump_link(sc, qtd->qtd_altnext, 0); 658 PRINTK("\n"); 659 s = hc32toh(sc, qtd->qtd_status); 660 PRINTK(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 661 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 662 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 663 PRINTK(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 664 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 665 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 666 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 667 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 668 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 669 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 670 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 671 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 672 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 673 674 for (s = 0; s < 5; s++) { 675 PRINTK(" buffer[%d]=0x%08x\n", s, 676 hc32toh(sc, qtd->qtd_buffer[s])); 677 } 678 for (s = 0; s < 5; s++) { 679 PRINTK(" buffer_hi[%d]=0x%08x\n", s, 680 hc32toh(sc, qtd->qtd_buffer_hi[s])); 681 } 682 } 683 684 static uint8_t 685 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 686 { 687 uint8_t temp; 688 689 usb_pc_cpu_invalidate(sqtd->page_cache); 690 PRINTK("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 691 ehci_dump_qtd(sc, sqtd); 692 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 693 return (temp); 694 } 695 696 static void 697 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 698 { 699 uint16_t i; 700 uint8_t stop; 701 702 stop = 0; 703 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 704 stop = ehci_dump_sqtd(sc, sqtd); 705 } 706 if (sqtd) { 707 PRINTK("dump aborted, too many TDs\n"); 708 } 709 } 710 711 static void 712 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 713 { 714 uint32_t endp; 715 uint32_t endphub; 716 717 usb_pc_cpu_invalidate(qh->page_cache); 718 PRINTK("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 719 PRINTK(" link="); 720 ehci_dump_link(sc, qh->qh_link, 1); 721 PRINTK("\n"); 722 endp = hc32toh(sc, qh->qh_endp); 723 PRINTK(" endp=0x%08x\n", endp); 724 PRINTK(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 725 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 726 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 727 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 728 PRINTK(" mpl=0x%x ctl=%d nrl=%d\n", 729 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 730 EHCI_QH_GET_NRL(endp)); 731 endphub = hc32toh(sc, qh->qh_endphub); 732 PRINTK(" endphub=0x%08x\n", endphub); 733 PRINTK(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 734 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 735 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 736 EHCI_QH_GET_MULT(endphub)); 737 PRINTK(" curqtd="); 738 ehci_dump_link(sc, qh->qh_curqtd, 0); 739 PRINTK("\n"); 740 PRINTK("Overlay qTD:\n"); 741 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 742 } 743 744 static void 745 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 746 { 747 usb_pc_cpu_invalidate(sitd->page_cache); 748 PRINTK("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 749 PRINTK(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 750 PRINTK(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 751 hc32toh(sc, sitd->sitd_portaddr), 752 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 753 ? "in" : "out", 754 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 755 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 756 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 757 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 758 PRINTK(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 759 PRINTK(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 760 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 761 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 762 PRINTK(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 763 hc32toh(sc, sitd->sitd_back), 764 hc32toh(sc, sitd->sitd_bp[0]), 765 hc32toh(sc, sitd->sitd_bp[1]), 766 hc32toh(sc, sitd->sitd_bp_hi[0]), 767 hc32toh(sc, sitd->sitd_bp_hi[1])); 768 } 769 770 static void 771 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 772 { 773 usb_pc_cpu_invalidate(itd->page_cache); 774 PRINTK("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 775 PRINTK(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 776 PRINTK(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 777 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 778 PRINTK(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 779 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 780 PRINTK(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 781 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 782 PRINTK(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 783 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 784 PRINTK(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 785 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 786 PRINTK(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 787 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 788 PRINTK(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 789 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 790 PRINTK(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 791 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 792 PRINTK(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 793 PRINTK(" addr=0x%02x; endpt=0x%01x\n", 794 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 795 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 796 PRINTK(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 797 PRINTK(" dir=%s; mpl=0x%02x\n", 798 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 799 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 800 PRINTK(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 801 hc32toh(sc, itd->itd_bp[2]), 802 hc32toh(sc, itd->itd_bp[3]), 803 hc32toh(sc, itd->itd_bp[4]), 804 hc32toh(sc, itd->itd_bp[5]), 805 hc32toh(sc, itd->itd_bp[6])); 806 PRINTK(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 807 " 0x%08x,0x%08x,0x%08x\n", 808 hc32toh(sc, itd->itd_bp_hi[0]), 809 hc32toh(sc, itd->itd_bp_hi[1]), 810 hc32toh(sc, itd->itd_bp_hi[2]), 811 hc32toh(sc, itd->itd_bp_hi[3]), 812 hc32toh(sc, itd->itd_bp_hi[4]), 813 hc32toh(sc, itd->itd_bp_hi[5]), 814 hc32toh(sc, itd->itd_bp_hi[6])); 815 } 816 817 static void 818 ehci_dump_isoc(ehci_softc_t *sc) 819 { 820 ehci_itd_t *itd; 821 ehci_sitd_t *sitd; 822 uint16_t max = 1000; 823 uint16_t pos; 824 825 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 826 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 827 828 PRINTK("%s: isochronous dump from frame 0x%03x:\n", 829 __FUNCTION__, pos); 830 831 itd = sc->sc_isoc_hs_p_last[pos]; 832 sitd = sc->sc_isoc_fs_p_last[pos]; 833 834 while (itd && max && max--) { 835 ehci_dump_itd(sc, itd); 836 itd = itd->prev; 837 } 838 839 while (sitd && max && max--) { 840 ehci_dump_sitd(sc, sitd); 841 sitd = sitd->prev; 842 } 843 } 844 845 #endif 846 847 static void 848 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 849 { 850 /* check for early completion */ 851 if (ehci_check_transfer(xfer)) { 852 DPRINTFN(0, " ehci_check_transfer return\n"); 853 return; 854 } 855 DPRINTFN(7, " enqueue\n"); 856 /* put transfer on interrupt queue */ 857 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 858 859 /* start timeout, if any */ 860 if (xfer->timeout != 0) { 861 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 862 } 863 } 864 865 #define EHCI_APPEND_FS_TD(std, last) (last) = _ehci_append_fs_td(std, last) 866 static ehci_sitd_t * 867 _ehci_append_fs_td(ehci_sitd_t *ehci_std, ehci_sitd_t *last) 868 { 869 DPRINTFN(11, "%p to %p\n", ehci_std, last); 870 871 /* (sc->sc_bus.mtx) must be locked */ 872 873 ehci_std->next = last->next; 874 ehci_std->sitd_next = last->sitd_next; 875 876 ehci_std->prev = last; 877 878 usb_pc_cpu_flush(ehci_std->page_cache); 879 880 /* 881 * the last->next->prev is never followed: std->next->prev = std; 882 */ 883 last->next = ehci_std; 884 last->sitd_next = ehci_std->sitd_self; 885 886 usb_pc_cpu_flush(last->page_cache); 887 888 return (ehci_std); 889 } 890 891 #define EHCI_APPEND_HS_TD(std, last) (last) = _ehci_append_hs_td(std, last) 892 static ehci_itd_t * 893 _ehci_append_hs_td(ehci_itd_t *ehci_std, ehci_itd_t *last) 894 { 895 DPRINTFN(11, "%p to %p\n", ehci_std, last); 896 897 /* (sc->sc_bus.mtx) must be locked */ 898 899 ehci_std->next = last->next; 900 ehci_std->itd_next = last->itd_next; 901 902 ehci_std->prev = last; 903 904 usb_pc_cpu_flush(ehci_std->page_cache); 905 906 /* 907 * the last->next->prev is never followed: std->next->prev = std; 908 */ 909 last->next = ehci_std; 910 last->itd_next = ehci_std->itd_self; 911 912 usb_pc_cpu_flush(last->page_cache); 913 914 return (ehci_std); 915 } 916 917 #define EHCI_APPEND_QH(sqh, last) (last) = _ehci_append_qh(sqh, last) 918 static ehci_qh_t * 919 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 920 { 921 DPRINTFN(11, "%p to %p\n", sqh, last); 922 923 if (sqh->prev != NULL) { 924 /* should not happen */ 925 DPRINTFN(0, "QH already linked!\n"); 926 return (last); 927 } 928 /* (sc->sc_bus.mtx) must be locked */ 929 930 sqh->next = last->next; 931 sqh->qh_link = last->qh_link; 932 933 sqh->prev = last; 934 935 usb_pc_cpu_flush(sqh->page_cache); 936 937 /* 938 * the last->next->prev is never followed: sqh->next->prev = sqh; 939 */ 940 941 last->next = sqh; 942 last->qh_link = sqh->qh_self; 943 944 usb_pc_cpu_flush(last->page_cache); 945 946 return (sqh); 947 } 948 949 #define EHCI_REMOVE_FS_TD(std, last) (last) = _ehci_remove_fs_td(std, last) 950 static ehci_sitd_t * 951 _ehci_remove_fs_td(ehci_sitd_t *ehci_std, ehci_sitd_t *last) 952 { 953 DPRINTFN(11, "%p from %p\n", ehci_std, last); 954 955 /* (sc->sc_bus.mtx) must be locked */ 956 957 ehci_std->prev->next = ehci_std->next; 958 ehci_std->prev->sitd_next = ehci_std->sitd_next; 959 960 usb_pc_cpu_flush(ehci_std->prev->page_cache); 961 962 if (ehci_std->next) { 963 ehci_std->next->prev = ehci_std->prev; 964 usb_pc_cpu_flush(ehci_std->next->page_cache); 965 } 966 return ((last == ehci_std) ? ehci_std->prev : last); 967 } 968 969 #define EHCI_REMOVE_HS_TD(std, last) (last) = _ehci_remove_hs_td(std, last) 970 static ehci_itd_t * 971 _ehci_remove_hs_td(ehci_itd_t *ehci_std, ehci_itd_t *last) 972 { 973 DPRINTFN(11, "%p from %p\n", ehci_std, last); 974 975 /* (sc->sc_bus.mtx) must be locked */ 976 977 ehci_std->prev->next = ehci_std->next; 978 ehci_std->prev->itd_next = ehci_std->itd_next; 979 980 usb_pc_cpu_flush(ehci_std->prev->page_cache); 981 982 if (ehci_std->next) { 983 ehci_std->next->prev = ehci_std->prev; 984 usb_pc_cpu_flush(ehci_std->next->page_cache); 985 } 986 return ((last == ehci_std) ? ehci_std->prev : last); 987 } 988 989 #define EHCI_REMOVE_QH(sqh, last) (last) = _ehci_remove_qh(sqh, last) 990 static ehci_qh_t * 991 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 992 { 993 DPRINTFN(11, "%p from %p\n", sqh, last); 994 995 /* (sc->sc_bus.mtx) must be locked */ 996 997 /* only remove if not removed from a queue */ 998 if (sqh->prev) { 999 sqh->prev->next = sqh->next; 1000 sqh->prev->qh_link = sqh->qh_link; 1001 1002 usb_pc_cpu_flush(sqh->prev->page_cache); 1003 1004 if (sqh->next) { 1005 sqh->next->prev = sqh->prev; 1006 usb_pc_cpu_flush(sqh->next->page_cache); 1007 } 1008 last = ((last == sqh) ? sqh->prev : last); 1009 1010 sqh->prev = 0; 1011 1012 usb_pc_cpu_flush(sqh->page_cache); 1013 } 1014 return (last); 1015 } 1016 1017 static void 1018 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1019 { 1020 uint16_t rem; 1021 uint8_t dt; 1022 1023 /* count number of full packets */ 1024 dt = (actlen / xfer->max_packet_size) & 1; 1025 1026 /* compute remainder */ 1027 rem = actlen % xfer->max_packet_size; 1028 1029 if (rem > 0) 1030 dt ^= 1; /* short packet at the end */ 1031 else if (actlen != xlen) 1032 dt ^= 1; /* zero length packet at the end */ 1033 else if (xlen == 0) 1034 dt ^= 1; /* zero length transfer */ 1035 1036 xfer->endpoint->toggle_next ^= dt; 1037 } 1038 1039 static usb_error_t 1040 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1041 { 1042 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1043 ehci_qtd_t *td; 1044 ehci_qtd_t *td_alt_next; 1045 uint32_t status; 1046 uint16_t len; 1047 1048 td = (ehci_qtd_t *)xfer->td_transfer_cache; 1049 td_alt_next = td->alt_next; 1050 1051 if (xfer->aframes != xfer->nframes) { 1052 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1053 } 1054 while (1) { 1055 usb_pc_cpu_invalidate(td->page_cache); 1056 status = hc32toh(sc, td->qtd_status); 1057 1058 len = EHCI_QTD_GET_BYTES(status); 1059 1060 /* 1061 * Verify the status length and 1062 * add the length to "frlengths[]": 1063 */ 1064 if (len > td->len) { 1065 /* should not happen */ 1066 DPRINTF("Invalid status length, " 1067 "0x%04x/0x%04x bytes\n", len, td->len); 1068 status |= EHCI_QTD_HALTED; 1069 } else if (xfer->aframes != xfer->nframes) { 1070 xfer->frlengths[xfer->aframes] += td->len - len; 1071 /* manually update data toggle */ 1072 ehci_data_toggle_update(xfer, td->len - len, td->len); 1073 } 1074 1075 /* Check for last transfer */ 1076 if (((void *)td) == xfer->td_transfer_last) { 1077 td = NULL; 1078 break; 1079 } 1080 /* Check for transfer error */ 1081 if (status & EHCI_QTD_HALTED) { 1082 /* the transfer is finished */ 1083 td = NULL; 1084 break; 1085 } 1086 /* Check for short transfer */ 1087 if (len > 0) { 1088 if (xfer->flags_int.short_frames_ok) { 1089 /* follow alt next */ 1090 td = td->alt_next; 1091 } else { 1092 /* the transfer is finished */ 1093 td = NULL; 1094 } 1095 break; 1096 } 1097 td = td->obj_next; 1098 1099 if (td->alt_next != td_alt_next) { 1100 /* this USB frame is complete */ 1101 break; 1102 } 1103 } 1104 1105 /* update transfer cache */ 1106 1107 xfer->td_transfer_cache = td; 1108 1109 #ifdef LOSCFG_USB_DEBUG 1110 if (status & EHCI_QTD_STATERRS) { 1111 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1112 "status=%s%s%s%s%s%s%s%s\n", 1113 xfer->address, xfer->endpointno, xfer->aframes, 1114 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1115 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1116 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1117 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1118 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1119 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1120 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1121 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1122 } 1123 #endif 1124 if (status & EHCI_QTD_HALTED) { 1125 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1126 (xfer->xroot->udev->address != 0)) { 1127 /* try to separate I/O errors from STALL */ 1128 if (EHCI_QTD_GET_CERR(status) == 0) 1129 return (USB_ERR_IOERROR); 1130 } 1131 return (USB_ERR_STALLED); 1132 } 1133 return (USB_ERR_NORMAL_COMPLETION); 1134 } 1135 1136 static void 1137 ehci_non_isoc_done(struct usb_xfer *xfer) 1138 { 1139 ehci_qh_t *qh; 1140 usb_error_t err = USB_ERR_NORMAL_COMPLETION; 1141 1142 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", xfer, xfer->endpoint); 1143 1144 #ifdef LOSCFG_USB_DEBUG 1145 if (ehcidebug > 10) { 1146 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1147 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1148 } 1149 #endif 1150 1151 /* extract data toggle directly from the QH's overlay area */ 1152 qh = (ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set]; 1153 1154 usb_pc_cpu_invalidate(qh->page_cache); 1155 1156 /* reset scanner */ 1157 xfer->td_transfer_cache = xfer->td_transfer_first; 1158 if (xfer->flags_int.control_xfr) { 1159 if (xfer->flags_int.control_hdr) { 1160 err = ehci_non_isoc_done_sub(xfer); 1161 } 1162 xfer->aframes = 1; 1163 1164 if (xfer->td_transfer_cache == NULL) { 1165 goto done; 1166 } 1167 } 1168 while (xfer->aframes != xfer->nframes) { 1169 err = ehci_non_isoc_done_sub(xfer); 1170 xfer->aframes++; 1171 1172 if (xfer->td_transfer_cache == NULL) { 1173 goto done; 1174 } 1175 } 1176 1177 if (xfer->flags_int.control_xfr && 1178 !xfer->flags_int.control_act) { 1179 err = ehci_non_isoc_done_sub(xfer); 1180 } 1181 done: 1182 ehci_device_done(xfer, err); 1183 } 1184 1185 /*------------------------------------------------------------------------* 1186 * ehci_check_transfer 1187 * 1188 * Return values: 1189 * 0: USB transfer is not finished 1190 * Else: USB transfer is finished 1191 *------------------------------------------------------------------------*/ 1192 static uint8_t 1193 ehci_check_transfer(struct usb_xfer *xfer) 1194 { 1195 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1196 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1197 1198 uint32_t status; 1199 1200 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1201 1202 if (methods == &ehci_device_isoc_fs_methods) { 1203 ehci_sitd_t *td; 1204 1205 /* isochronous full speed transfer */ 1206 1207 td = (ehci_sitd_t *)xfer->td_transfer_last; 1208 usb_pc_cpu_invalidate(td->page_cache); 1209 status = hc32toh(sc, td->sitd_status); 1210 1211 /* also check if first is complete */ 1212 1213 td = (ehci_sitd_t *)xfer->td_transfer_first; 1214 usb_pc_cpu_invalidate(td->page_cache); 1215 status |= hc32toh(sc, td->sitd_status); 1216 1217 if (!(status & EHCI_SITD_ACTIVE)) { 1218 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1219 goto transferred; 1220 } 1221 } else if (methods == &ehci_device_isoc_hs_methods) { 1222 ehci_itd_t *td; 1223 1224 /* isochronous high speed transfer */ 1225 1226 /* check last transfer */ 1227 td = (ehci_itd_t *)xfer->td_transfer_last; 1228 usb_pc_cpu_invalidate(td->page_cache); 1229 status = td->itd_status[0]; 1230 status |= td->itd_status[1]; 1231 status |= td->itd_status[2]; 1232 status |= td->itd_status[3]; 1233 status |= td->itd_status[4]; 1234 status |= td->itd_status[5]; 1235 status |= td->itd_status[6]; 1236 status |= td->itd_status[7]; 1237 1238 /* also check first transfer */ 1239 td = (ehci_itd_t *)xfer->td_transfer_first; 1240 usb_pc_cpu_invalidate(td->page_cache); 1241 status |= td->itd_status[0]; 1242 status |= td->itd_status[1]; 1243 status |= td->itd_status[2]; 1244 status |= td->itd_status[3]; 1245 status |= td->itd_status[4]; 1246 status |= td->itd_status[5]; 1247 status |= td->itd_status[6]; 1248 status |= td->itd_status[7]; 1249 1250 /* if no transactions are active we continue */ 1251 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1252 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1253 goto transferred; 1254 } 1255 } else { 1256 ehci_qtd_t *td; 1257 ehci_qh_t *qh; 1258 1259 /* non-isochronous transfer */ 1260 1261 /* 1262 * check whether there is an error somewhere in the middle, 1263 * or whether there was a short packet (SPD and not ACTIVE) 1264 */ 1265 td = (ehci_qtd_t *)xfer->td_transfer_cache; 1266 1267 qh = (ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set]; 1268 1269 usb_pc_cpu_invalidate(qh->page_cache); 1270 1271 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1272 if (status & EHCI_QTD_ACTIVE) { 1273 /* transfer is pending */ 1274 goto done; 1275 } 1276 1277 while (1) { 1278 usb_pc_cpu_invalidate(td->page_cache); 1279 status = hc32toh(sc, td->qtd_status); 1280 1281 /* 1282 * Check if there is an active TD which 1283 * indicates that the transfer isn't done. 1284 */ 1285 if (status & EHCI_QTD_ACTIVE) { 1286 /* update cache */ 1287 xfer->td_transfer_cache = td; 1288 goto done; 1289 } 1290 /* 1291 * last transfer descriptor makes the transfer done 1292 */ 1293 if (((void *)td) == xfer->td_transfer_last) { 1294 break; 1295 } 1296 /* 1297 * any kind of error makes the transfer done 1298 */ 1299 if (status & EHCI_QTD_HALTED) { 1300 break; 1301 } 1302 /* 1303 * if there is no alternate next transfer, a short 1304 * packet also makes the transfer done 1305 */ 1306 if (EHCI_QTD_GET_BYTES(status)) { 1307 if (xfer->flags_int.short_frames_ok) { 1308 /* follow alt next */ 1309 if (td->alt_next) { 1310 td = td->alt_next; 1311 continue; 1312 } 1313 } 1314 /* transfer is done */ 1315 break; 1316 } 1317 td = td->obj_next; 1318 } 1319 ehci_non_isoc_done(xfer); 1320 goto transferred; 1321 } 1322 1323 done: 1324 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1325 return (0); 1326 1327 transferred: 1328 return (1); 1329 } 1330 1331 static void 1332 ehci_pcd_enable(ehci_softc_t *sc) 1333 { 1334 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1335 1336 sc->sc_eintrs |= EHCI_STS_PCD; 1337 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1338 1339 /* acknowledge any PCD interrupt */ 1340 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1341 1342 ehci_root_intr(sc); 1343 } 1344 1345 static void 1346 ehci_interrupt_poll(ehci_softc_t *sc) 1347 { 1348 struct usb_xfer *xfer; 1349 1350 repeat: 1351 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1352 /* 1353 * check if transfer is transferred 1354 */ 1355 if (ehci_check_transfer(xfer)) { 1356 /* queue has been modified */ 1357 goto repeat; 1358 } 1359 } 1360 } 1361 1362 /* 1363 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1364 * writing back the qTD status, or miss signalling occasionally under 1365 * heavy load. If the host machine is too fast, we can miss 1366 * transaction completion - when we scan the active list the 1367 * transaction still seems to be active. This generally exhibits 1368 * itself as a umass stall that never recovers. 1369 * 1370 * We work around this behaviour by setting up this callback after any 1371 * softintr that completes with transactions still pending, giving us 1372 * another chance to check for completion after the writeback has 1373 * taken place. 1374 */ 1375 static void 1376 ehci_poll_timeout(void *ehci_arg) 1377 { 1378 ehci_softc_t *sc = (ehci_softc_t *)ehci_arg; 1379 1380 DPRINTFN(3, "\n"); 1381 ehci_interrupt_poll(sc); 1382 } 1383 1384 /*------------------------------------------------------------------------* 1385 * ehci_interrupt - EHCI interrupt handler 1386 * 1387 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1388 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1389 * is present ! 1390 *------------------------------------------------------------------------*/ 1391 void 1392 ehci_interrupt(unsigned int irq, ehci_softc_t *sc) 1393 { 1394 uint32_t status; 1395 1396 USB_BUS_LOCK(&sc->sc_bus); 1397 DPRINTFN(16, "real interrupt\n"); 1398 1399 #ifdef LOSCFG_USB_DEBUG 1400 if (ehcidebug > 15) { 1401 ehci_dump_regs(sc); 1402 } 1403 #endif 1404 1405 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1406 1407 if (status == 0) { 1408 /* the interrupt was not for us */ 1409 goto done; 1410 } 1411 if (!(status & sc->sc_eintrs)) { 1412 goto done; 1413 } 1414 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1415 1416 status &= sc->sc_eintrs; 1417 1418 #ifdef LOSCFG_USB_DEBUG 1419 if (status & EHCI_STS_HSE) { 1420 ehci_dump_regs(sc); 1421 ehci_dump_isoc(sc); 1422 } 1423 #endif 1424 if (status & EHCI_STS_PCD) { 1425 /* 1426 * Disable PCD interrupt for now, because it will be 1427 * on until the port has been reset. 1428 */ 1429 sc->sc_eintrs &= ~EHCI_STS_PCD; 1430 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1431 1432 ehci_root_intr(sc); 1433 1434 /* do not allow RHSC interrupts > 1 per second */ 1435 callout_reset(&sc->sc_tmo_pcd, hz, 1436 (void *)&ehci_pcd_enable, sc); 1437 } 1438 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1439 1440 if (status != 0) { 1441 /* block unprocessed interrupts */ 1442 sc->sc_eintrs &= ~status; 1443 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1444 } 1445 /* poll all the USB transfers */ 1446 ehci_interrupt_poll(sc); 1447 1448 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1449 callout_reset(&sc->sc_tmo_poll, hz / 128, 1450 (void *)&ehci_poll_timeout, sc); 1451 } 1452 1453 done: 1454 USB_BUS_UNLOCK(&sc->sc_bus); 1455 } 1456 1457 /* 1458 * called when a request does not complete 1459 */ 1460 static void 1461 ehci_timeout(void *ehci_arg) 1462 { 1463 struct usb_xfer *xfer = (struct usb_xfer *)ehci_arg; 1464 1465 DPRINTF("xfer=%p\n", xfer); 1466 1467 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1468 1469 /* transfer is transferred */ 1470 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1471 } 1472 1473 static void 1474 ehci_do_poll(struct usb_bus *bus) 1475 { 1476 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1477 1478 USB_BUS_LOCK(&sc->sc_bus); 1479 ehci_interrupt_poll(sc); 1480 USB_BUS_UNLOCK(&sc->sc_bus); 1481 } 1482 1483 static void 1484 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1485 { 1486 struct usb_page_search buf_res; 1487 ehci_qtd_t *td; 1488 ehci_qtd_t *td_next; 1489 ehci_qtd_t *td_alt_next; 1490 uint32_t buf_offset; 1491 uint32_t average; 1492 uint32_t len_old; 1493 uint32_t terminate; 1494 uint32_t qtd_altnext; 1495 uint8_t shortpkt_old; 1496 uint8_t precompute; 1497 1498 terminate = temp->sc->sc_terminate_self; 1499 qtd_altnext = temp->sc->sc_terminate_self; 1500 td_alt_next = NULL; 1501 buf_offset = 0; 1502 shortpkt_old = temp->shortpkt; 1503 len_old = temp->len; 1504 precompute = 1; 1505 1506 restart: 1507 1508 td = temp->td; 1509 td_next = temp->td_next; 1510 1511 while (1) { 1512 if (temp->len == 0) { 1513 if (temp->shortpkt) { 1514 break; 1515 } 1516 /* send a Zero Length Packet, ZLP, last */ 1517 1518 temp->shortpkt = 1; 1519 average = 0; 1520 1521 } else { 1522 average = temp->average; 1523 1524 if (temp->len < average) { 1525 if (temp->len % temp->max_frame_size) { 1526 temp->shortpkt = 1; 1527 } 1528 average = temp->len; 1529 } 1530 } 1531 1532 if (td_next == NULL) { 1533 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1534 } 1535 /* get next TD */ 1536 1537 td = td_next; 1538 td_next = td->obj_next; 1539 1540 /* check if we are pre-computing */ 1541 1542 if (precompute) { 1543 /* update remaining length */ 1544 1545 temp->len -= average; 1546 1547 continue; 1548 } 1549 /* fill out current TD */ 1550 1551 td->qtd_status = 1552 temp->qtd_status | 1553 htohc32(temp->sc, EHCI_QTD_IOC | 1554 EHCI_QTD_SET_BYTES(average)); 1555 1556 if (average == 0) { 1557 if (temp->auto_data_toggle == 0) { 1558 /* update data toggle, ZLP case */ 1559 1560 temp->qtd_status ^= 1561 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1562 } 1563 td->len = 0; 1564 1565 /* properly reset reserved fields */ 1566 td->qtd_buffer[0] = 0; 1567 td->qtd_buffer[1] = 0; 1568 td->qtd_buffer[2] = 0; 1569 td->qtd_buffer[3] = 0; 1570 td->qtd_buffer[4] = 0; 1571 td->qtd_buffer_hi[0] = 0; 1572 td->qtd_buffer_hi[1] = 0; 1573 td->qtd_buffer_hi[2] = 0; 1574 td->qtd_buffer_hi[3] = 0; 1575 td->qtd_buffer_hi[4] = 0; 1576 } else { 1577 uint8_t x; 1578 1579 if (temp->auto_data_toggle == 0) { 1580 /* update data toggle */ 1581 1582 if (((average + temp->max_frame_size - 1) / 1583 temp->max_frame_size) & 1) { 1584 temp->qtd_status ^= 1585 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1586 } 1587 } 1588 td->len = average; 1589 1590 /* update remaining length */ 1591 1592 temp->len -= average; 1593 1594 /* fill out buffer pointers */ 1595 1596 usbd_get_page(temp->pc, buf_offset, &buf_res); 1597 td->qtd_buffer[0] = 1598 #if USB_HAVE_BUSDMA 1599 htohc32(temp->sc, buf_res.physaddr); 1600 #else 1601 htohc32(temp->sc, (unsigned int)buf_res.buffer); 1602 #endif 1603 td->qtd_buffer_hi[0] = 0; 1604 1605 x = 1; 1606 1607 while (average > EHCI_PAGE_SIZE) { 1608 average -= EHCI_PAGE_SIZE; 1609 buf_offset += EHCI_PAGE_SIZE; 1610 usbd_get_page(temp->pc, buf_offset, &buf_res); 1611 td->qtd_buffer[x] = 1612 htohc32(temp->sc, 1613 #if USB_HAVE_BUSDMA 1614 buf_res.physaddr & (~0xFFF)); 1615 #else 1616 (unsigned int)buf_res.buffer & (~0xFFF)); 1617 #endif 1618 td->qtd_buffer_hi[x] = 0; 1619 x++; 1620 } 1621 1622 /* 1623 * NOTE: The "average" variable is never zero after 1624 * exiting the loop above ! 1625 * 1626 * NOTE: We have to subtract one from the offset to 1627 * ensure that we are computing the physical address 1628 * of a valid page ! 1629 */ 1630 buf_offset += average; 1631 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1632 td->qtd_buffer[x] = 1633 htohc32(temp->sc, 1634 #if USB_HAVE_BUSDMA 1635 buf_res.physaddr & (~0xFFF)); 1636 #else 1637 (unsigned int)buf_res.buffer & (~0xFFF)); 1638 #endif 1639 td->qtd_buffer_hi[x] = 0; 1640 1641 /* properly reset reserved fields */ 1642 while (++x < EHCI_QTD_NBUFFERS) { 1643 td->qtd_buffer[x] = 0; 1644 td->qtd_buffer_hi[x] = 0; 1645 } 1646 } 1647 1648 if (td_next) { 1649 1650 /* link the current TD with the next one */ 1651 td->qtd_next = td_next->qtd_self; 1652 } 1653 1654 td->qtd_altnext = qtd_altnext; 1655 td->alt_next = td_alt_next; 1656 1657 usb_pc_cpu_flush(td->page_cache); 1658 } 1659 1660 if (precompute) { 1661 precompute = 0; 1662 1663 /* setup alt next pointer, if any */ 1664 if (temp->last_frame) { 1665 td_alt_next = NULL; 1666 qtd_altnext = terminate; 1667 } else { 1668 /* we use this field internally */ 1669 td_alt_next = td_next; 1670 if (temp->setup_alt_next && td_next) { 1671 qtd_altnext = td_next->qtd_self; 1672 } else { 1673 qtd_altnext = terminate; 1674 } 1675 } 1676 1677 /* restore */ 1678 temp->shortpkt = shortpkt_old; 1679 temp->len = len_old; 1680 goto restart; 1681 } 1682 temp->td = td; 1683 temp->td_next = td_next; 1684 } 1685 1686 static void 1687 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1688 { 1689 struct ehci_std_temp temp; 1690 const struct usb_pipe_methods *methods; 1691 ehci_qh_t *qh; 1692 ehci_qtd_t *td; 1693 uint32_t qh_endp; 1694 uint32_t qh_endphub; 1695 uint32_t x; 1696 uint32_t int_save; 1697 1698 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1699 xfer->address, UE_GET_ADDR(xfer->endpointno), 1700 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1701 1702 temp.average = xfer->max_hc_frame_size; 1703 temp.max_frame_size = xfer->max_frame_size; 1704 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1705 1706 /* toggle the DMA set we are using */ 1707 xfer->flags_int.curr_dma_set ^= 1; 1708 1709 /* get next DMA set */ 1710 td = (ehci_qtd_t *)xfer->td_start[xfer->flags_int.curr_dma_set]; 1711 1712 xfer->td_transfer_first = td; 1713 xfer->td_transfer_cache = td; 1714 1715 temp.td = NULL; 1716 temp.td_next = td; 1717 temp.qtd_status = 0; 1718 temp.last_frame = 0; 1719 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1720 1721 if (xfer->flags_int.control_xfr) { 1722 if (xfer->endpoint->toggle_next) { 1723 /* DATA1 is next */ 1724 temp.qtd_status |= 1725 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1U)); 1726 } 1727 temp.auto_data_toggle = 0; 1728 } else { 1729 temp.auto_data_toggle = 1; 1730 } 1731 1732 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1733 (xfer->xroot->udev->address != 0)) { 1734 /* max 3 retries */ 1735 temp.qtd_status |= 1736 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1737 } 1738 /* check if we should prepend a setup message */ 1739 1740 if (xfer->flags_int.control_xfr) { 1741 if (xfer->flags_int.control_hdr) { 1742 xfer->endpoint->toggle_next = 0; 1743 1744 temp.qtd_status &= 1745 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1746 temp.qtd_status |= htohc32(temp.sc, 1747 EHCI_QTD_ACTIVE | 1748 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1749 EHCI_QTD_SET_TOGGLE(0)); 1750 1751 temp.len = xfer->frlengths[0]; 1752 temp.pc = xfer->frbuffers + 0; 1753 temp.shortpkt = temp.len ? 1 : 0; 1754 /* check for last frame */ 1755 if (xfer->nframes == 1) { 1756 /* no STATUS stage yet, SETUP is last */ 1757 if (xfer->flags_int.control_act) { 1758 temp.last_frame = 1; 1759 temp.setup_alt_next = 0; 1760 } 1761 } 1762 ehci_setup_standard_chain_sub(&temp); 1763 } 1764 x = 1; 1765 } else { 1766 x = 0; 1767 } 1768 1769 while (x != xfer->nframes) { 1770 /* DATA0 / DATA1 message */ 1771 1772 temp.len = xfer->frlengths[x]; 1773 temp.pc = xfer->frbuffers + x; 1774 1775 x++; 1776 1777 if (x == xfer->nframes) { 1778 if (xfer->flags_int.control_xfr) { 1779 /* no STATUS stage yet, DATA is last */ 1780 if (xfer->flags_int.control_act) { 1781 temp.last_frame = 1; 1782 temp.setup_alt_next = 0; 1783 } 1784 } else { 1785 temp.last_frame = 1; 1786 temp.setup_alt_next = 0; 1787 } 1788 } 1789 /* keep previous data toggle and error count */ 1790 1791 temp.qtd_status &= 1792 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1793 EHCI_QTD_SET_TOGGLE(1U)); 1794 1795 if (temp.len == 0) { 1796 /* make sure that we send an USB packet */ 1797 1798 temp.shortpkt = 0; 1799 1800 } else { 1801 /* regular data transfer */ 1802 1803 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1804 } 1805 1806 /* set endpoint direction */ 1807 1808 temp.qtd_status |= 1809 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1810 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1811 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1812 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1813 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1814 1815 ehci_setup_standard_chain_sub(&temp); 1816 } 1817 1818 /* check if we should append a status stage */ 1819 1820 if (xfer->flags_int.control_xfr && 1821 !xfer->flags_int.control_act) { 1822 /* 1823 * Send a DATA1 message and invert the current endpoint 1824 * direction. 1825 */ 1826 1827 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1828 EHCI_QTD_SET_TOGGLE(1U)); 1829 temp.qtd_status |= 1830 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1831 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1832 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1833 EHCI_QTD_SET_TOGGLE(1U)) : 1834 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1835 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1836 EHCI_QTD_SET_TOGGLE(1U)); 1837 1838 temp.len = 0; 1839 temp.pc = NULL; 1840 temp.shortpkt = 0; 1841 temp.last_frame = 1; 1842 temp.setup_alt_next = 0; 1843 1844 ehci_setup_standard_chain_sub(&temp); 1845 } 1846 td = temp.td; 1847 if (td == NULL) 1848 return; 1849 1850 /* the last TD terminates the transfer: */ 1851 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1852 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1853 1854 usb_pc_cpu_flush(td->page_cache); 1855 1856 /* must have at least one frame! */ 1857 1858 xfer->td_transfer_last = td; 1859 1860 #ifdef LOSCFG_USB_DEBUG 1861 if (ehcidebug > 8) { 1862 DPRINTF("nexttog=%d; data before transfer:\n", 1863 xfer->endpoint->toggle_next); 1864 ehci_dump_sqtds(temp.sc, 1865 xfer->td_transfer_first); 1866 } 1867 #endif 1868 1869 methods = xfer->endpoint->methods; 1870 1871 qh = (ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set]; 1872 1873 /* the "qh_link" field is filled when the QH is added */ 1874 1875 qh_endp = 1876 (EHCI_QH_SET_ADDR(xfer->address) | 1877 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1878 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1879 1880 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1881 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1882 if (methods != &ehci_device_intr_methods) 1883 qh_endp |= EHCI_QH_SET_NRL(8U); 1884 } else { 1885 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1886 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1887 } else { 1888 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1889 } 1890 1891 if (methods == &ehci_device_ctrl_methods) { 1892 qh_endp |= EHCI_QH_CTL; 1893 } 1894 if (methods != &ehci_device_intr_methods) { 1895 /* Only try one time per microframe! */ 1896 qh_endp |= EHCI_QH_SET_NRL(1); 1897 } 1898 } 1899 1900 if (temp.auto_data_toggle == 0) { 1901 /* software computes the data toggle */ 1902 qh_endp |= EHCI_QH_DTC; 1903 } 1904 1905 qh->qh_endp = htohc32(temp.sc, qh_endp); 1906 1907 qh_endphub = 1908 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1909 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1910 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1911 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1912 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1913 1914 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1915 qh->qh_curqtd = 0; 1916 1917 /* fill the overlay qTD */ 1918 1919 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1920 /* DATA1 is next */ 1921 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1U)); 1922 } else { 1923 qh->qh_qtd.qtd_status = 0; 1924 } 1925 1926 td = (ehci_qtd_t *)xfer->td_transfer_first; 1927 1928 qh->qh_qtd.qtd_next = td->qtd_self; 1929 qh->qh_qtd.qtd_altnext = 1930 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1931 1932 /* properly reset reserved fields */ 1933 qh->qh_qtd.qtd_buffer[0] = 0; 1934 qh->qh_qtd.qtd_buffer[1] = 0; 1935 qh->qh_qtd.qtd_buffer[2] = 0; 1936 qh->qh_qtd.qtd_buffer[3] = 0; 1937 qh->qh_qtd.qtd_buffer[4] = 0; 1938 qh->qh_qtd.qtd_buffer_hi[0] = 0; 1939 qh->qh_qtd.qtd_buffer_hi[1] = 0; 1940 qh->qh_qtd.qtd_buffer_hi[2] = 0; 1941 qh->qh_qtd.qtd_buffer_hi[3] = 0; 1942 qh->qh_qtd.qtd_buffer_hi[4] = 0; 1943 1944 usb_pc_cpu_flush(qh->page_cache); 1945 1946 if (xfer->xroot->udev->flags.self_suspended == 0) { 1947 spin_lock_irqsave(&g_usb_ehci_qh_spinlock, int_save); 1948 EHCI_APPEND_QH(qh, *qh_last); 1949 spin_unlock_irqrestore(&g_usb_ehci_qh_spinlock, int_save); 1950 } 1951 } 1952 1953 static void 1954 ehci_root_intr(ehci_softc_t *sc) 1955 { 1956 uint16_t i; 1957 uint16_t m; 1958 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1959 1960 /* clear any old interrupt data */ 1961 (void)memset_s(sc->sc_hub_idata, sizeof(sc->sc_hub_idata), 0, sizeof(sc->sc_hub_idata)); 1962 1963 /* set bits */ 1964 m = (sc->sc_noport + 1); 1965 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1966 m = (8 * sizeof(sc->sc_hub_idata)); 1967 } 1968 for (i = 1; i < m; i++) { 1969 /* pick out CHANGE bits from the status register */ 1970 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 1971 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1972 DPRINTF("port %d changed\n", i); 1973 } 1974 } 1975 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1976 sizeof(sc->sc_hub_idata)); 1977 } 1978 1979 static void 1980 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 1981 { 1982 uint32_t nframes = xfer->nframes; 1983 uint32_t status; 1984 uint32_t *plen = xfer->frlengths; 1985 uint16_t len = 0; 1986 ehci_sitd_t *td = (ehci_sitd_t *)xfer->td_transfer_first; 1987 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 1988 1989 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1990 xfer, xfer->endpoint); 1991 1992 while (nframes--) { 1993 if (td == NULL) { 1994 panic("%s:%d: out of TD's\n", 1995 __FUNCTION__, __LINE__); 1996 } 1997 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 1998 pp_last = &sc->sc_isoc_fs_p_last[0]; 1999 } 2000 #ifdef LOSCFG_USB_DEBUG 2001 if (ehcidebug > 15) { 2002 DPRINTF("isoc FS-TD\n"); 2003 ehci_dump_sitd(sc, td); 2004 } 2005 #endif 2006 usb_pc_cpu_invalidate(td->page_cache); 2007 status = hc32toh(sc, td->sitd_status); 2008 2009 len = EHCI_SITD_GET_LEN(status); 2010 2011 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2012 2013 if (*plen >= len) { 2014 len = *plen - len; 2015 } else { 2016 len = 0; 2017 } 2018 2019 *plen = len; 2020 2021 /* remove FS-TD from schedule */ 2022 EHCI_REMOVE_FS_TD(td, *pp_last); 2023 2024 pp_last++; 2025 plen++; 2026 td = td->obj_next; 2027 } 2028 2029 xfer->aframes = xfer->nframes; 2030 } 2031 2032 static void 2033 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2034 { 2035 uint32_t nframes = xfer->nframes; 2036 uint32_t status; 2037 uint32_t *plen = xfer->frlengths; 2038 uint16_t len = 0; 2039 uint8_t td_no = 0; 2040 ehci_itd_t *td = (ehci_itd_t *)xfer->td_transfer_first; 2041 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2042 2043 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2044 xfer, xfer->endpoint); 2045 2046 while (nframes) { 2047 if (td == NULL) { 2048 panic("%s:%d: out of TD's\n", 2049 __FUNCTION__, __LINE__); 2050 } 2051 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2052 pp_last = &sc->sc_isoc_hs_p_last[0]; 2053 } 2054 #ifdef LOSCFG_USB_DEBUG 2055 if (ehcidebug > 15) { 2056 DPRINTF("isoc HS-TD\n"); 2057 ehci_dump_itd(sc, td); 2058 } 2059 #endif 2060 2061 usb_pc_cpu_invalidate(td->page_cache); 2062 status = hc32toh(sc, td->itd_status[td_no]); 2063 2064 len = EHCI_ITD_GET_LEN(status); 2065 2066 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2067 2068 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2069 if (*plen >= len) { 2070 /* 2071 * The length is valid. NOTE: The 2072 * complete length is written back 2073 * into the status field, and not the 2074 * remainder like with other transfer 2075 * descriptor types. 2076 */ 2077 } else { 2078 /* Invalid length - truncate */ 2079 len = 0; 2080 } 2081 2082 *plen = len; 2083 plen++; 2084 nframes--; 2085 } 2086 2087 td_no++; 2088 2089 if ((td_no == 8) || (nframes == 0)) { 2090 /* remove HS-TD from schedule */ 2091 EHCI_REMOVE_HS_TD(td, *pp_last); 2092 pp_last++; 2093 2094 td_no = 0; 2095 td = td->obj_next; 2096 } 2097 } 2098 xfer->aframes = xfer->nframes; 2099 } 2100 2101 /* NOTE: "done" can be run two times in a row, 2102 * from close and from interrupt 2103 */ 2104 static void 2105 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2106 { 2107 uintptr_t interrupt_ret; 2108 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2109 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2110 2111 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2112 2113 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2114 xfer, xfer->endpoint, error); 2115 2116 if ((methods == &ehci_device_bulk_methods) || 2117 (methods == &ehci_device_ctrl_methods)) { 2118 #ifdef LOSCFG_USB_DEBUG 2119 if (ehcidebug > 8) { 2120 DPRINTF("nexttog=%d; data after transfer:\n", 2121 xfer->endpoint->toggle_next); 2122 ehci_dump_sqtds(sc, 2123 xfer->td_transfer_first); 2124 } 2125 #endif 2126 2127 spin_lock_irqsave(&g_usb_ehci_qh_spinlock, interrupt_ret); 2128 EHCI_REMOVE_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 2129 sc->sc_async_p_last); 2130 spin_unlock_irqrestore(&g_usb_ehci_qh_spinlock, interrupt_ret); 2131 } 2132 if (methods == &ehci_device_intr_methods) { 2133 spin_lock_irqsave(&g_usb_ehci_qh_spinlock, interrupt_ret); 2134 EHCI_REMOVE_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 2135 sc->sc_intr_p_last[xfer->qh_pos]); 2136 spin_unlock_irqrestore(&g_usb_ehci_qh_spinlock, interrupt_ret); 2137 } 2138 /* 2139 * Only finish isochronous transfers once which will update 2140 * "xfer->frlengths". 2141 */ 2142 if (xfer->td_transfer_first && 2143 xfer->td_transfer_last) { 2144 if (methods == &ehci_device_isoc_fs_methods) { 2145 ehci_isoc_fs_done(sc, xfer); 2146 } 2147 if (methods == &ehci_device_isoc_hs_methods) { 2148 ehci_isoc_hs_done(sc, xfer); 2149 } 2150 xfer->td_transfer_first = NULL; 2151 xfer->td_transfer_last = NULL; 2152 } 2153 /* dequeue transfer and start next transfer */ 2154 usbd_transfer_done(xfer, error); 2155 } 2156 2157 /*------------------------------------------------------------------------* 2158 * ehci bulk support 2159 *------------------------------------------------------------------------*/ 2160 static void 2161 ehci_device_bulk_open(struct usb_xfer *xfer) 2162 { 2163 return; 2164 } 2165 2166 static void 2167 ehci_device_bulk_close(struct usb_xfer *xfer) 2168 { 2169 ehci_device_done(xfer, USB_ERR_CANCELLED); 2170 } 2171 2172 static void 2173 ehci_device_bulk_enter(struct usb_xfer *xfer) 2174 { 2175 return; 2176 } 2177 2178 static void 2179 ehci_doorbell_async(struct ehci_softc *sc) 2180 { 2181 uint32_t temp; 2182 2183 /* 2184 * XXX Performance quirk: Some Host Controllers have a too low 2185 * interrupt rate. Issue an IAAD to stimulate the Host 2186 * Controller after queueing the BULK transfer. 2187 * 2188 * XXX Force the host controller to refresh any QH caches. 2189 */ 2190 temp = EOREAD4(sc, EHCI_USBCMD); 2191 if (!(temp & EHCI_CMD_IAAD)) 2192 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2193 } 2194 2195 static void 2196 ehci_device_bulk_start(struct usb_xfer *xfer) 2197 { 2198 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2199 2200 /* setup TD's and QH */ 2201 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2202 2203 /* put transfer on interrupt queue */ 2204 ehci_transfer_intr_enqueue(xfer); 2205 2206 /* 2207 * XXX Certain nVidia chipsets choke when using the IAAD 2208 * feature too frequently. 2209 */ 2210 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2211 return; 2212 2213 ehci_doorbell_async(sc); 2214 } 2215 2216 const struct usb_pipe_methods ehci_device_bulk_methods = 2217 { 2218 .open = ehci_device_bulk_open, 2219 .close = ehci_device_bulk_close, 2220 .enter = ehci_device_bulk_enter, 2221 .start = ehci_device_bulk_start, 2222 }; 2223 2224 /*------------------------------------------------------------------------* 2225 * ehci control support 2226 *------------------------------------------------------------------------*/ 2227 static void 2228 ehci_device_ctrl_open(struct usb_xfer *xfer) 2229 { 2230 return; 2231 } 2232 2233 static void 2234 ehci_device_ctrl_close(struct usb_xfer *xfer) 2235 { 2236 ehci_device_done(xfer, USB_ERR_CANCELLED); 2237 } 2238 2239 static void 2240 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2241 { 2242 return; 2243 } 2244 2245 static void 2246 ehci_device_ctrl_start(struct usb_xfer *xfer) 2247 { 2248 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2249 2250 /* setup TD's and QH */ 2251 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2252 2253 /* put transfer on interrupt queue */ 2254 ehci_transfer_intr_enqueue(xfer); 2255 } 2256 2257 const struct usb_pipe_methods ehci_device_ctrl_methods = 2258 { 2259 .open = ehci_device_ctrl_open, 2260 .close = ehci_device_ctrl_close, 2261 .enter = ehci_device_ctrl_enter, 2262 .start = ehci_device_ctrl_start, 2263 }; 2264 2265 /*------------------------------------------------------------------------* 2266 * ehci interrupt support 2267 *------------------------------------------------------------------------*/ 2268 static void 2269 ehci_device_intr_open(struct usb_xfer *xfer) 2270 { 2271 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2272 uint16_t best; 2273 uint16_t bit; 2274 uint16_t x; 2275 2276 usb_hs_bandwidth_alloc(xfer); 2277 2278 /* 2279 * Find the best QH position corresponding to the given interval: 2280 */ 2281 2282 best = 0; 2283 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2284 while (bit) { 2285 if (xfer->interval >= bit) { 2286 x = bit; 2287 best = bit; 2288 while (x & bit) { 2289 if (sc->sc_intr_stat[x] < 2290 sc->sc_intr_stat[best]) { 2291 best = x; 2292 } 2293 x++; 2294 } 2295 break; 2296 } 2297 bit >>= 1; 2298 } 2299 2300 sc->sc_intr_stat[best]++; 2301 xfer->qh_pos = best; 2302 2303 DPRINTFN(3, "best=%d interval=%d\n", 2304 best, xfer->interval); 2305 } 2306 2307 static void 2308 ehci_device_intr_close(struct usb_xfer *xfer) 2309 { 2310 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2311 2312 sc->sc_intr_stat[xfer->qh_pos]--; 2313 2314 ehci_device_done(xfer, USB_ERR_CANCELLED); 2315 2316 /* bandwidth must be freed after device done */ 2317 usb_hs_bandwidth_free(xfer); 2318 } 2319 2320 static void 2321 ehci_device_intr_enter(struct usb_xfer *xfer) 2322 { 2323 return; 2324 } 2325 2326 static void 2327 ehci_device_intr_start(struct usb_xfer *xfer) 2328 { 2329 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2330 2331 /* setup TD's and QH */ 2332 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2333 2334 /* put transfer on interrupt queue */ 2335 ehci_transfer_intr_enqueue(xfer); 2336 } 2337 2338 const struct usb_pipe_methods ehci_device_intr_methods = 2339 { 2340 .open = ehci_device_intr_open, 2341 .close = ehci_device_intr_close, 2342 .enter = ehci_device_intr_enter, 2343 .start = ehci_device_intr_start, 2344 }; 2345 2346 /*------------------------------------------------------------------------* 2347 * ehci full speed isochronous support 2348 *------------------------------------------------------------------------*/ 2349 static void 2350 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2351 { 2352 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2353 ehci_sitd_t *td; 2354 uint32_t sitd_portaddr; 2355 uint8_t ds; 2356 2357 sitd_portaddr = 2358 EHCI_SITD_SET_ADDR(xfer->address) | 2359 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2360 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2361 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2362 2363 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2364 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2365 2366 sitd_portaddr = htohc32(sc, sitd_portaddr); 2367 2368 /* initialize all TD's */ 2369 2370 for (ds = 0; ds != 2; ds++) { 2371 for (td = (ehci_sitd_t *)xfer->td_start[ds]; td; td = td->obj_next) { 2372 td->sitd_portaddr = sitd_portaddr; 2373 2374 /* 2375 * TODO: make some kind of automatic 2376 * SMASK/CMASK selection based on micro-frame 2377 * usage 2378 * 2379 * micro-frame usage (8 microframes per 1ms) 2380 */ 2381 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2382 2383 usb_pc_cpu_flush(td->page_cache); 2384 } 2385 } 2386 } 2387 2388 static void 2389 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2390 { 2391 ehci_device_done(xfer, USB_ERR_CANCELLED); 2392 } 2393 2394 static void 2395 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2396 { 2397 struct usb_page_search buf_res; 2398 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2399 ehci_sitd_t *td; 2400 ehci_sitd_t *td_last = NULL; 2401 ehci_sitd_t **pp_last; 2402 uint32_t *plen; 2403 uint32_t buf_offset; 2404 uint32_t nframes; 2405 uint32_t temp; 2406 uint32_t sitd_mask; 2407 uint16_t tlen; 2408 uint8_t sa; 2409 uint8_t sb; 2410 2411 #ifdef LOSCFG_USB_DEBUG 2412 uint8_t once = 1; 2413 #endif 2414 2415 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2416 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2417 2418 /* get the current frame index */ 2419 2420 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2421 2422 /* 2423 * check if the frame index is within the window where the frames 2424 * will be inserted 2425 */ 2426 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2427 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2428 2429 if ((xfer->endpoint->is_synced == 0) || 2430 (buf_offset < xfer->nframes)) { 2431 /* 2432 * If there is data underflow or the pipe queue is empty we 2433 * schedule the transfer a few frames ahead of the current 2434 * frame position. Else two isochronous transfers might 2435 * overlap. 2436 */ 2437 xfer->endpoint->isoc_next = (nframes + 3) & 2438 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2439 xfer->endpoint->is_synced = 1; 2440 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2441 } 2442 /* 2443 * compute how many milliseconds the insertion is ahead of the 2444 * current frame position: 2445 */ 2446 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2447 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2448 2449 /* 2450 * pre-compute when the isochronous transfer will be finished: 2451 */ 2452 xfer->isoc_time_complete = 2453 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2454 buf_offset + xfer->nframes; 2455 2456 /* get the real number of frames */ 2457 2458 nframes = xfer->nframes; 2459 2460 buf_offset = 0; 2461 2462 plen = xfer->frlengths; 2463 2464 /* toggle the DMA set we are using */ 2465 xfer->flags_int.curr_dma_set ^= 1; 2466 2467 /* get next DMA set */ 2468 td = (ehci_sitd_t *)xfer->td_start[xfer->flags_int.curr_dma_set]; 2469 xfer->td_transfer_first = td; 2470 2471 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2472 2473 /* store starting position */ 2474 2475 xfer->qh_pos = xfer->endpoint->isoc_next; 2476 2477 while (nframes--) { 2478 if (td == NULL) { 2479 panic("%s:%d: out of TD's\n", 2480 __FUNCTION__, __LINE__); 2481 } 2482 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2483 pp_last = &sc->sc_isoc_fs_p_last[0]; 2484 2485 /* reuse sitd_portaddr and sitd_back from last transfer */ 2486 2487 if (*plen > xfer->max_frame_size) { 2488 #ifdef LOSCFG_USB_DEBUG 2489 if (once) { 2490 once = 0; 2491 PRINTK("%s: frame length(%d) exceeds %d " 2492 "bytes (frame truncated)\n", 2493 __FUNCTION__, *plen, 2494 xfer->max_frame_size); 2495 } 2496 #endif 2497 *plen = xfer->max_frame_size; 2498 } 2499 2500 /* allocate a slot */ 2501 2502 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2503 xfer->isoc_time_complete - nframes - 1); 2504 2505 if (sa == 255) { 2506 /* 2507 * Schedule is FULL, set length to zero: 2508 */ 2509 2510 *plen = 0; 2511 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2512 } 2513 if (*plen) { 2514 /* 2515 * only call "usbd_get_page()" when we have a 2516 * non-zero length 2517 */ 2518 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2519 #if USB_HAVE_BUSDMA 2520 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2521 #else 2522 td->sitd_bp[0] = htohc32(sc, (unsigned int)buf_res.buffer); 2523 #endif 2524 buf_offset += *plen; 2525 /* 2526 * NOTE: We need to subtract one from the offset so 2527 * that we are on a valid page! 2528 */ 2529 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2530 &buf_res); 2531 #if USB_HAVE_BUSDMA 2532 temp = buf_res.physaddr & ~0xFFF; 2533 #else 2534 temp = (unsigned int)buf_res.buffer & ~0xFFF; 2535 #endif 2536 } else { 2537 td->sitd_bp[0] = 0; 2538 temp = 0; 2539 } 2540 2541 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2542 tlen = *plen; 2543 if (tlen <= 188) { 2544 temp |= 1; /* T-count = 1, TP = ALL */ 2545 tlen = 1; 2546 } else { 2547 tlen += 187; 2548 tlen /= 188; 2549 temp |= (uint32_t)tlen; /* T-count = [1..6] */ 2550 temp |= 8; /* TP = Begin */ 2551 } 2552 2553 tlen += sa; 2554 2555 if (tlen >= 8) { 2556 sb = 0; 2557 } else { 2558 sb = (1 << tlen); 2559 } 2560 2561 sa = (1 << sa); 2562 sa = (sb - sa) & 0x3F; 2563 sb = 0; 2564 } else { 2565 sb = (-(4 << sa)) & 0xFE; 2566 sa = (1 << sa) & 0x3F; 2567 } 2568 2569 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2570 EHCI_SITD_SET_CMASK(sb)); 2571 2572 td->sitd_bp[1] = htohc32(sc, temp); 2573 2574 td->sitd_mask = htohc32(sc, sitd_mask); 2575 2576 if (nframes == 0) { 2577 td->sitd_status = htohc32(sc, 2578 EHCI_SITD_IOC | 2579 EHCI_SITD_ACTIVE | 2580 EHCI_SITD_SET_LEN(*plen)); 2581 } else { 2582 td->sitd_status = htohc32(sc, 2583 EHCI_SITD_ACTIVE | 2584 EHCI_SITD_SET_LEN(*plen)); 2585 } 2586 usb_pc_cpu_flush(td->page_cache); 2587 2588 #ifdef LOSCFG_USB_DEBUG 2589 if (ehcidebug > 15) { 2590 DPRINTF("FS-TD %d\n", nframes); 2591 ehci_dump_sitd(sc, td); 2592 } 2593 #endif 2594 /* insert TD into schedule */ 2595 EHCI_APPEND_FS_TD(td, *pp_last); 2596 pp_last++; 2597 2598 plen++; 2599 td_last = td; 2600 td = td->obj_next; 2601 } 2602 2603 xfer->td_transfer_last = td_last; 2604 2605 /* update isoc_next */ 2606 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2607 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2608 2609 /* 2610 * We don't allow cancelling of the SPLIT transaction USB FULL 2611 * speed transfer, because it disturbs the bandwidth 2612 * computation algorithm. 2613 */ 2614 xfer->flags_int.can_cancel_immed = 0; 2615 } 2616 2617 static void 2618 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2619 { 2620 /* 2621 * We don't allow cancelling of the SPLIT transaction USB FULL 2622 * speed transfer, because it disturbs the bandwidth 2623 * computation algorithm. 2624 */ 2625 xfer->flags_int.can_cancel_immed = 0; 2626 2627 /* set a default timeout */ 2628 if (xfer->timeout == 0) 2629 xfer->timeout = 500; /* ms */ 2630 2631 /* put transfer on interrupt queue */ 2632 ehci_transfer_intr_enqueue(xfer); 2633 } 2634 2635 const struct usb_pipe_methods ehci_device_isoc_fs_methods = { 2636 .open = ehci_device_isoc_fs_open, 2637 .close = ehci_device_isoc_fs_close, 2638 .enter = ehci_device_isoc_fs_enter, 2639 .start = ehci_device_isoc_fs_start, 2640 }; 2641 2642 /*------------------------------------------------------------------------* 2643 * ehci high speed isochronous support 2644 *------------------------------------------------------------------------*/ 2645 static void 2646 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2647 { 2648 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2649 ehci_itd_t *td; 2650 uint32_t temp; 2651 uint8_t ds; 2652 2653 usb_hs_bandwidth_alloc(xfer); 2654 2655 /* initialize all TD's */ 2656 2657 for (ds = 0; ds != 2; ds++) { 2658 for (td = (ehci_itd_t *)xfer->td_start[ds]; td; td = td->obj_next) { 2659 /* set TD inactive */ 2660 td->itd_status[0] = 0; 2661 td->itd_status[1] = 0; 2662 td->itd_status[2] = 0; 2663 td->itd_status[3] = 0; 2664 td->itd_status[4] = 0; 2665 td->itd_status[5] = 0; 2666 td->itd_status[6] = 0; 2667 td->itd_status[7] = 0; 2668 2669 /* set endpoint and address */ 2670 td->itd_bp[0] = htohc32(sc, 2671 EHCI_ITD_SET_ADDR(xfer->address) | 2672 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2673 2674 temp = 2675 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2676 2677 /* set direction */ 2678 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2679 temp |= EHCI_ITD_SET_DIR_IN; 2680 } 2681 /* set maximum packet size */ 2682 td->itd_bp[1] = htohc32(sc, temp); 2683 2684 /* set transfer multiplier */ 2685 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2686 2687 usb_pc_cpu_flush(td->page_cache); 2688 } 2689 } 2690 } 2691 2692 static void 2693 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2694 { 2695 ehci_device_done(xfer, USB_ERR_CANCELLED); 2696 2697 /* bandwidth must be freed after device done */ 2698 usb_hs_bandwidth_free(xfer); 2699 } 2700 2701 static void 2702 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2703 { 2704 struct usb_page_search buf_res; 2705 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2706 ehci_itd_t *td; 2707 ehci_itd_t *td_last = NULL; 2708 ehci_itd_t **pp_last; 2709 bus_size_t page_addr; 2710 uint32_t *plen; 2711 uint32_t status; 2712 uint32_t buf_offset; 2713 uint32_t nframes; 2714 uint32_t itd_offset[8 + 1]; 2715 uint8_t x; 2716 uint8_t td_no; 2717 uint8_t page_no; 2718 2719 #ifdef LOSCFG_USB_DEBUG 2720 uint8_t once = 1; 2721 #endif 2722 2723 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2724 xfer, xfer->endpoint->isoc_next, xfer->nframes, 2725 usbd_xfer_get_fps_shift(xfer)); 2726 2727 /* get the current frame index */ 2728 2729 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2730 2731 /* 2732 * check if the frame index is within the window where the frames 2733 * will be inserted 2734 */ 2735 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2736 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2737 2738 if ((xfer->endpoint->is_synced == 0) || 2739 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2740 /* 2741 * If there is data underflow or the pipe queue is empty we 2742 * schedule the transfer a few frames ahead of the current 2743 * frame position. Else two isochronous transfers might 2744 * overlap. 2745 */ 2746 xfer->endpoint->isoc_next = (nframes + 3) & 2747 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2748 xfer->endpoint->is_synced = 1; 2749 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2750 } 2751 /* 2752 * compute how many milliseconds the insertion is ahead of the 2753 * current frame position: 2754 */ 2755 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2756 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2757 2758 /* 2759 * pre-compute when the isochronous transfer will be finished: 2760 */ 2761 xfer->isoc_time_complete = 2762 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2763 (((xfer->nframes << shift) + 7) / 8); 2764 2765 /* get the real number of frames */ 2766 2767 nframes = xfer->nframes; 2768 2769 buf_offset = 0; 2770 td_no = 0; 2771 2772 plen = xfer->frlengths; 2773 2774 /* toggle the DMA set we are using */ 2775 xfer->flags_int.curr_dma_set ^= 1; 2776 2777 /* get next DMA set */ 2778 td = (ehci_itd_t *)xfer->td_start[xfer->flags_int.curr_dma_set]; 2779 xfer->td_transfer_first = td; 2780 2781 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2782 2783 /* store starting position */ 2784 2785 xfer->qh_pos = xfer->endpoint->isoc_next; 2786 2787 while (nframes) { 2788 if (td == NULL) { 2789 panic("%s:%d: out of TD's\n", 2790 __FUNCTION__, __LINE__); 2791 } 2792 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2793 pp_last = &sc->sc_isoc_hs_p_last[0]; 2794 } 2795 /* range check */ 2796 if (*plen > xfer->max_frame_size) { 2797 #ifdef LOSCFG_USB_DEBUG 2798 if (once) { 2799 once = 0; 2800 PRINTK("%s: frame length(%d) exceeds %d bytes " 2801 "(frame truncated)\n", 2802 __FUNCTION__, *plen, xfer->max_frame_size); 2803 } 2804 #endif 2805 *plen = xfer->max_frame_size; 2806 } 2807 2808 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2809 status = (EHCI_ITD_SET_LEN(*plen) | 2810 EHCI_ITD_ACTIVE | 2811 EHCI_ITD_SET_PG(0)); 2812 td->itd_status[td_no] = htohc32(sc, status); 2813 itd_offset[td_no] = buf_offset; 2814 buf_offset += *plen; 2815 plen++; 2816 nframes --; 2817 } else { 2818 td->itd_status[td_no] = 0; /* not active */ 2819 itd_offset[td_no] = buf_offset; 2820 } 2821 2822 td_no++; 2823 2824 if ((td_no == 8) || (nframes == 0)) { 2825 /* the rest of the transfers are not active, if any */ 2826 for (x = td_no; x != 8; x++) { 2827 td->itd_status[x] = 0; /* not active */ 2828 } 2829 2830 /* check if there is any data to be transferred */ 2831 if (itd_offset[0] != buf_offset) { 2832 page_no = 0; 2833 itd_offset[td_no] = buf_offset; 2834 2835 /* get first page offset */ 2836 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2837 /* get page address */ 2838 #if USB_HAVE_BUSDMA 2839 page_addr = buf_res.physaddr & ~0xFFF; 2840 #else 2841 page_addr = (unsigned int)buf_res.buffer & ~0xFFF; 2842 #endif 2843 /* update page address */ 2844 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2845 td->itd_bp[0] |= htohc32(sc, page_addr); 2846 2847 for (x = 0; x != td_no; x++) { 2848 /* set page number and page offset */ 2849 status = (EHCI_ITD_SET_PG(page_no) | 2850 #if USB_HAVE_BUSDMA 2851 (buf_res.physaddr & 0xFFF)); 2852 #else 2853 ((unsigned int)buf_res.buffer & 0xFFF)); 2854 #endif 2855 td->itd_status[x] |= htohc32(sc, status); 2856 2857 /* get next page offset */ 2858 if (itd_offset[x + 1] == buf_offset) { 2859 /* 2860 * We subtract one so that 2861 * we don't go off the last 2862 * page! 2863 */ 2864 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2865 } else { 2866 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2867 } 2868 #if USB_HAVE_BUSDMA 2869 /* check if we need a new page */ 2870 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2871 /* new page needed */ 2872 page_addr = buf_res.physaddr & ~0xFFF; 2873 #else 2874 /* check if we need a new page */ 2875 if (((unsigned int)buf_res.buffer ^ page_addr) & ~0xFFF) { 2876 /* new page needed */ 2877 page_addr = (unsigned int)buf_res.buffer & ~0xFFF; 2878 #endif 2879 if (page_no == 6) { 2880 panic("%s: too many pages\n", __FUNCTION__); 2881 } 2882 page_no++; 2883 page_no%= EHCI_ITD_BP_MAX; 2884 /* update page address */ 2885 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2886 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2887 } 2888 } 2889 } 2890 /* set IOC bit if we are complete */ 2891 if (nframes == 0) { 2892 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2893 } 2894 usb_pc_cpu_flush(td->page_cache); 2895 #ifdef LOSCFG_USB_DEBUG 2896 if (ehcidebug > 15) { 2897 DPRINTF("HS-TD %d\n", nframes); 2898 ehci_dump_itd(sc, td); 2899 } 2900 #endif 2901 /* insert TD into schedule */ 2902 EHCI_APPEND_HS_TD(td, *pp_last); 2903 pp_last++; 2904 2905 td_no = 0; 2906 td_last = td; 2907 td = td->obj_next; 2908 } 2909 } 2910 2911 xfer->td_transfer_last = td_last; 2912 2913 /* update isoc_next */ 2914 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2915 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2916 } 2917 2918 static void 2919 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2920 { 2921 /* put transfer on interrupt queue */ 2922 ehci_transfer_intr_enqueue(xfer); 2923 } 2924 2925 const struct usb_pipe_methods ehci_device_isoc_hs_methods = { 2926 .open = ehci_device_isoc_hs_open, 2927 .close = ehci_device_isoc_hs_close, 2928 .enter = ehci_device_isoc_hs_enter, 2929 .start = ehci_device_isoc_hs_start, 2930 }; 2931 2932 /*------------------------------------------------------------------------* 2933 * ehci root control support 2934 *------------------------------------------------------------------------* 2935 * Simulate a hardware hub by handling all the necessary requests. 2936 *------------------------------------------------------------------------*/ 2937 2938 static const 2939 struct usb_device_descriptor ehci_devd = { 2940 sizeof(struct usb_device_descriptor), 2941 UDESC_DEVICE, /* type */ 2942 {0x00, 0x02}, /* USB version */ 2943 UDCLASS_HUB, /* class */ 2944 UDSUBCLASS_HUB, /* subclass */ 2945 UDPROTO_HSHUBSTT, /* protocol */ 2946 64, /* max packet */ 2947 {0}, {0}, {0x00, 0x01}, /* device id */ 2948 1, 2, 0, /* string indicies */ 2949 1 /* # of configurations */ 2950 }; 2951 2952 static const 2953 struct usb_device_qualifier ehci_odevd = { 2954 sizeof(struct usb_device_qualifier), 2955 UDESC_DEVICE_QUALIFIER, /* type */ 2956 {0x00, 0x02}, /* USB version */ 2957 UDCLASS_HUB, /* class */ 2958 UDSUBCLASS_HUB, /* subclass */ 2959 UDPROTO_FSHUB, /* protocol */ 2960 0, /* max packet */ 2961 0, /* # of configurations */ 2962 0 2963 }; 2964 2965 static const struct ehci_config_desc ehci_confd = { 2966 .confd = { 2967 .bLength = sizeof(struct usb_config_descriptor), 2968 .bDescriptorType = UDESC_CONFIG, 2969 .wTotalLength[0] = sizeof(ehci_confd), 2970 .bNumInterface = 1, 2971 .bConfigurationValue = 1, 2972 .iConfiguration = 0, 2973 .bmAttributes = UC_SELF_POWERED, 2974 .bMaxPower = 0 /* max power */ 2975 }, 2976 .ifcd = { 2977 .bLength = sizeof(struct usb_interface_descriptor), 2978 .bDescriptorType = UDESC_INTERFACE, 2979 .bNumEndpoints = 1, 2980 .bInterfaceClass = UICLASS_HUB, 2981 .bInterfaceSubClass = UISUBCLASS_HUB, 2982 .bInterfaceProtocol = 0, 2983 }, 2984 .endpd = { 2985 .bLength = sizeof(struct usb_endpoint_descriptor), 2986 .bDescriptorType = UDESC_ENDPOINT, 2987 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2988 .bmAttributes = UE_INTERRUPT, 2989 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2990 .bInterval = 255, 2991 }, 2992 }; 2993 2994 static const 2995 struct usb_hub_descriptor ehci_hubd = { 2996 .bDescLength = 0, /* dynamic length */ 2997 .bDescriptorType = UDESC_HUB, 2998 }; 2999 3000 uint16_t 3001 ehci_get_port_speed_portsc(struct ehci_softc *sc, uint16_t index) 3002 { 3003 uint32_t v; 3004 3005 v = EOREAD4(sc, EHCI_PORTSC(index)); 3006 v = (v >> EHCI_PORTSC_PSPD_SHIFT) & EHCI_PORTSC_PSPD_MASK; 3007 3008 if (v == EHCI_PORT_SPEED_HIGH) 3009 return (UPS_HIGH_SPEED); 3010 if (v == EHCI_PORT_SPEED_LOW) 3011 return (UPS_LOW_SPEED); 3012 return (0); 3013 } 3014 3015 uint16_t 3016 ehci_get_port_speed_hostc(struct ehci_softc *sc, uint16_t index) 3017 { 3018 uint32_t v; 3019 3020 v = EOREAD4(sc, EHCI_HOSTC(index)); 3021 v = (v >> EHCI_HOSTC_PSPD_SHIFT) & EHCI_HOSTC_PSPD_MASK; 3022 3023 if (v == EHCI_PORT_SPEED_HIGH) 3024 return (UPS_HIGH_SPEED); 3025 if (v == EHCI_PORT_SPEED_LOW) 3026 return (UPS_LOW_SPEED); 3027 return (0); 3028 } 3029 3030 static usb_error_t 3031 ehci_roothub_exec(struct usb_device *udev, 3032 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3033 { 3034 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3035 const char *str_ptr; 3036 const void *ptr; 3037 uint32_t port; 3038 uint32_t v; 3039 uint16_t len; 3040 uint16_t i; 3041 uint16_t value; 3042 uint16_t index; 3043 usb_error_t err = USB_ERR_NORMAL_COMPLETION; 3044 3045 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3046 3047 /* buffer reset */ 3048 ptr = (const void *)&sc->sc_hub_desc; 3049 len = 0; 3050 3051 value = UGETW(req->wValue); 3052 index = UGETW(req->wIndex); 3053 3054 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3055 "wValue=0x%04x wIndex=0x%04x\n", 3056 req->bmRequestType, req->bRequest, 3057 UGETW(req->wLength), value, index); 3058 3059 #define C(x,y) ((x) | ((y) << 8)) 3060 switch (C(req->bRequest, req->bmRequestType)) { 3061 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3062 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3063 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3064 /* 3065 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3066 * for the integrated root hub. 3067 */ 3068 break; 3069 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3070 len = 1; 3071 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3072 break; 3073 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3074 switch (value >> 8) { 3075 case UDESC_DEVICE: 3076 if ((value & 0xff) != 0) { 3077 err = USB_ERR_IOERROR; 3078 goto done; 3079 } 3080 len = sizeof(ehci_devd); 3081 ptr = (const void *)&ehci_devd; 3082 break; 3083 /* 3084 * We can't really operate at another speed, 3085 * but the specification says we need this 3086 * descriptor: 3087 */ 3088 case UDESC_DEVICE_QUALIFIER: 3089 if ((value & 0xff) != 0) { 3090 err = USB_ERR_IOERROR; 3091 goto done; 3092 } 3093 len = sizeof(ehci_odevd); 3094 ptr = (const void *)&ehci_odevd; 3095 break; 3096 3097 case UDESC_CONFIG: 3098 if ((value & 0xff) != 0) { 3099 err = USB_ERR_IOERROR; 3100 goto done; 3101 } 3102 len = sizeof(ehci_confd); 3103 ptr = (const void *)&ehci_confd; 3104 break; 3105 3106 case UDESC_STRING: 3107 switch (value & 0xff) { 3108 case 0: /* Language table */ 3109 str_ptr = "\001"; 3110 break; 3111 3112 case 1: /* Vendor */ 3113 str_ptr = sc->sc_vendor; 3114 break; 3115 3116 case 2: /* Product */ 3117 str_ptr = "EHCI root HUB"; 3118 break; 3119 3120 default: 3121 str_ptr = ""; 3122 break; 3123 } 3124 3125 len = usb_make_str_desc( 3126 sc->sc_hub_desc.temp, 3127 sizeof(sc->sc_hub_desc.temp), 3128 str_ptr); 3129 break; 3130 default: 3131 err = USB_ERR_IOERROR; 3132 goto done; 3133 } 3134 break; 3135 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3136 len = 1; 3137 sc->sc_hub_desc.temp[0] = 0; 3138 break; 3139 case C(UR_GET_STATUS, UT_READ_DEVICE): 3140 len = 2; 3141 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3142 break; 3143 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3144 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3145 len = 2; 3146 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3147 break; 3148 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3149 if (value >= EHCI_MAX_DEVICES) { 3150 err = USB_ERR_IOERROR; 3151 goto done; 3152 } 3153 sc->sc_addr = value; 3154 break; 3155 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3156 if ((value != 0) && (value != 1)) { 3157 err = USB_ERR_IOERROR; 3158 goto done; 3159 } 3160 sc->sc_conf = value; 3161 break; 3162 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3163 break; 3164 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3165 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3166 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3167 err = USB_ERR_IOERROR; 3168 goto done; 3169 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3170 break; 3171 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3172 break; 3173 /* Hub requests */ 3174 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3175 break; 3176 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3177 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3178 3179 if ((index < 1) || 3180 (index > sc->sc_noport)) { 3181 err = USB_ERR_IOERROR; 3182 goto done; 3183 } 3184 port = EHCI_PORTSC(index); 3185 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3186 switch (value) { 3187 case UHF_PORT_ENABLE: 3188 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3189 break; 3190 case UHF_PORT_SUSPEND: 3191 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3192 /* 3193 * waking up a High Speed device is rather 3194 * complicated if 3195 */ 3196 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3197 } 3198 /* wait 20ms for resume sequence to complete */ 3199 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3200 3201 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3202 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3203 3204 /* 4ms settle time */ 3205 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3206 break; 3207 case UHF_PORT_POWER: 3208 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3209 break; 3210 case UHF_PORT_TEST: 3211 DPRINTFN(3, "clear port test " 3212 "%d\n", index); 3213 break; 3214 case UHF_PORT_INDICATOR: 3215 DPRINTFN(3, "clear port ind " 3216 "%d\n", index); 3217 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3218 break; 3219 case UHF_C_PORT_CONNECTION: 3220 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3221 break; 3222 case UHF_C_PORT_ENABLE: 3223 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3224 break; 3225 case UHF_C_PORT_SUSPEND: 3226 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3227 break; 3228 case UHF_C_PORT_OVER_CURRENT: 3229 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3230 break; 3231 case UHF_C_PORT_RESET: 3232 sc->sc_isreset = 0; 3233 break; 3234 default: 3235 err = USB_ERR_IOERROR; 3236 goto done; 3237 } 3238 break; 3239 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3240 if ((value & 0xff) != 0) { 3241 err = USB_ERR_IOERROR; 3242 goto done; 3243 } 3244 v = EREAD4(sc, EHCI_HCSPARAMS); 3245 3246 sc->sc_hub_desc.hubd = ehci_hubd; 3247 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3248 3249 if (EHCI_HCS_PPC(v)) 3250 i = UHD_PWR_INDIVIDUAL; 3251 else 3252 i = UHD_PWR_NO_SWITCH; 3253 3254 if (EHCI_HCS_P_INDICATOR(v)) 3255 i |= UHD_PORT_IND; 3256 3257 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3258 /* XXX can't find out? */ 3259 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3260 /* XXX don't know if ports are removable or not */ 3261 sc->sc_hub_desc.hubd.bDescLength = 3262 8 + ((sc->sc_noport + 7) / 8); 3263 len = sc->sc_hub_desc.hubd.bDescLength; 3264 break; 3265 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3266 len = 16; 3267 (void)memset_s(sc->sc_hub_desc.temp, sizeof(sc->sc_hub_desc.temp), 0, len); 3268 break; 3269 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3270 DPRINTFN(9, "get port status i=%d\n", 3271 index); 3272 if ((index < 1) || 3273 (index > sc->sc_noport)) { 3274 err = USB_ERR_IOERROR; 3275 goto done; 3276 } 3277 v = EOREAD4(sc, EHCI_PORTSC(index)); 3278 DPRINTFN(1, "port status=0x%04x\n", v); 3279 if (sc->sc_flags & EHCI_SCFLG_TT) { 3280 if (sc->sc_vendor_get_port_speed != NULL) { 3281 i = sc->sc_vendor_get_port_speed(sc, index); 3282 } else { 3283 device_printf(sc->sc_bus.bdev, 3284 "EHCI_SCFLG_TT quirk is set but " 3285 "sc_vendor_get_hub_speed() is NULL\n"); 3286 i = UPS_HIGH_SPEED; 3287 } 3288 } else { 3289 i = UPS_HIGH_SPEED; 3290 } 3291 if (v & EHCI_PS_CS) 3292 i |= UPS_CURRENT_CONNECT_STATUS; 3293 if (v & EHCI_PS_PE) 3294 i |= UPS_PORT_ENABLED; 3295 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3296 i |= UPS_SUSPEND; 3297 if (v & EHCI_PS_OCA) 3298 i |= UPS_OVERCURRENT_INDICATOR; 3299 if (v & EHCI_PS_PR) 3300 i |= UPS_RESET; 3301 if (v & EHCI_PS_PP) 3302 i |= UPS_PORT_POWER; 3303 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3304 i = 0; 3305 if (v & EHCI_PS_CSC) 3306 i |= UPS_C_CONNECT_STATUS; 3307 if (v & EHCI_PS_PEC) 3308 i |= UPS_C_PORT_ENABLED; 3309 if (v & EHCI_PS_OCC) 3310 i |= UPS_C_OVERCURRENT_INDICATOR; 3311 if (v & EHCI_PS_FPR) 3312 i |= UPS_C_SUSPEND; 3313 if (sc->sc_isreset) 3314 i |= UPS_C_PORT_RESET; 3315 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3316 len = sizeof(sc->sc_hub_desc.ps); 3317 break; 3318 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3319 err = USB_ERR_IOERROR; 3320 goto done; 3321 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3322 break; 3323 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3324 if ((index < 1) || 3325 (index > sc->sc_noport)) { 3326 err = USB_ERR_IOERROR; 3327 goto done; 3328 } 3329 port = EHCI_PORTSC(index); 3330 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3331 switch (value) { 3332 case UHF_PORT_ENABLE: 3333 EOWRITE4(sc, port, v | EHCI_PS_PE); 3334 break; 3335 case UHF_PORT_SUSPEND: 3336 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3337 break; 3338 case UHF_PORT_RESET: 3339 DPRINTFN(6, "reset port %d\n", index); 3340 if (EHCI_PS_IS_LOWSPEED(v) && 3341 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3342 /* Low speed device, give up ownership. */ 3343 DPRINTFN(6, "Low speed device is not support!!!!\n"); 3344 err = USB_ERR_INVAL; 3345 goto done; 3346 } 3347 /* Start reset sequence. */ 3348 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3349 EOWRITE4(sc, port, v | EHCI_PS_PR); 3350 3351 /* Wait for reset to complete. */ 3352 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3353 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3354 3355 /* Terminate reset sequence. */ 3356 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3357 EOWRITE4(sc, port, v); 3358 3359 /* Wait for HC to complete reset. */ 3360 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3361 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3362 3363 v = EOREAD4(sc, port); 3364 DPRINTF("ehci after reset, status=0x%08x\n", v); 3365 if (v & EHCI_PS_PR) { 3366 device_printf(sc->sc_bus.bdev, 3367 "port reset timeout\n"); 3368 err = USB_ERR_TIMEOUT; 3369 goto done; 3370 } 3371 if (!(v & EHCI_PS_PE) && 3372 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3373 /* Not a high speed device, give up ownership.*/ 3374 DPRINTFN(6, "Full speed device is not support!!!!\n"); 3375 err = USB_ERR_INVAL; 3376 goto done; 3377 } 3378 sc->sc_isreset = 1; 3379 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3380 index, v); 3381 break; 3382 3383 case UHF_PORT_POWER: 3384 DPRINTFN(3, "set port power %d\n", index); 3385 EOWRITE4(sc, port, v | EHCI_PS_PP); 3386 break; 3387 3388 case UHF_PORT_TEST: 3389 DPRINTFN(3, "set port test %d\n", index); 3390 break; 3391 3392 case UHF_PORT_INDICATOR: 3393 DPRINTFN(3, "set port ind %d\n", index); 3394 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3395 break; 3396 3397 default: 3398 err = USB_ERR_IOERROR; 3399 goto done; 3400 } 3401 break; 3402 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3403 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3404 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3405 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3406 break; 3407 default: 3408 err = USB_ERR_IOERROR; 3409 goto done; 3410 } 3411 done: 3412 *plength = len; 3413 *pptr = ptr; 3414 return (err); 3415 } 3416 3417 static void 3418 ehci_xfer_setup(struct usb_setup_params *parm) 3419 { 3420 struct usb_page_search page_info; 3421 struct usb_page_cache *pc; 3422 ehci_softc_t *sc; 3423 struct usb_xfer *xfer; 3424 void *last_obj; 3425 uint32_t nqtd; 3426 uint32_t nqh; 3427 uint32_t nsitd; 3428 uint32_t nitd; 3429 uint32_t n; 3430 3431 sc = EHCI_BUS2SC(parm->udev->bus); 3432 xfer = parm->curr_xfer; 3433 3434 nqtd = 0; 3435 nqh = 0; 3436 nsitd = 0; 3437 nitd = 0; 3438 3439 /* 3440 * compute maximum number of some structures 3441 */ 3442 if (parm->methods == &ehci_device_ctrl_methods) { 3443 /* 3444 * The proof for the "nqtd" formula is illustrated like 3445 * this: 3446 * 3447 * +------------------------------------+ 3448 * | | 3449 * | |remainder -> | 3450 * | +-----+---+ | 3451 * | | xxx | x | frm 0 | 3452 * | +-----+---++ | 3453 * | | xxx | xx | frm 1 | 3454 * | +-----+----+ | 3455 * | ... | 3456 * +------------------------------------+ 3457 * 3458 * "xxx" means a completely full USB transfer descriptor 3459 * 3460 * "x" and "xx" means a short USB packet 3461 * 3462 * For the remainder of an USB transfer modulo 3463 * "max_data_length" we need two USB transfer descriptors. 3464 * One to transfer the remaining data and one to finalise 3465 * with a zero length packet in case the "force_short_xfer" 3466 * flag is set. We only need two USB transfer descriptors in 3467 * the case where the transfer length of the first one is a 3468 * factor of "max_frame_size". The rest of the needed USB 3469 * transfer descriptors is given by the buffer size divided 3470 * by the maximum data payload. 3471 */ 3472 parm->hc_max_packet_size = 0x400; 3473 parm->hc_max_packet_count = 1; 3474 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3475 #if USB_HAVE_BUSDMA 3476 xfer->flags_int.bdma_enable = 1; 3477 #endif 3478 usbd_transfer_setup_sub(parm); 3479 3480 nqh = 1; 3481 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3482 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3483 3484 } else if (parm->methods == &ehci_device_bulk_methods) { 3485 parm->hc_max_packet_size = 0x400; 3486 parm->hc_max_packet_count = 1; 3487 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3488 #if USB_HAVE_BUSDMA 3489 xfer->flags_int.bdma_enable = 1; 3490 #endif 3491 3492 usbd_transfer_setup_sub(parm); 3493 3494 nqh = 1; 3495 nqtd = ((2 * xfer->nframes) 3496 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3497 3498 } else if (parm->methods == &ehci_device_intr_methods) { 3499 if (parm->speed == USB_SPEED_HIGH) { 3500 parm->hc_max_packet_size = 0x400; 3501 parm->hc_max_packet_count = 3; 3502 } else if (parm->speed == USB_SPEED_FULL) { 3503 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3504 parm->hc_max_packet_count = 1; 3505 } else { 3506 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3507 parm->hc_max_packet_count = 1; 3508 } 3509 3510 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3511 #if USB_HAVE_BUSDMA 3512 xfer->flags_int.bdma_enable = 1; 3513 #endif 3514 3515 usbd_transfer_setup_sub(parm); 3516 3517 nqh = 1; 3518 nqtd = ((2 * xfer->nframes) 3519 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3520 3521 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3522 parm->hc_max_packet_size = 0x3FF; 3523 parm->hc_max_packet_count = 1; 3524 parm->hc_max_frame_size = 0x3FF; 3525 #if USB_HAVE_BUSDMA 3526 xfer->flags_int.bdma_enable = 1; 3527 #endif 3528 3529 usbd_transfer_setup_sub(parm); 3530 3531 nsitd = xfer->nframes; 3532 3533 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3534 parm->hc_max_packet_size = 0x400; 3535 parm->hc_max_packet_count = 3; 3536 parm->hc_max_frame_size = 0xC00; 3537 #if USB_HAVE_BUSDMA 3538 xfer->flags_int.bdma_enable = 1; 3539 #endif 3540 3541 usbd_transfer_setup_sub(parm); 3542 3543 nitd = ((xfer->nframes + 7) / 8) << 3544 usbd_xfer_get_fps_shift(xfer); 3545 3546 } else { 3547 parm->hc_max_packet_size = 0x400; 3548 parm->hc_max_packet_count = 1; 3549 parm->hc_max_frame_size = 0x400; 3550 3551 usbd_transfer_setup_sub(parm); 3552 } 3553 3554 alloc_dma_set: 3555 3556 if (parm->err) { 3557 return; 3558 } 3559 /* 3560 * Allocate queue heads and transfer descriptors 3561 */ 3562 last_obj = NULL; 3563 3564 if (usbd_transfer_setup_sub_malloc( 3565 parm, &pc, sizeof(ehci_itd_t), 3566 EHCI_ITD_ALIGN, nitd)) { 3567 parm->err = USB_ERR_NOMEM; 3568 return; 3569 } 3570 if (parm->buf) { 3571 for (n = 0; n != nitd; n++) { 3572 ehci_itd_t *td; 3573 3574 usbd_get_page(pc + n, 0, &page_info); 3575 3576 td = (ehci_itd_t *)page_info.buffer; 3577 3578 /* init TD */ 3579 #if USB_HAVE_BUSDMA 3580 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3581 #else 3582 td->itd_self = htohc32(sc, (unsigned int)page_info.buffer | EHCI_LINK_ITD); 3583 #endif 3584 td->obj_next = (ehci_itd_t *)last_obj; 3585 td->page_cache = pc + n; 3586 3587 last_obj = td; 3588 3589 usb_pc_cpu_flush(pc + n); 3590 } 3591 } 3592 if (usbd_transfer_setup_sub_malloc( 3593 parm, &pc, sizeof(ehci_sitd_t), 3594 EHCI_SITD_ALIGN, nsitd)) { 3595 parm->err = USB_ERR_NOMEM; 3596 return; 3597 } 3598 if (parm->buf) { 3599 for (n = 0; n != nsitd; n++) { 3600 ehci_sitd_t *td; 3601 3602 usbd_get_page(pc + n, 0, &page_info); 3603 3604 td = (ehci_sitd_t *)page_info.buffer; 3605 3606 /* init TD */ 3607 #if USB_HAVE_BUSDMA 3608 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3609 #else 3610 td->sitd_self = htohc32(sc, (unsigned int)page_info.buffer | EHCI_LINK_SITD); 3611 #endif 3612 td->obj_next = (ehci_sitd_t *)last_obj; 3613 td->page_cache = pc + n; 3614 3615 last_obj = td; 3616 3617 usb_pc_cpu_flush(pc + n); 3618 } 3619 } 3620 if (usbd_transfer_setup_sub_malloc( 3621 parm, &pc, sizeof(ehci_qtd_t), 3622 EHCI_QTD_ALIGN, nqtd)) { 3623 parm->err = USB_ERR_NOMEM; 3624 return; 3625 } 3626 if (parm->buf) { 3627 for (n = 0; n != nqtd; n++) { 3628 ehci_qtd_t *qtd; 3629 3630 usbd_get_page(pc + n, 0, &page_info); 3631 3632 qtd = (ehci_qtd_t *)page_info.buffer; 3633 3634 /* init TD */ 3635 #if USB_HAVE_BUSDMA 3636 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3637 #else 3638 qtd->qtd_self = htohc32(sc, (unsigned int)page_info.buffer); 3639 #endif 3640 qtd->obj_next = (ehci_qtd_t *)last_obj; 3641 qtd->page_cache = pc + n; 3642 3643 last_obj = qtd; 3644 3645 usb_pc_cpu_flush(pc + n); 3646 } 3647 } 3648 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3649 3650 last_obj = NULL; 3651 3652 if (usbd_transfer_setup_sub_malloc( 3653 parm, &pc, sizeof(ehci_qh_t), 3654 EHCI_QH_ALIGN, nqh)) { 3655 parm->err = USB_ERR_NOMEM; 3656 return; 3657 } 3658 if (parm->buf) { 3659 for (n = 0; n != nqh; n++) { 3660 ehci_qh_t *qh; 3661 3662 usbd_get_page(pc + n, 0, &page_info); 3663 3664 qh = (ehci_qh_t *)page_info.buffer; 3665 3666 /* init QH */ 3667 #if USB_HAVE_BUSDMA 3668 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3669 #else 3670 qh->qh_self = htohc32(sc, (unsigned int)page_info.buffer | EHCI_LINK_QH); 3671 #endif 3672 qh->obj_next = (ehci_qh_t *)last_obj; 3673 qh->page_cache = pc + n; 3674 3675 last_obj = qh; 3676 3677 usb_pc_cpu_flush(pc + n); 3678 } 3679 } 3680 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3681 3682 if (!xfer->flags_int.curr_dma_set) { 3683 xfer->flags_int.curr_dma_set = 1; 3684 goto alloc_dma_set; 3685 } 3686 } 3687 3688 static void 3689 ehci_xfer_unsetup(struct usb_xfer *xfer) 3690 { 3691 return; 3692 } 3693 3694 static void 3695 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3696 struct usb_endpoint *ep) 3697 { 3698 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3699 3700 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3701 ep, udev->address, 3702 edesc->bEndpointAddress, udev->flags.usb_mode, 3703 sc->sc_addr); 3704 3705 if (udev->device_index != sc->sc_addr) { 3706 if ((udev->speed != USB_SPEED_HIGH) && 3707 ((udev->hs_hub_addr == 0) || 3708 (udev->hs_port_no == 0) || 3709 (udev->parent_hs_hub == NULL) || 3710 (udev->parent_hs_hub->hub == NULL))) { 3711 /* We need a transaction translator */ 3712 DPRINTFN(2, "no hub or no port\n"); 3713 goto done; 3714 } 3715 switch (edesc->bmAttributes & UE_XFERTYPE) { 3716 case UE_CONTROL: 3717 ep->methods = &ehci_device_ctrl_methods; 3718 DPRINTFN(2, "UE_CONTROL\n"); 3719 break; 3720 case UE_INTERRUPT: 3721 ep->methods = &ehci_device_intr_methods; 3722 DPRINTFN(2, "UE_INTERRUPT\n"); 3723 break; 3724 case UE_ISOCHRONOUS: 3725 if (udev->speed == USB_SPEED_HIGH) { 3726 ep->methods = &ehci_device_isoc_hs_methods; 3727 } else if (udev->speed == USB_SPEED_FULL) { 3728 ep->methods = &ehci_device_isoc_fs_methods; 3729 } 3730 DPRINTFN(2, "UE_ISOCHRONOUS\n"); 3731 break; 3732 case UE_BULK: 3733 ep->methods = &ehci_device_bulk_methods; 3734 DPRINTFN(2, "UE_BULK\n"); 3735 break; 3736 default: 3737 /* do nothing */ 3738 break; 3739 } 3740 } 3741 done: 3742 return; 3743 } 3744 3745 static void 3746 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3747 { 3748 /* 3749 * Wait until the hardware has finished any possible use of 3750 * the transfer descriptor(s) and QH 3751 */ 3752 *pus = (1125); /* microseconds */ 3753 } 3754 3755 static void 3756 ehci_device_resume(struct usb_device *udev) 3757 { 3758 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3759 struct usb_xfer *xfer; 3760 const struct usb_pipe_methods *methods; 3761 3762 DPRINTF("\n"); 3763 3764 USB_BUS_LOCK(udev->bus); 3765 3766 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3767 if (xfer->xroot->udev == udev) { 3768 methods = xfer->endpoint->methods; 3769 3770 if ((methods == &ehci_device_bulk_methods) || 3771 (methods == &ehci_device_ctrl_methods)) { 3772 EHCI_APPEND_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 3773 sc->sc_async_p_last); 3774 } 3775 if (methods == &ehci_device_intr_methods) { 3776 EHCI_APPEND_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 3777 sc->sc_intr_p_last[xfer->qh_pos]); 3778 } 3779 } 3780 } 3781 3782 USB_BUS_UNLOCK(udev->bus); 3783 3784 return; 3785 } 3786 3787 static void 3788 ehci_device_suspend(struct usb_device *udev) 3789 { 3790 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3791 struct usb_xfer *xfer; 3792 const struct usb_pipe_methods *methods; 3793 3794 DPRINTF("\n"); 3795 3796 USB_BUS_LOCK(udev->bus); 3797 3798 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3799 3800 if (xfer->xroot->udev == udev) { 3801 3802 methods = xfer->endpoint->methods; 3803 3804 if ((methods == &ehci_device_bulk_methods) || 3805 (methods == &ehci_device_ctrl_methods)) { 3806 EHCI_REMOVE_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 3807 sc->sc_async_p_last); 3808 } 3809 if (methods == &ehci_device_intr_methods) { 3810 EHCI_REMOVE_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 3811 sc->sc_intr_p_last[xfer->qh_pos]); 3812 } 3813 } 3814 } 3815 3816 USB_BUS_UNLOCK(udev->bus); 3817 } 3818 3819 static void 3820 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3821 { 3822 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3823 3824 switch (state) { 3825 case USB_HW_POWER_SUSPEND: 3826 case USB_HW_POWER_SHUTDOWN: 3827 ehci_suspend(sc); 3828 break; 3829 case USB_HW_POWER_RESUME: 3830 ehci_resume(sc); 3831 break; 3832 default: 3833 break; 3834 } 3835 } 3836 3837 static void 3838 ehci_set_hw_power(struct usb_bus *bus) 3839 { 3840 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3841 uint32_t temp; 3842 uint32_t flags; 3843 3844 DPRINTF("\n"); 3845 3846 USB_BUS_LOCK(bus); 3847 3848 flags = bus->hw_power_state; 3849 3850 temp = EOREAD4(sc, EHCI_USBCMD); 3851 3852 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3853 3854 if (flags & (USB_HW_POWER_CONTROL | 3855 USB_HW_POWER_BULK)) { 3856 DPRINTF("Async is active\n"); 3857 temp |= EHCI_CMD_ASE; 3858 } 3859 if (flags & (USB_HW_POWER_INTERRUPT | 3860 USB_HW_POWER_ISOC)) { 3861 DPRINTF("Periodic is active\n"); 3862 temp |= EHCI_CMD_PSE; 3863 } 3864 EOWRITE4(sc, EHCI_USBCMD, temp); 3865 3866 USB_BUS_UNLOCK(bus); 3867 3868 return; 3869 } 3870 3871 static void 3872 ehci_start_dma_delay_second(struct usb_xfer *xfer) 3873 { 3874 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3875 3876 DPRINTF("\n"); 3877 3878 /* trigger doorbell */ 3879 ehci_doorbell_async(sc); 3880 3881 /* give the doorbell 4ms */ 3882 usbd_transfer_timeout_ms(xfer, 3883 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3884 } 3885 3886 /* 3887 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3888 * controllers apparently cache the QH descriptors and need a message 3889 * that the cache needs to be discarded. 3890 */ 3891 static void 3892 ehci_start_dma_delay(struct usb_xfer *xfer) 3893 { 3894 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3895 3896 DPRINTF("\n"); 3897 3898 /* trigger doorbell */ 3899 ehci_doorbell_async(sc); 3900 3901 /* give the doorbell 4ms */ 3902 usbd_transfer_timeout_ms(xfer, 3903 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3904 } 3905 3906 const struct usb_bus_methods ehci_bus_methods = { 3907 .endpoint_init = ehci_ep_init, 3908 .xfer_setup = ehci_xfer_setup, 3909 .xfer_unsetup = ehci_xfer_unsetup, 3910 .get_dma_delay = ehci_get_dma_delay, 3911 .device_resume = ehci_device_resume, 3912 .device_suspend = ehci_device_suspend, 3913 .set_hw_power = ehci_set_hw_power, 3914 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3915 .roothub_exec = ehci_roothub_exec, 3916 .xfer_poll = ehci_do_poll, 3917 .start_dma_delay = ehci_start_dma_delay, 3918 }; 3919 #undef USB_DEBUG_VAR 3920