Lines Matching +full:0 +full:x1821
158 u8 cls = 0; in pci_apply_final_quirks()
192 return 0; in pci_apply_final_quirks()
235 pci_read_config_byte(d, 0x82, &dlc); in quirk_passive_release()
239 pci_write_config_byte(d, 0x82, dlc); in quirk_passive_release()
282 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
283 pmbase = pmbase & 0xff80; in quirk_tigerpoint_bm_sts()
286 if (pm1a & 0x10) { in quirk_tigerpoint_bm_sts()
288 outw(0x10, pmbase); in quirk_tigerpoint_bm_sts()
296 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { in quirk_nopcipci()
307 pci_read_config_byte(dev, 0x08, &rev); in quirk_nopciamd()
308 if (rev == 0x13) { in quirk_nopciamd()
319 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { in quirk_triton()
352 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
356 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
364 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
380 pci_read_config_byte(dev, 0x76, &busarb); in quirk_vialatency()
383 * Set bit 4 and bit 5 of byte 76 to 0x01 in quirk_vialatency()
388 pci_write_config_byte(dev, 0x76, busarb); in quirk_vialatency()
404 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { in quirk_viaetbf()
413 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { in quirk_vsfx()
422 * space. Latency must be set to 0xA and Triton workaround applied too.
427 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { in quirk_alimagik()
438 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { in quirk_natoma()
451 * This chip can cause PCI parity errors if config register 0xA0 is read
456 dev->cfg_size = 0xA0; in quirk_citrine()
461 * This chip can cause bus lockups if config addresses above 0x600
466 dev->cfg_size = 0x600; in quirk_nfp6000()
478 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in quirk_extend_bar_to_page()
483 r->start = 0; in quirk_extend_bar_to_page()
490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
498 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
500 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
502 r->start = 0; in quirk_s3_64M()
503 r->end = 0x3ffffff; in quirk_s3_64M()
532 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", in quirk_io()
549 if (pci_resource_len(dev, 0) != 8) { in quirk_cs5536_vsa()
550 quirk_io(dev, 0, 8, name); /* SMB */ in quirk_cs5536_vsa()
586 * between 0x3b0->0x3bb or read 0x3d3
590 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); in quirk_ati_exploding_mce()
592 request_region(0x3b0, 0x0C, "RadeonIGP"); in quirk_ati_exploding_mce()
593 request_region(0x3d3, 0x01, "RadeonIGP"); in quirk_ati_exploding_mce()
599 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
604 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
644 PCI_CLASS_SERIAL_USB_XHCI, 0,
654 * 0xE0 (64 bytes of ACPI registers)
655 * 0xE2 (32 bytes of SMB registers)
659 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); in quirk_ali7101_acpi()
660 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); in quirk_ali7101_acpi()
673 base = devres & 0xffff; in piix4_io_quirk()
683 * reserve it (at least if it's in the 0x1000+ range), but in piix4_io_quirk()
698 base = devres & 0xffff0000; in piix4_mem_quirk()
699 mask = (devres & 0x3f) << 16; in piix4_mem_quirk()
718 * 0x40 (64 bytes of ACPI registers)
719 * 0x90 (16 bytes of SMB registers)
726 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); in quirk_piix4_acpi()
727 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); in quirk_piix4_acpi()
730 pci_read_config_dword(dev, 0x5c, &res_a); in quirk_piix4_acpi()
732 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); in quirk_piix4_acpi()
733 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); in quirk_piix4_acpi()
739 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); in quirk_piix4_acpi()
740 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); in quirk_piix4_acpi()
744 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); in quirk_piix4_acpi()
745 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); in quirk_piix4_acpi()
747 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); in quirk_piix4_acpi()
748 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); in quirk_piix4_acpi()
753 #define ICH_PMBASE 0x40
754 #define ICH_ACPI_CNTL 0x44
755 #define ICH4_ACPI_EN 0x10
756 #define ICH6_ACPI_EN 0x80
757 #define ICH4_GPIOBASE 0x58
758 #define ICH4_GPIO_CNTL 0x5c
759 #define ICH4_GPIO_EN 0x10
760 #define ICH6_GPIOBASE 0x48
761 #define ICH6_GPIO_CNTL 0x4c
762 #define ICH6_GPIO_EN 0x10
766 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
767 * 0x58 (64 bytes of GPIO I/O space)
827 base = val & 0xfffc; in ich6_lpc_generic_decode()
854 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
855 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
873 base = val & 0xfffc; in ich7_lpc_generic_decode()
874 mask = (val >> 16) & 0xfc; in ich7_lpc_generic_decode()
891 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
892 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
893 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
894 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
912 * 0x48 or 0x20 (256 bytes of ACPI registers)
916 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
917 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, in quirk_vt82c586_acpi()
924 * 0x48 (256 bytes of ACPI registers)
925 * 0x70 (128 bytes of hardware monitoring register)
926 * 0x90 (16 bytes of SMB registers)
932 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, in quirk_vt82c686_acpi()
935 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); in quirk_vt82c686_acpi()
941 * 0x88 (128 bytes of power management registers)
942 * 0xd0 (16 bytes of SMB registers)
946 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); in quirk_vt8235_acpi()
947 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); in quirk_vt8235_acpi()
986 tmp = 0; /* nothing routed to external APIC */ in quirk_via_ioapic()
988 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
991 tmp == 0 ? "Disa" : "Ena"); in quirk_via_ioapic()
993 /* Offset 0x58: External APIC IRQ output control */ in quirk_via_ioapic()
994 pci_write_config_byte(dev, 0x58, tmp); in quirk_via_ioapic()
1010 pci_read_config_byte(dev, 0x5B, &misc_control2); in quirk_via_vt8237_bypass_apic_deassert()
1013 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); in quirk_via_vt8237_bypass_apic_deassert()
1030 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1043 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1055 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1074 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ in quirk_via_acpi()
1075 pci_read_config_byte(d, 0x42, &irq); in quirk_via_acpi()
1076 irq &= 0xf; in quirk_via_acpi()
1149 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1174 pci_write_config_byte(dev, 0xfc, 0); in quirk_vt82c598_id()
1187 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); in quirk_cardbus_legacy()
1204 pci_read_config_dword(dev, 0x4C, &pcic); in quirk_amd_ordering()
1208 pci_write_config_dword(dev, 0x4C, pcic); in quirk_amd_ordering()
1209 pci_read_config_dword(dev, 0x84, &pcic); in quirk_amd_ordering()
1211 pci_write_config_dword(dev, 0x84, pcic); in quirk_amd_ordering()
1229 r->start = 0; in quirk_dunord()
1230 r->end = 0xffffff; in quirk_dunord()
1237 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1256 pci_read_config_byte(dev, 0x41, ®); in quirk_mediagx_master()
1259 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", in quirk_mediagx_master()
1261 pci_write_config_byte(dev, 0x41, reg); in quirk_mediagx_master()
1276 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1278 pci_read_config_word(pdev, 0x40, &config); in quirk_disable_pxb()
1281 pci_write_config_word(pdev, 0x40, config); in quirk_disable_pxb()
1294 if (tmp == 0x01) { in quirk_amd_ide_mode()
1295 pci_read_config_byte(pdev, 0x40, &tmp); in quirk_amd_ide_mode()
1296 pci_write_config_byte(pdev, 0x40, tmp|1); in quirk_amd_ide_mode()
1297 pci_write_config_byte(pdev, 0x9, 1); in quirk_amd_ide_mode()
1298 pci_write_config_byte(pdev, 0xa, 6); in quirk_amd_ide_mode()
1299 pci_write_config_byte(pdev, 0x40, tmp); in quirk_amd_ide_mode()
1311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1312 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1377 * package 2.7.0 for details)
1404 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1405 case 0x8070: /* P4B */ in asus_hides_smbus_hostbridge()
1406 case 0x8088: /* P4B533 */ in asus_hides_smbus_hostbridge()
1407 case 0x1626: /* L3C notebook */ in asus_hides_smbus_hostbridge()
1412 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1413 case 0x80b2: /* P4PE */ in asus_hides_smbus_hostbridge()
1414 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1419 case 0x8030: /* P4T533 */ in asus_hides_smbus_hostbridge()
1424 case 0x8070: /* P4G8X Deluxe */ in asus_hides_smbus_hostbridge()
1429 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1434 case 0x1751: /* M2N notebook */ in asus_hides_smbus_hostbridge()
1435 case 0x1821: /* M5N notebook */ in asus_hides_smbus_hostbridge()
1436 case 0x1897: /* A6L notebook */ in asus_hides_smbus_hostbridge()
1441 case 0x184b: /* W1N notebook */ in asus_hides_smbus_hostbridge()
1442 case 0x186a: /* M6Ne notebook */ in asus_hides_smbus_hostbridge()
1447 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1452 case 0x1882: /* M6V notebook */ in asus_hides_smbus_hostbridge()
1453 case 0x1977: /* A6VA notebook */ in asus_hides_smbus_hostbridge()
1459 case 0x088C: /* HP Compaq nc8000 */ in asus_hides_smbus_hostbridge()
1460 case 0x0890: /* HP Compaq nc6000 */ in asus_hides_smbus_hostbridge()
1465 case 0x12bc: /* HP D330L */ in asus_hides_smbus_hostbridge()
1466 case 0x12bd: /* HP D530 */ in asus_hides_smbus_hostbridge()
1467 case 0x006a: /* HP Compaq nx9500 */ in asus_hides_smbus_hostbridge()
1472 case 0x12bf: /* HP xw4100 */ in asus_hides_smbus_hostbridge()
1478 case 0xC00C: /* Samsung P35 notebook */ in asus_hides_smbus_hostbridge()
1484 case 0x0058: /* Compaq Evo N620c */ in asus_hides_smbus_hostbridge()
1489 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1497 case 0x00b8: /* Compaq Evo D510 CMT */ in asus_hides_smbus_hostbridge()
1498 case 0x00b9: /* Compaq Evo D510 SFF */ in asus_hides_smbus_hostbridge()
1499 case 0x00ba: /* Compaq Evo D510 USDT */ in asus_hides_smbus_hostbridge()
1509 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ in asus_hides_smbus_hostbridge()
1539 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1540 if (val & 0x8) { in asus_hides_smbus_lpc()
1541 pci_write_config_word(dev, 0xF2, val & (~0x8)); in asus_hides_smbus_lpc()
1542 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1543 if (val & 0x8) in asus_hides_smbus_lpc()
1544 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", in asus_hides_smbus_lpc()
1575 pci_read_config_dword(dev, 0xF0, &rcba); in asus_hides_smbus_lpc_ich6_suspend()
1577 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); in asus_hides_smbus_lpc_ich6_suspend()
1590 val = readl(asus_rcba_base + 0x3418); in asus_hides_smbus_lpc_ich6_resume_early()
1593 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); in asus_hides_smbus_lpc_ich6_resume_early()
1620 u8 val = 0; in quirk_sis_96x_smbus()
1621 pci_read_config_byte(dev, 0x77, &val); in quirk_sis_96x_smbus()
1622 if (val & 0x10) { in quirk_sis_96x_smbus()
1624 pci_write_config_byte(dev, 0x77, val & ~0x10); in quirk_sis_96x_smbus()
1644 #define SIS_DETECT_REGISTER 0x40
1654 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { in quirk_sis_503()
1679 int asus_hides_ac97 = 0; in asus_hides_ac97_lpc()
1689 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1690 if (val & 0xc0) { in asus_hides_ac97_lpc()
1691 pci_write_config_byte(dev, 0x50, val & (~0xc0)); in asus_hides_ac97_lpc()
1692 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1693 if (val & 0xc0) in asus_hides_ac97_lpc()
1694 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", in asus_hides_ac97_lpc()
1714 /* Only poke fn 0 */ in quirk_jmicron_ata()
1718 pci_read_config_dword(pdev, 0x40, &conf1); in quirk_jmicron_ata()
1719 pci_read_config_dword(pdev, 0x80, &conf5); in quirk_jmicron_ata()
1721 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1729 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ in quirk_jmicron_ata()
1740 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ in quirk_jmicron_ata()
1741 /* Set the class codes correctly and then direct IDE 0 */ in quirk_jmicron_ata()
1742 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ in quirk_jmicron_ata()
1747 conf1 |= 0x00C00000; /* Set 22, 23 */ in quirk_jmicron_ata()
1751 pci_write_config_dword(pdev, 0x40, conf1); in quirk_jmicron_ata()
1752 pci_write_config_dword(pdev, 0x80, conf5); in quirk_jmicron_ata()
1756 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1757 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1791 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, qu…
1792 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1793 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1800 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1808 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) in quirk_alder_ioapic()
1809 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1816 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1826 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1829 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1841 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch…
1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1874 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1876 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1877 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1878 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1879 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1880 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1881 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1882 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1883 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1884 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1902 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1921 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1922 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
1930 return 0; in dmi_disable_ioapicreroute()
2000 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2003 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2022 case 0x3c28: /* Xeon E5 1600/2600/4600 */ in quirk_disable_intel_boot_interrupt()
2023 case 0x0e28: /* Xeon E5/E7 V2 */ in quirk_disable_intel_boot_interrupt()
2024 case 0x2f28: /* Xeon E5/E7 V3,V4 */ in quirk_disable_intel_boot_interrupt()
2025 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2026 case 0x2034: /* Xeon Scalable Family */ in quirk_disable_intel_boot_interrupt()
2049 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2065 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2067 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2069 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2071 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2073 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2077 #define BC_HT1000_FEATURE_REG 0x64
2078 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2079 #define BC_HT1000_MAP_IDX 0xC00
2080 #define BC_HT1000_MAP_DATA 0xC01
2094 for (irq = 0x10; irq < 0x10 + 32; irq++) { in quirk_disable_broadcom_boot_interrupt()
2096 outb(0x00, BC_HT1000_MAP_DATA); in quirk_disable_broadcom_boot_interrupt()
2114 #define AMD_813X_MISC 0x40
2115 #define AMD_813X_NOIOAMODE (1<<0)
2116 #define AMD_813X_REV_B1 0x12
2117 #define AMD_813X_REV_B2 0x13
2141 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2156 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); in quirk_disable_amd_8111_boot_interrupt()
2171 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2173 if (r->start & 0x8) { in quirk_tc86c001_ide()
2175 r->start = 0; in quirk_tc86c001_ide()
2176 r->end = 0xf; in quirk_tc86c001_ide()
2187 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2197 for (bar = 0; bar <= 1; bar++) in quirk_plx_pci9050()
2198 if (pci_resource_len(dev, bar) == 0x80 && in quirk_plx_pci9050()
2199 (pci_resource_start(dev, bar) & 0x80)) { in quirk_plx_pci9050()
2204 r->start = 0; in quirk_plx_pci9050()
2205 r->end = 0xff; in quirk_plx_pci9050()
2211 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2212 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2213 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2214 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2216 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2219 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2220 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2224 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2225 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2234 * The subdevice ID is of the form 0x00PS, where <P> is the number in quirk_netmos()
2241 dev->subsystem_device == 0x0299) in quirk_netmos()
2252 (dev->class & 0xff); in quirk_netmos()
2267 case 0x1029: in quirk_e100_interrupt()
2268 case 0x1030 ... 0x1034: in quirk_e100_interrupt()
2269 case 0x1038 ... 0x103E: in quirk_e100_interrupt()
2270 case 0x1050 ... 0x1057: in quirk_e100_interrupt()
2271 case 0x1059: in quirk_e100_interrupt()
2272 case 0x1064 ... 0x106B: in quirk_e100_interrupt()
2273 case 0x1091 ... 0x1095: in quirk_e100_interrupt()
2274 case 0x1209: in quirk_e100_interrupt()
2275 case 0x1229: in quirk_e100_interrupt()
2276 case 0x2449: in quirk_e100_interrupt()
2277 case 0x2459: in quirk_e100_interrupt()
2278 case 0x245D: in quirk_e100_interrupt()
2279 case 0x27DC: in quirk_e100_interrupt()
2294 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) in quirk_e100_interrupt()
2308 csr = ioremap(pci_resource_start(dev, 0), 8); in quirk_e100_interrupt()
2315 if (cmd_hi == 0) { in quirk_e100_interrupt()
2334 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2335 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2345 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2346 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2347 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2375 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2376 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2377 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2401 pci_read_config_word(dev, 0x40, &en1k); in quirk_p64h2_1k_io()
2403 if (en1k & 0x200) { in quirk_p64h2_1k_io()
2408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2419 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2420 if (!(b & 0x20)) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2421 pci_write_config_byte(dev, 0xf41, b | 0x20); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2436 * bus leading to USB2.0 packet loss. in quirk_via_cx700_pci_parking_caching()
2457 if (pci_read_config_byte(dev, 0x76, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2458 if (b & 0x40) { in quirk_via_cx700_pci_parking_caching()
2460 pci_write_config_byte(dev, 0x76, b ^ 0x40); in quirk_via_cx700_pci_parking_caching()
2466 if (pci_read_config_byte(dev, 0x72, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2467 if (b != 0) { in quirk_via_cx700_pci_parking_caching()
2469 pci_write_config_byte(dev, 0x72, 0x0); in quirk_via_cx700_pci_parking_caching()
2472 pci_write_config_byte(dev, 0x75, 0x1); in quirk_via_cx700_pci_parking_caching()
2475 pci_write_config_byte(dev, 0x77, 0x0); in quirk_via_cx700_pci_parking_caching()
2481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2487 pci_read_config_dword(dev, 0xf4, &rev); in quirk_brcm_5719_limit_mrrs()
2490 if (rev == 0x05719000) { in quirk_brcm_5719_limit_mrrs()
2510 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { in quirk_unhide_mch_dev6()
2512 pci_write_config_byte(dev, 0xF4, reg | 0x02); in quirk_unhide_mch_dev6()
2540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2564 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2566 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2587 &flags) == 0) { in msi_ht_cap_enabled()
2591 return (flags & HT_MSI_FLAGS_ENABLE) != 0; in msi_ht_cap_enabled()
2597 return 0; in msi_ht_cap_enabled()
2626 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2648 &flags) == 0) { in ht_enable_msi_mapping()
2685 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2697 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2700 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2703 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2706 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2709 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2712 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2715 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2718 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2721 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2724 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2727 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2730 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2733 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2754 pci_read_config_dword(dev, 0x74, &cfg); in nvbridge_check_legacy_irq_routing()
2759 pci_write_config_dword(dev, 0x74, cfg); in nvbridge_check_legacy_irq_routing()
2772 int found = 0; in ht_check_msi_mapping()
2782 &flags) == 0) { in ht_check_msi_mapping()
2802 int found = 0; in host_bridge_with_leaf()
2805 for (i = dev_no + 1; i < 0x20; i++) { in host_bridge_with_leaf()
2806 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2812 if (pos != 0) { in host_bridge_with_leaf()
2834 int end = 0; in is_end_of_ht_chain()
2860 int found = 0; in nv_ht_enable_msi_mapping()
2863 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
2864 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
2869 if (pos != 0) { in nv_ht_enable_msi_mapping()
2903 &flags) == 0) { in ht_disable_msi_mapping()
2927 if (found == 0) in __nv_msi_ht_cap_quirk()
2934 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
2935 PCI_DEVFN(0, 0)); in __nv_msi_ht_cap_quirk()
2942 if (pos != 0) { in __nv_msi_ht_cap_quirk()
2974 return __nv_msi_ht_cap_quirk(dev, 0); in nv_msi_ht_cap_quirk_leaf()
2998 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3005 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ in quirk_msi_intx_disable_qca_bug()
3006 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3064 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3086 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3121 * live on PCI function 0, which might be the CardBus controller or the
3138 * This must be done via function #0 in ricoh_mmc_fixup_rl5c476()
3143 pci_read_config_byte(dev, 0xB7, &disable); in ricoh_mmc_fixup_rl5c476()
3144 if (disable & 0x02) in ricoh_mmc_fixup_rl5c476()
3147 pci_read_config_byte(dev, 0x8E, &write_enable); in ricoh_mmc_fixup_rl5c476()
3148 pci_write_config_byte(dev, 0x8E, 0xAA); in ricoh_mmc_fixup_rl5c476()
3149 pci_read_config_byte(dev, 0x8D, &write_target); in ricoh_mmc_fixup_rl5c476()
3150 pci_write_config_byte(dev, 0x8D, 0xB7); in ricoh_mmc_fixup_rl5c476()
3151 pci_write_config_byte(dev, 0xB7, disable | 0x02); in ricoh_mmc_fixup_rl5c476()
3152 pci_write_config_byte(dev, 0x8E, write_enable); in ricoh_mmc_fixup_rl5c476()
3153 pci_write_config_byte(dev, 0x8D, write_target); in ricoh_mmc_fixup_rl5c476()
3169 * This must be done via function #0 in ricoh_mmc_fixup_r5c832()
3174 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize in ricoh_mmc_fixup_r5c832()
3178 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3180 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3181 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3182 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3183 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3187 pci_write_config_byte(dev, 0xf9, 0xfc); in ricoh_mmc_fixup_r5c832()
3188 pci_write_config_byte(dev, 0x150, 0x10); in ricoh_mmc_fixup_r5c832()
3189 pci_write_config_byte(dev, 0xf9, 0x00); in ricoh_mmc_fixup_r5c832()
3190 pci_write_config_byte(dev, 0xfc, 0x01); in ricoh_mmc_fixup_r5c832()
3191 pci_write_config_byte(dev, 0xe1, 0x32); in ricoh_mmc_fixup_r5c832()
3192 pci_write_config_byte(dev, 0xfc, 0x00); in ricoh_mmc_fixup_r5c832()
3197 pci_read_config_byte(dev, 0xCB, &disable); in ricoh_mmc_fixup_r5c832()
3199 if (disable & 0x02) in ricoh_mmc_fixup_r5c832()
3202 pci_read_config_byte(dev, 0xCA, &write_enable); in ricoh_mmc_fixup_r5c832()
3203 pci_write_config_byte(dev, 0xCA, 0x57); in ricoh_mmc_fixup_r5c832()
3204 pci_write_config_byte(dev, 0xCB, disable | 0x02); in ricoh_mmc_fixup_r5c832()
3205 pci_write_config_byte(dev, 0xCA, write_enable); in ricoh_mmc_fixup_r5c832()
3220 #define VTUNCERRMSK_REG 0x1ac
3239 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3240 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3252 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3269 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3293 err = pci_read_config_word(dev, 0x48, &rcc); in quirk_intel_mc_errata()
3304 err = pci_write_config_word(dev, 0x48, rcc); in quirk_intel_mc_errata()
3313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3350 rc = pci_read_config_byte(dev, 0x00D0, &val); in quirk_intel_ntb()
3356 rc = pci_read_config_byte(dev, 0x00D1, &val); in quirk_intel_ntb()
3362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3377 #define I915_DEIER_REG 0x4400c
3380 void __iomem *regs = pci_iomap(dev, 0, 0); in disable_igfx_irq()
3387 if (readl(regs + I915_DEIER_REG) != 0) { in disable_igfx_irq()
3390 writel(0, regs + I915_DEIER_REG); in disable_igfx_irq()
3395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3409 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3449 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3451 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3468 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3470 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3471 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3472 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3473 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3474 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3475 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3476 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3477 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3478 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3479 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3520 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { in mellanox_check_broken_intx_masking()
3544 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); in mellanox_check_broken_intx_masking()
3553 fw_major = fw_maj_min & 0xffff; in mellanox_check_broken_intx_masking()
3555 fw_subminor = fw_sub_min & 0xffff; in mellanox_check_broken_intx_masking()
3583 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3717 acpi_execute_simple_method(SXFP, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3719 acpi_execute_simple_method(SXLV, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3720 acpi_execute_simple_method(SXIO, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3721 acpi_execute_simple_method(SXLV, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3745 return 0; in reset_intel_82599_sfp_virtfn()
3748 #define SOUTH_CHICKEN2 0xc2004
3749 #define PCH_PP_STATUS 0xc7200
3750 #define PCH_PP_CONTROL 0xc7204
3751 #define MSG_CTL 0x45010
3752 #define NSDE_PWR_STATE 0xd0100
3762 return 0; in reset_ivb_igd()
3764 mmio_base = pci_iomap(dev, 0, 0); in reset_ivb_igd()
3768 iowrite32(0x00000002, mmio_base + MSG_CTL); in reset_ivb_igd()
3776 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); in reset_ivb_igd()
3778 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; in reset_ivb_igd()
3784 if ((val & 0xb0000000) == 0) in reset_ivb_igd()
3791 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); in reset_ivb_igd()
3794 return 0; in reset_ivb_igd()
3807 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3811 * If this is the "probe" phase, return 0 indicating that we can in reset_chelsio_generic_dev()
3815 return 0; in reset_chelsio_generic_dev()
3841 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) in reset_chelsio_generic_dev()
3856 return 0; in reset_chelsio_generic_dev()
3859 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3860 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3861 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3883 !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) in nvme_disable_and_flr()
3887 return 0; in nvme_disable_and_flr()
3889 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); in nvme_disable_and_flr()
3941 return 0; in nvme_disable_and_flr()
3956 return 0; in delay_250ms_after_flr()
3962 return 0; in delay_250ms_after_flr()
3965 #define PCI_DEVICE_ID_HINIC_VF 0x375E
3966 #define HINIC_VF_FLR_TYPE 0x1000
3968 #define HINIC_VF_OP 0xE80
3980 return 0; in reset_hinic_vf_dev()
3982 bar = pci_iomap(pdev, 0, 0); in reset_hinic_vf_dev()
4005 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); in reset_hinic_vf_dev()
4025 return 0; in reset_hinic_vf_dev()
4035 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4036 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4041 { 0 }
4066 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4067 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4073 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4097 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
4130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4139 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4140 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4151 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4159 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4160 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4161 .driver_data = PCI_DEVFN(1, 0) },
4162 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4163 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4164 .driver_data = PCI_DEVFN(1, 0) },
4165 { 0 }
4176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4196 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4199 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4201 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4203 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4205 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4215 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); in quirk_mic_x200_dma_alias()
4216 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); in quirk_mic_x200_dma_alias()
4217 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); in quirk_mic_x200_dma_alias()
4219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4231 * All possible slot numbers (0x20) are used, since we are unable to tell
4238 const unsigned int num_pci_slots = 0x20; in quirk_pex_vca_alias()
4241 for (slot = 0; slot < num_pci_slots; slot++) in quirk_pex_vca_alias()
4242 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); in quirk_pex_vca_alias()
4244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4249 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4274 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4278 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4280 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4282 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4284 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4303 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4305 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4307 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4309 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4311 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4313 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4315 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4317 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4319 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4321 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4323 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4325 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4327 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4329 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4331 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4333 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4335 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4337 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4339 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4341 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4343 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4345 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4347 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4349 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4351 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4353 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4355 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4357 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4369 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4371 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4373 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4377 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4412 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); in quirk_disable_root_port_attributes()
4424 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely in quirk_chelsio_T5_disable_root_port_attributes()
4425 * 0x54xx so we use that one. in quirk_chelsio_T5_disable_root_port_attributes()
4427 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4442 * caller desires. Return 0 otherwise.
4448 return 0; in pci_acs_ctrl_enabled()
4487 status = acpi_get_table("IVRS", 0, &header); in pci_quirk_amd_sb_acs()
4512 case 0xa000 ... 0xa7ff: /* ThunderX1 */ in pci_quirk_cavium_acs_match()
4513 case 0xaf84: /* ThunderX2 */ in pci_quirk_cavium_acs_match()
4514 case 0xb884: /* ThunderX3 */ in pci_quirk_cavium_acs_match()
4566 case 0x0710 ... 0x071e: in pci_quirk_zhaoxin_pcie_ports_acs()
4567 case 0x0721: in pci_quirk_zhaoxin_pcie_ports_acs()
4568 case 0x0723 ... 0x0752: in pci_quirk_zhaoxin_pcie_ports_acs()
4584 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4585 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4587 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4588 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4590 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4591 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4593 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4594 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4596 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4597 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4599 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4600 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4602 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4604 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4605 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4607 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4618 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) in pci_quirk_intel_pch_acs_match()
4634 return pci_acs_ctrl_enabled(acs_flags, 0); in pci_quirk_intel_pch_acs()
4680 return acs_flags ? 0 : 1; in pci_quirk_al_acs()
4693 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4694 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4706 * 0xa290-0xa29f PCI Express Root port #{0-16}
4707 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4718 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4734 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ in pci_quirk_intel_spt_pch_acs_match()
4735 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ in pci_quirk_intel_spt_pch_acs_match()
4736 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ in pci_quirk_intel_spt_pch_acs_match()
4818 case 0x0100 ... 0x010F: in pci_quirk_wangxun_nic_acs()
4819 case 0x1001: in pci_quirk_wangxun_nic_acs()
4820 case 0x2001: in pci_quirk_wangxun_nic_acs()
4833 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4834 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4835 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4836 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4837 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4838 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4839 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4840 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4841 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4842 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4843 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4844 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4845 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4846 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4847 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4848 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4849 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4850 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4851 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4852 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4853 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4854 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4855 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4856 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4857 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4858 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4859 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4860 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4861 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4862 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4863 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4865 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4866 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4867 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4868 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4869 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4870 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4871 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4873 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4874 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4875 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4876 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4877 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4878 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4879 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4880 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4882 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4883 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4884 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4886 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4887 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4888 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4889 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4891 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4892 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4893 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4894 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4896 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4897 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4900 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4901 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4903 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4907 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4908 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4912 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
4913 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
4914 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
4916 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4918 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4919 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4920 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4921 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4922 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4923 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4924 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4925 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4927 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4928 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
4929 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
4930 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
4931 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4933 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4935 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4936 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4937 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4940 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
4941 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
4942 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
4944 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
4945 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
4946 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
4948 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
4949 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
4950 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
4952 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
4953 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
4954 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
4956 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
4957 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
4958 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
4960 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
4961 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
4962 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
4964 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
4965 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
4966 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
4968 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
4969 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
4970 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
4975 { 0 }
4986 * 0: Device does not provide all the desired controls
4987 * >0: Device provides all the controls in @acs_flags
5006 if (ret >= 0) in pci_dev_specific_acs_enabled()
5015 #define INTEL_LPC_RCBA_REG 0xf0
5017 #define INTEL_LPC_RCBA_MASK 0xffffc000
5019 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5022 #define INTEL_BSPR_REG 0x1104
5029 #define INTEL_UPDCR_REG 0x1014
5030 /* 5:0 Peer Decode Enable bits */
5031 #define INTEL_UPDCR_REG_MASK 0x3f
5043 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5072 return 0; in pci_quirk_enable_intel_lpc_acs()
5076 #define INTEL_MPC_REG 0xd8
5112 return 0; in pci_quirk_enable_intel_pch_acs()
5121 return 0; in pci_quirk_enable_intel_pch_acs()
5151 return 0; in pci_quirk_enable_intel_spt_pch_acs()
5175 return 0; in pci_quirk_disable_intel_spt_pch_acs_redir()
5198 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { in pci_dev_specific_enable_acs()
5206 if (ret >= 0) in pci_dev_specific_enable_acs()
5219 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { in pci_dev_specific_disable_acs_redir()
5227 if (ret >= 0) in pci_dev_specific_disable_acs_redir()
5236 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5239 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5244 int pos, i = 0; in quirk_intel_qat_vf_cap()
5260 * is not the expected incorrect 0x00. in quirk_intel_qat_vf_cap()
5267 * PCIe Capability Structure is expected to be at 0x50 and should in quirk_intel_qat_vf_cap()
5268 * terminate the list (Next Capability pointer is 0x00). Verify in quirk_intel_qat_vf_cap()
5274 pos = 0x50; in quirk_intel_qat_vf_cap()
5276 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { in quirk_intel_qat_vf_cap()
5291 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) in quirk_intel_qat_vf_cap()
5303 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5305 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5316 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5321 * AMD Starship/Matisse HD Audio Controller 0x1487
5322 * AMD Starship USB 3.0 Host Controller 0x148c
5323 * AMD Matisse USB 3.0 Host Controller 0x149c
5324 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5325 * Intel 82579V Gigabit Ethernet Controller 0x1503
5332 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5333 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5334 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5335 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5336 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5337 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5351 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5352 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5353 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5354 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5355 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5356 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5357 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5363 pdev->ats_cap = 0; in quirk_no_ats()
5373 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || in quirk_amd_harvest_no_ats()
5374 (pdev->device == 0x7340 && pdev->revision != 0xc5) || in quirk_amd_harvest_no_ats()
5375 (pdev->device == 0x7341 && pdev->revision != 0x00)) in quirk_amd_harvest_no_ats()
5382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5397 if (pdev->revision < 0x20) in quirk_intel_e2000_no_ats()
5400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
5401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
5402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
5403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
5404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
5405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
5406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
5407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
5408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
5462 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_hda()
5477 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_usb()
5490 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5493 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_usb_typec_ucsi()
5515 /* Bit 25 at offset 0x488 enables the HDA controller */ in quirk_nvidia_hda()
5516 pci_read_config_dword(gpu, 0x488, &val); in quirk_nvidia_hda()
5521 pci_write_config_dword(gpu, 0x488, val | BIT(25)); in quirk_nvidia_hda()
5525 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5534 * completions for config read requests even though PCIe r4.0, sec
5547 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5560 u16 ctrl = 0; in pci_idt_bus_quirk()
5578 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); in pci_idt_bus_quirk()
5608 mmio = pci_iomap(pdev, 0, 0); in quirk_switchtec_ntb_dma_alias()
5626 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { in quirk_switchtec_ntb_dma_alias()
5628 u32 table_sz = 0; in quirk_switchtec_ntb_dma_alias()
5640 pci_warn(pdev, "Partition %d table_sz 0\n", pp); in quirk_switchtec_ntb_dma_alias()
5651 for (te = 0; te < table_sz; te++) { in quirk_switchtec_ntb_dma_alias()
5656 devfn = (rid_entry >> 1) & 0xFF; in quirk_switchtec_ntb_dma_alias()
5671 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5672 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5673 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5674 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5675 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5676 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5677 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5678 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5679 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5680 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5681 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5682 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5683 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5684 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5685 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5686 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5687 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5688 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5689 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5690 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5691 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5692 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5693 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5694 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5695 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5696 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5697 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5698 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5699 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5700 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5701 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5702 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5703 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5704 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5705 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5706 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5707 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5708 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5709 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5710 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5711 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5712 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5713 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5714 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5715 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5716 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5717 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5718 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5730 pci_add_dma_alias(pdev, 0, 256); in quirk_plx_ntb_dma_alias()
5732 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5733 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5757 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5768 map = pci_iomap(pdev, 0, 0x23000); in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5778 if (ioread32(map + 0x2240c) & 0x2) { in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5781 if (ret < 0) in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5789 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5805 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5821 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
5823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
5824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
5830 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);