Lines Matching +full:test +full:- +full:manual +full:- +full:mr
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
63 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
64 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
65 (f->vendor == dev->vendor || in pci_do_fixups()
66 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
67 (f->device == dev->device || in pci_do_fixups()
68 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
71 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
73 hook = f->hook; in pci_do_fixups()
199 * key system devices. For devices that need to have mmio decoding always-on,
200 * we need to set the dev->mmio_always_on bit.
204 dev->mmio_always_on = 1; in quirk_mmio_always_on()
216 dev->broken_parity_status = 1; /* This device gives false positives */ in quirk_mellanox_tavor()
249 * contacts at VIA ask them for me please -- Alan
293 /* Chipsets where PCI->PCI transfers vanish or hang */
331 * Made according to a Windows driver-based patch by George E. Breese;
333 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
334 * which Mr Breese based his work.
352 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
356 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
364 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
456 dev->cfg_size = 0xA0; in quirk_citrine()
466 dev->cfg_size = 0x600; in quirk_nfp6000()
479 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
481 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { in quirk_extend_bar_to_page()
482 r->end = PAGE_SIZE - 1; in quirk_extend_bar_to_page()
483 r->start = 0; in quirk_extend_bar_to_page()
484 r->flags |= IORESOURCE_UNSET; in quirk_extend_bar_to_page()
494 * If it's needed, re-allocate the region.
498 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
500 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
501 r->flags |= IORESOURCE_UNSET; in quirk_s3_64M()
502 r->start = 0; in quirk_s3_64M()
503 r->end = 0x3ffffff; in quirk_s3_64M()
514 struct resource *res = dev->resource + pos; in quirk_io()
521 res->name = pci_name(dev); in quirk_io()
522 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
523 res->flags |= in quirk_io()
525 region &= ~(size - 1); in quirk_io()
529 bus_region.end = region + size - 1; in quirk_io()
530 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
542 * CS553x's ISA PCI BARs may also be read-only (ref:
543 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
564 struct resource *res = dev->resource + nr; in quirk_io_region()
567 region &= ~(size - 1); in quirk_io_region()
572 res->name = pci_name(dev); in quirk_io_region()
573 res->flags = IORESOURCE_IO; in quirk_io_region()
577 bus_region.end = region + size - 1; in quirk_io_region()
578 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
586 * between 0x3b0->0x3bb or read 0x3d3
610 u32 class = pdev->class; in quirk_amd_dwc_class()
613 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_amd_dwc_class()
614 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_amd_dwc_class()
615 class, pdev->class); in quirk_amd_dwc_class()
625 * devices should use dwc3-haps driver. Change these devices' class code to
626 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
631 u32 class = pdev->class; in quirk_synopsys_haps()
633 switch (pdev->device) { in quirk_synopsys_haps()
637 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_synopsys_haps()
638 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_synopsys_haps()
639 class, pdev->class); in quirk_synopsys_haps()
686 base &= -size; in piix4_io_quirk()
687 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
712 base &= -size; in piix4_mem_quirk()
713 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
765 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
839 base &= ~(size-1); in ich6_lpc_generic_decode()
845 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
853 /* ICH6-specific generic IO decode */ in quirk_ich6_lpc()
872 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ in ich7_lpc_generic_decode()
884 /* ICH7-10 has the same common LPC generic IO decode registers */
916 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
933 "vt82c686 HW-mon"); in quirk_vt82c686_acpi()
952 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
953 * back-to-back: Disable fast back-to-back on the secondary bus segment
960 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
961 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
975 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
978 * TODO: When we have device-specific interrupt routers, this code will go
988 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
1000 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1012 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1020 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1030 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1042 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ in quirk_cavium_sriov_rnm_link()
1043 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1044 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1051 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1055 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1056 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1057 dev->revision); in quirk_amd_8131_mmrbc()
1058 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1068 * -jgarzik
1078 d->irq = irq; in quirk_via_acpi()
1084 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1089 switch (dev->device) { in quirk_via_bridge()
1096 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1097 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1124 * quirk_via_vlink - VIA VLink IRQ number update
1139 if (via_vlink_dev_lo == -1) in quirk_via_vlink()
1142 new_irq = dev->irq; in quirk_via_vlink()
1149 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1150 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1175 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1218 * DreamWorks-provided workaround for Dunord I-3000 problem
1226 struct resource *r = &dev->resource[1]; in quirk_dunord()
1228 r->flags |= IORESOURCE_UNSET; in quirk_dunord()
1229 r->start = 0; in quirk_dunord()
1230 r->end = 0xffffff; in quirk_dunord()
1235 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1237 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1241 dev->transparent = 1; in quirk_transparent_bridge()
1276 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1290 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ in quirk_amd_ide_mode()
1301 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; in quirk_amd_ide_mode()
1321 pdev->class &= ~5; in quirk_svwks_csb5ide()
1328 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1338 pdev->class &= ~5; in quirk_ide_samemode()
1347 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; in quirk_no_ata_d3()
1363 * This was originally an Alpha-specific thing, but it really fits here.
1364 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1368 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1381 * becomes necessary to do this tweak in two steps -- the chosen trigger
1382 * is either the Host bridge (preferred) or on-board VGA controller.
1395 * the DSDT and double-check that there is no code accessing the SMBus.
1401 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1402 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1403 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1404 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1410 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1411 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1412 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1414 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1417 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1418 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1422 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1423 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1427 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1428 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1429 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1432 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1433 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1439 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1440 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1445 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1446 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1447 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1450 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1451 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1456 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1457 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1458 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1463 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1464 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1470 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1471 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1475 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1476 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1477 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1481 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1482 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1483 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1487 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1488 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1489 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1492 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1495 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1496 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1501 * subvendor/subdevice IDs and on-board VGA in asus_hides_smbus_hostbridge()
1507 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1508 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1512 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1664 dev->device = devid; in quirk_sis_503()
1674 * -- bjd
1681 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1682 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1715 if (PCI_FUNC(pdev->devfn)) in quirk_jmicron_ata()
1721 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1724 switch (pdev->device) { in quirk_jmicron_ata()
1756 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1757 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1760 pdev->class = class >> 8; in quirk_jmicron_ata()
1785 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1786 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1787 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1800 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1804 * The first BAR is the location of the IO-APIC... we must in quirk_alder_ioapic()
1809 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1816 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1824 dev->no_msi = 1; in quirk_no_msi()
1835 pdev->no_msi = 1; in quirk_pcie_mch()
1845 * together on certain PXH-based systems.
1849 dev->no_msi = 1; in quirk_pcie_pxh()
1865 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
1891 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
1894 dev->d3hot_delay = delay; in quirk_d3hot_delay()
1895 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
1896 dev->d3hot_delay); in quirk_d3hot_delay()
1901 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
1902 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
1913 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1928 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); in dmi_disable_ioapicreroute()
1939 .ident = "ASUSTek Computer INC. M2N-LR",
1942 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1960 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
1962 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
1987 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1988 * 300641-004US, section 5.7.3.
1990 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1991 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1992 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1993 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1994 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1995 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1996 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1997 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2014 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2025 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2037 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2040 * Device 29 Func 5 Device IDs of IO-APIC
2076 /* Disable boot interrupts on HT-1000 */
2102 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2111 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2125 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2126 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2134 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2153 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2158 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2165 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2167 * Re-allocate the region if needed...
2171 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2173 if (r->start & 0x8) { in quirk_tc86c001_ide()
2174 r->flags |= IORESOURCE_UNSET; in quirk_tc86c001_ide()
2175 r->start = 0; in quirk_tc86c001_ide()
2176 r->end = 0xf; in quirk_tc86c001_ide()
2188 * Re-allocate the regions to a 256-byte boundary if necessary.
2195 if (dev->revision >= 2) in quirk_plx_pci9050()
2200 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2201 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2203 r->flags |= IORESOURCE_UNSET; in quirk_plx_pci9050()
2204 r->start = 0; in quirk_plx_pci9050()
2205 r->end = 0xff; in quirk_plx_pci9050()
2224 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2225 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2237 switch (dev->device) { in quirk_netmos()
2240 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2241 dev->subsystem_device == 0x0299) in quirk_netmos()
2250 dev->device, num_parallel, num_serial); in quirk_netmos()
2251 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2252 (dev->class & 0xff); in quirk_netmos()
2265 switch (dev->device) { in quirk_e100_interrupt()
2290 * re-enable them when it's ready. in quirk_e100_interrupt()
2301 if (dev->pm_cap) { in quirk_e100_interrupt()
2302 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2356 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2363 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2372 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2381 u32 class = dev->class; in fixup_rev1_53c810()
2390 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2391 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2392 class, dev->class); in fixup_rev1_53c810()
2405 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2439 * VT6212L is found -- the CX700 core itself also contains a USB in quirk_via_cx700_pci_parking_caching()
2449 * p should contain the first (internal) VT6212L -- see if we have in quirk_via_cx700_pci_parking_caching()
2471 /* Set PCI Master Bus time-out to "1x16 PCLK" */ in quirk_via_cx700_pci_parking_caching()
2503 * DRBs - this is where we expose device 6.
2504 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2545 if (dev->subordinate) { in quirk_disable_msi()
2547 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2564 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2566 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2583 while (pos && ttl--) { in msi_ht_cap_enabled()
2603 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { in quirk_msi_ht_cap()
2605 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_msi_ht_cap()
2619 if (!dev->subordinate) in quirk_nvidia_ck804_msi_ht_cap()
2626 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2631 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_nvidia_ck804_msi_ht_cap()
2644 while (pos && ttl--) { in ht_enable_msi_mapping()
2665 * The P5N32-SLI motherboards from Asus have a problem with MSI
2674 (strstr(board_name, "P5N32-SLI PREMIUM") || in nvenet_msi_disable()
2675 strstr(board_name, "P5N32-E SLI"))) { in nvenet_msi_disable()
2676 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2677 dev->no_msi = 1; in nvenet_msi_disable()
2685 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2690 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2695 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2776 while (pos && ttl--) { in ht_check_msi_mapping()
2804 dev_no = host_bridge->devfn >> 3; in host_bridge_with_leaf()
2806 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2862 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
2863 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
2864 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
2899 while (pos && ttl--) { in ht_disable_msi_mapping()
2932 * a non-Hypertransport host bridge. Locate the host bridge... in __nv_msi_ht_cap_quirk()
2934 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
2981 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
2998 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
2999 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3006 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3008 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3072 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3076 * tested), since currently there is no standard way to disable only MSI-X.
3083 dev->no_msi = 1; in quirk_al_msi_disable()
3084 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3091 * Allow manual resource allocation for PCI hotplug bridges via
3092 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3099 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3116 * MMC controller - so the SDHCI driver never sees them.
3140 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3171 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3178 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3180 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3181 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3182 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3183 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3185 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3186 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3223 * This is a quirk for masking VT-d spec-defined errors to platform error
3226 * on the RAS config settings of the platform) when a VT-d fault happens.
3229 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3245 u32 class = dev->class; in fixup_ti816x_class()
3248 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3249 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3250 class, dev->class); in fixup_ti816x_class()
3261 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3276 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3312 /* Intel 5000 series memory controllers and ports 2-7 */
3327 /* Intel 5100 series memory controllers and ports 2-7 */
3354 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3360 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3369 * and the interrupt ends up -somewhere-.
3409 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3415 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3445 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3458 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3465 * DisINTx can be set but the interrupt status bit is non-functional.
3505 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3521 if (pdev->device == mellanox_broken_intx_devs[i]) { in mellanox_check_broken_intx_masking()
3522 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3528 * Getting here means Connect-IB cards and up. Connect-IB has no INTx in mellanox_check_broken_intx_masking()
3531 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) in mellanox_check_broken_intx_masking()
3534 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && in mellanox_check_broken_intx_masking()
3535 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) in mellanox_check_broken_intx_masking()
3538 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ in mellanox_check_broken_intx_masking()
3546 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); in mellanox_check_broken_intx_masking()
3558 …pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW… in mellanox_check_broken_intx_masking()
3559 fw_major, fw_minor, fw_subminor, pdev->device == in mellanox_check_broken_intx_masking()
3561 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3574 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3583 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3591 * The device will throw a Link Down error on AER-capable systems and
3626 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3627 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3631 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3632 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3648 if (pdev->is_hotplug_bridge && in quirk_thunderbolt_hotplug_msi()
3649 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || in quirk_thunderbolt_hotplug_msi()
3650 pdev->revision <= 1)) in quirk_thunderbolt_hotplug_msi()
3651 pdev->no_msi = 1; in quirk_thunderbolt_hotplug_msi()
3698 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3729 * Following are device-specific reset methods which can be used to
3730 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3736 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf in reset_intel_82599_sfp_virtfn()
3766 return -ENOMEM; in reset_ivb_igd()
3797 /* Device-specific reset method for Chelsio T4-based adapters */
3804 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating in reset_chelsio_generic_dev()
3805 * that we have no device-specific reset method. in reset_chelsio_generic_dev()
3807 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3808 return -ENOTTY; in reset_chelsio_generic_dev()
3834 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts in reset_chelsio_generic_dev()
3835 * are disabled when an MSI-X interrupt message needs to be delivered. in reset_chelsio_generic_dev()
3836 * So we briefly re-enable MSI-X interrupts for the duration of the in reset_chelsio_generic_dev()
3838 * MSI-X state. in reset_chelsio_generic_dev()
3840 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
3842 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
3865 * FLR where config space reads from the device return -1. We seem to be
3882 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
3884 return -ENOTTY; in nvme_disable_and_flr()
3891 return -ENOTTY; in nvme_disable_and_flr()
3953 return -ENOTTY; in delay_250ms_after_flr()
3972 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
3984 return -ENOTTY; in reset_hinic_vf_dev()
3990 return -ENOTTY; in reset_hinic_vf_dev()
4045 * These device-specific reset methods are here rather than in a driver
4053 for (i = pci_dev_reset_methods; i->reset; i++) { in pci_dev_specific_reset()
4054 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4055 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_reset()
4056 (i->device == dev->device || in pci_dev_specific_reset()
4057 i->device == (u16)PCI_ANY_ID)) in pci_dev_specific_reset()
4058 return i->reset(dev, probe); in pci_dev_specific_reset()
4061 return -ENOTTY; in pci_dev_specific_reset()
4066 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4067 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4080 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4081 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4139 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4149 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4174 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4179 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4181 * used as either forward or reverse bridges, so we need to test whether the
4183 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4184 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4185 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4189 if (!pci_is_root_bus(pdev->bus) && in quirk_use_pcie_bridge_dma_alias()
4190 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in quirk_use_pcie_bridge_dma_alias()
4191 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && in quirk_use_pcie_bridge_dma_alias()
4192 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) in quirk_use_pcie_bridge_dma_alias()
4193 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; in quirk_use_pcie_bridge_dma_alias()
4210 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4223 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4258 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; in quirk_bridge_cavm_thrx2_pcie_root()
4266 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4271 u32 class = pdev->class; in quirk_tw686x_class()
4274 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4275 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", in quirk_tw686x_class()
4276 class, pdev->class); in quirk_tw686x_class()
4294 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4381 * If a non-compliant device generates a completion with a different
4383 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4387 * If the non-compliant device generates completions with zero attributes
4409 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4427 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4434 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4452 * AMD has indicated that the devices below do not support peer-to-peer
4455 * peer-to-peer between functions can claim to support a subset of ACS.
4483 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4484 return -ENODEV; in pci_quirk_amd_sb_acs()
4489 return -ENODEV; in pci_quirk_amd_sb_acs()
4498 return -ENODEV; in pci_quirk_amd_sb_acs()
4507 switch (dev->device) { in pci_quirk_cavium_acs_match()
4524 return -ENOTTY; in pci_quirk_cavium_acs()
4541 * X-Gene Root Ports matching this quirk do not allow peer-to-peer in pci_quirk_xgene_acs()
4551 * But the implementation could block peer-to-peer transactions between them
4552 * and provide ACS-like functionality.
4559 return -ENOTTY; in pci_quirk_zhaoxin_pcie_ports_acs()
4565 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4577 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4592 /* Lynxpoint-H PCH */
4595 /* Lynxpoint-LP PCH */
4614 /* Filter out a few obvious non-matches first */ in pci_quirk_intel_pch_acs_match()
4619 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4628 return -ENOTTY; in pci_quirk_intel_pch_acs()
4630 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4638 * These QCOM Root Ports do provide ACS-like features to disable peer
4642 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4668 return -ENOTTY; in pci_quirk_al_acs()
4672 * but do include ACS-like functionality. The hardware doesn't support in pci_quirk_al_acs()
4673 * peer-to-peer transactions via the root port and each has a unique in pci_quirk_al_acs()
4693 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4694 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4702 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4706 * 0xa290-0xa29f PCI Express Root port #{0-16}
4707 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4713 * August 2017, Revision 002, Document#: 334660-002)[6]
4716 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4718 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4720 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4721 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4722 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4723 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4724 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4725 …ww.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-…
4726 …tel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datas…
4733 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4751 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4753 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4755 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4772 * in their ACS capability if they support peer-to-peer transactions. in pci_quirk_mf_endpoint_acs()
4774 * perform peer-to-peer with other functions, allowing us to mask out in pci_quirk_mf_endpoint_acs()
4786 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, in pci_quirk_rciep_acs()
4787 * "Root-Complex Peer to Peer Considerations". in pci_quirk_rciep_acs()
4790 return -ENOTTY; in pci_quirk_rciep_acs()
4800 * they do not allow peer-to-peer transactions between Root Ports. in pci_quirk_brcm_acs()
4809 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4810 * devices, peer-to-peer transactions are not be used between the functions.
4817 switch (dev->device) { in pci_quirk_wangxun_nic_acs()
4890 /* 82571 (Quads omitted due to non-ACS switch) */
4907 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4908 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4911 /* Cavium multi-function devices */
4915 /* APM X-Gene */
4926 /* Broadcom multi-function device */
4934 /* Zhaoxin multi-function devices */
4939 /* LX2xx0A : without security features + CAN-FD */
4943 /* LX2xx0C : security features + CAN-FD */
4955 /* LX2xx2A : without security features + CAN-FD */
4959 /* LX2xx2C : security features + CAN-FD */
4979 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4984 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4996 * or control to indicate their support here. Multi-function express in pci_dev_specific_acs_enabled()
4997 * devices which do not allow internal peer-to-peer between functions, in pci_dev_specific_acs_enabled()
5000 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { in pci_dev_specific_acs_enabled()
5001 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
5002 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_acs_enabled()
5003 (i->device == dev->device || in pci_dev_specific_acs_enabled()
5004 i->device == (u16)PCI_ANY_ID)) { in pci_dev_specific_acs_enabled()
5005 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
5011 return -ENOTTY; in pci_dev_specific_acs_enabled()
5023 /* Backbone Peer Non-Posted Disable */
5043 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5046 return -EINVAL; in pci_quirk_enable_intel_lpc_acs()
5051 return -ENOMEM; in pci_quirk_enable_intel_lpc_acs()
5055 * therefore read-only. If both posted and non-posted peer cycles are in pci_quirk_enable_intel_lpc_acs()
5103 * if dev->external_facing || dev->untrusted
5108 return -ENOTTY; in pci_quirk_enable_intel_pch_acs()
5117 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5130 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5132 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5134 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5144 if (dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5160 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5162 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5164 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5200 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5201 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5202 (p->device == dev->device || in pci_dev_specific_enable_acs()
5203 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5204 p->enable_acs) { in pci_dev_specific_enable_acs()
5205 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5211 return -ENOTTY; in pci_dev_specific_enable_acs()
5221 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5222 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5223 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5224 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5225 p->disable_acs_redir) { in pci_dev_specific_disable_acs_redir()
5226 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5232 return -ENOTTY; in pci_dev_specific_disable_acs_redir()
5250 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) in quirk_intel_qat_vf_cap()
5270 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() in quirk_intel_qat_vf_cap()
5283 pdev->pcie_cap = pos; in quirk_intel_qat_vf_cap()
5285 pdev->pcie_flags_reg = reg16; in quirk_intel_qat_vf_cap()
5287 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in quirk_intel_qat_vf_cap()
5289 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in quirk_intel_qat_vf_cap()
5292 pdev->cfg_size = PCI_CFG_SPACE_SIZE; in quirk_intel_qat_vf_cap()
5302 state->cap.cap_nr = PCI_CAP_ID_EXP; in quirk_intel_qat_vf_cap()
5303 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5304 state->cap.size = size; in quirk_intel_qat_vf_cap()
5305 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5313 hlist_add_head(&state->next, &pdev->saved_cap_space); in quirk_intel_qat_vf_cap()
5330 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5341 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); in quirk_no_ext_tags()
5346 bridge->no_ext_tags = 1; in quirk_no_ext_tags()
5349 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); in quirk_no_ext_tags()
5363 pdev->ats_cap = 0; in quirk_no_ats()
5373 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || in quirk_amd_harvest_no_ats()
5374 (pdev->device == 0x7340 && pdev->revision != 0xc5) || in quirk_amd_harvest_no_ats()
5375 (pdev->device == 0x7341 && pdev->revision != 0x00)) in quirk_amd_harvest_no_ats()
5397 if (pdev->revision < 0x20) in quirk_intel_e2000_no_ats()
5415 pdev->no_msi = 1; in quirk_fsl_no_msi()
5420 * Although not allowed by the spec, some multi-function devices have
5433 if (PCI_FUNC(pdev->devfn) != consumer) in pci_create_device_link()
5436 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), in pci_create_device_link()
5437 pdev->bus->number, in pci_create_device_link()
5438 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); in pci_create_device_link()
5439 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { in pci_create_device_link()
5444 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5452 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
5485 * Create device link for GPUs with integrated Type-C UCSI controller
5512 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) in quirk_nvidia_hda()
5523 /* The GPU becomes a multi-function device when the HDA is enabled */ in quirk_nvidia_hda()
5525 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5536 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5538 * Item #36 - Downstream port applies ACS Source Validation to Completions
5551 * write, so we do config reads until we receive a non-Config Request Retry
5562 struct pci_dev *bridge = bus->self; in pci_idt_bus_quirk()
5564 pos = bridge->acs_cap; in pci_idt_bus_quirk()
5576 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ in pci_idt_bus_quirk()
5580 /* Re-enable ACS_SV if it was previously enabled */ in pci_idt_bus_quirk()
5620 partition = ioread8(&mmio_ntb->partition_id); in quirk_switchtec_ntb_dma_alias()
5622 partition_map = ioread32(&mmio_ntb->ep_map); in quirk_switchtec_ntb_dma_alias()
5623 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; in quirk_switchtec_ntb_dma_alias()
5638 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); in quirk_switchtec_ntb_dma_alias()
5655 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); in quirk_switchtec_ntb_dma_alias()
5756 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5757 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5758 !pdev->reset_fn) in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5800 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
5812 * 7.3.27, 7.3.29-7.3.31.
5818 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
5821 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
5828 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; in apex_pci_fixup_class()
5835 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; in nvidia_ion_ahci_fixup()