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Searched +full:sgmii +full:- +full:enable +full:- +full:pll (Results 1 – 25 of 43) sorted by relevance

12

/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm958625-meraki-alamo.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm958625-meraki-mx6x-common.dtsi"
12 compatible = "gpio-keys-polled";
14 poll-interval = <20>;
16 button-reset {
24 compatible = "gpio-leds";
26 led-0 {
27 /* green:wan1-left */
29 function-enumerator = <0>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/dsa/
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
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/kernel/linux/linux-6.6/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
11 * This driver is tested for USB, SGMII, SATA and Display Port currently.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
57 /* PLL Test Mode register parameters */
61 /* PLL SSC step size offsets */
160 #define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */
161 #define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */
[all …]
/kernel/linux/linux-5.10/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
12 * Other controllers PCIe and SGMII should also work but that is
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
57 /* PLL Test Mode register parameters */
61 /* PLL SSC step size offsets */
160 #define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */
161 #define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */
[all …]
/kernel/linux/linux-6.6/drivers/phy/freescale/
Dphy-fsl-lynx-28g.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
26 /* Per PLL registers */
27 #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0) argument
31 #define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4) argument
39 #define LYNX_28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8) argument
134 struct lynx_28g_pll pll[LYNX_28G_NUM_PLL]; member
143 void __iomem *reg = priv->base + off; in lynx_28g_rmw()
153 lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dat803x.c1 // SPDX-License-Identifier: GPL-2.0+
22 #include <dt-bindings/net/qca-ar803x.h>
86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
99 /* AT803x supports either the XTAL input pad, an internal PLL or the
101 * is only used for 25 MHz output, all other frequencies need the PLL.
105 * By default the PLL is only enabled if there is a link. Otherwise
106 * the PHY will go into low power state and disabled the PLL. You can
107 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
122 * but doesn't support choosing between XTAL/PLL and DSP.
148 #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */
[all …]
Dbcm54140.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
13 #include "bcm-phy-lib.h"
15 /* RDB per-port registers
35 #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */
37 #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */
45 #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */
60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
80 * T = 413.35 - (0.49055 * bits[9:0])
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/
Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
73 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect()
77 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect()
82 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect()
87 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect()
92 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect()
96 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect()
105 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect()
109 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_write_mmd_indirect()
114 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_write_mmd_indirect()
[all …]
Dmt7530.h1 /* SPDX-License-Identifier: GPL-2.0-only */
227 /* Register for port port-and-protocol based vlan 1 control */
310 /* MT7531 SGMII register group */
313 ((p) - 5) * 0x1000 + (r))
321 /* Register for SGMII PCS_SPPED_ABILITY */
346 /* Values of SGMII SPEED */
479 /* Registers for RGMII and SGMII PLL clock */
540 /* Registers for core PLL access through mmd indirect */
617 /* struct mt7530_port - This is the main data structure for holding the state
619 * @enable: The status used for show port is enabled or not.
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Dbcm54140.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
13 #include "bcm-phy-lib.h"
15 /* RDB per-port registers
35 #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */
37 #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */
45 #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */
60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
80 * T = 413.35 - (0.49055 * bits[9:0])
[all …]
Dat803x.c1 // SPDX-License-Identifier: GPL-2.0+
23 #include <dt-bindings/net/qca-ar803x.h>
103 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
130 /* AT803x supports either the XTAL input pad, an internal PLL or the
132 * is only used for 25 MHz output, all other frequencies need the PLL.
136 * By default the PLL is only enabled if there is a link. Otherwise
137 * the PHY will go into low power state and disabled the PLL. You can
138 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
153 * but doesn't support choosing between XTAL/PLL and DSP.
191 /* don't turn off internal PLL */
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/qca/
Dqca8k-8xxx.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
47 ret = bus->write(bus, phy_id, regnum, lo); in qca8k_mii_write_lo()
49 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_lo()
62 ret = bus->write(bus, phy_id, regnum, hi); in qca8k_mii_write_hi()
64 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_hi()
75 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_lo()
83 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_lo()
95 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_hi()
103 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_hi()
[all …]
/kernel/linux/linux-6.6/drivers/phy/marvell/
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
189 * (used only by SGMII code)
210 * (used only by SGMII code)
301 /*-----------------------------------------------------------*/
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
400 if (lane->id == 2) { in comphy_lane_reg_set()
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/
Dmt7530.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
271 /* Register for port port-and-protocol based vlan 1 control */
374 /* MT7531 SGMII register group */
375 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
511 /* Registers for RGMII and SGMII PLL clock */
573 /* LED enable, 0: Disable, 1: Enable (Default) */
579 /* GPIO output enable, 0: Disable, 1: Enable */
592 /* Registers for core PLL access through mmd indirect */
669 /* struct mt7530_port - This is the main data structure for holding the state
[all …]
Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
85 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect()
89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect()
94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect()
99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect()
104 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect()
108 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect()
117 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect()
121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_write_mmd_indirect()
126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_write_mmd_indirect()
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/mscc/
Dmscc_serdes.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
25 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_detune()
39 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_tune()
56 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_pll_cfg_wr()
72 /* qrate = 1 for SGMII, 0 for QSGMII */ in vsc85xx_sd6g_common_cfg_wr()
73 /* if_mode = 1 for SGMII, 3 for QSGMII */ in vsc85xx_sd6g_common_cfg_wr()
85 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_common_cfg_wr()
109 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_des_cfg_wr()
134 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg0_wr()
158 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg1_wr()
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/sja1105/
Dsja1105_clocking.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright (c) 2016-2018, NXP Semiconductors
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
99 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
100 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
101 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
102 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
108 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
109 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
115 return -ERANGE; in sja1105_cgu_idiv_config()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/igb/
De1000_82575.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igb/
De1000_82575.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-intel.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
44 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
49 return -ENODEV; in stmmac_pci_find_phy_addr()
51 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
52 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
55 if (func_data->func == func) in stmmac_pci_find_phy_addr()
56 return func_data->phy_addr; in stmmac_pci_find_phy_addr()
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/sja1105/
Dsja1105_clocking.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
[all …]
/kernel/linux/linux-6.6/drivers/phy/mediatek/
Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
216 /* CDR Charge Pump P-path current adjustment */
235 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
244 /* I-path capacitance adjustment for Gen1 */
258 /* PHY switch between pcie/usb3/sgmii/sata */
[all …]
/kernel/linux/linux-5.10/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
365 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
367 writew(val, ctx->base + offset); in cdns_regmap_write()
375 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
377 *val = readw(ctx->base + offset); in cdns_regmap_read()
387 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()
398 *val = readl(ctx->base + offset); in cdns_regmap_dptx_read()
497 * Structure used to store values of PHY registers for voltage-related
498 * coefficients, for particular voltage swing and pre-emphasis level. Values
[all …]
/kernel/linux/linux-6.6/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
464 for (i = 0; i < tbl->num_entries; i++) { in cdns_torrent_get_tbl_vals()
465 if (tbl->entries[i].key == key) in cdns_torrent_get_tbl_vals()
466 return tbl->entries[i].vals; in cdns_torrent_get_tbl_vals()
[all …]
/kernel/linux/linux-5.10/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
14 * operate according to the mode of operation. The first PLL CMU is only
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
[all …]

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