1 /*
2 * Copyright (c) 2023 Huawei Device Co., Ltd.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #if TARGAARCH64
17 #include "aarch64_global.h"
18 #endif
19 #if TARGRISCV64
20 #include "riscv64_global.h"
21 #endif
22 #if TARGARM32
23 #include "arm32_global.h"
24 #endif
25 #include "reaching.h"
26 #include "cgfunc.h"
27 #include "live.h"
28 /*
29 * This phase do some optimization using use-def chain and def-use chain.
30 * each function in Run() is a optimization. mainly include 2 parts:
31 * 1. find the number of valid bits for register by finding the definition insn of register,
32 * and then using the valid bits to delete redundant insns.
33 * 2. copy Propagate:
34 * a. forward copy propagate
35 * this optimization aim to optimize following:
36 * mov x100, x200;
37 * BBs:
38 * ...
39 * mOp ..., x100 /// multiple site that use x100
40 * =>
41 * mov x200, x200
42 * BBs:
43 * ...
44 * mOp ..., x200 // multiple site that use x100
45 * b. backward copy propagate
46 * this optimization aim to optimize following:
47 * mOp x200, ... // Define insn of x200
48 * ...
49 * mOp ..., x200 // use site of x200
50 * mov x100, x200;
51 * =>
52 * mOp x100, ... // Define insn of x200
53 * ...
54 * mOp ..., x100 // use site of x200
55 * mov x100, x100;
56 *
57 * NOTE: after insn is modified, UD-chain and DU-chain should be maintained by self. currently several common
58 * interface has been implemented in RD, but they must be used reasonably. specific instructions for use
59 * can be found at the begining of corresponding function.
60 */
61 namespace maplebe {
62 using namespace maple;
63
PhaseRun(maplebe::CGFunc & f)64 bool CgGlobalOpt::PhaseRun(maplebe::CGFunc &f)
65 {
66 ReachingDefinition *reachingDef = nullptr;
67 LiveAnalysis *live = nullptr;
68 if (Globals::GetInstance()->GetOptimLevel() >= CGOptions::kLevel2) {
69 reachingDef = GET_ANALYSIS(CgReachingDefinition, f);
70 live = GET_ANALYSIS(CgLiveAnalysis, f);
71 }
72 if (reachingDef == nullptr || !f.GetRDStatus()) {
73 GetAnalysisInfoHook()->ForceEraseAnalysisPhase(f.GetUniqueID(), &CgReachingDefinition::id);
74 return false;
75 }
76 reachingDef->SetAnalysisMode(kRDAllAnalysis);
77 auto *loopInfo = GET_ANALYSIS(CgLoopAnalysis, f);
78 GlobalOpt *globalOpt = nullptr;
79 #if TARGAARCH64 || TARGRISCV64
80 globalOpt = GetPhaseAllocator()->New<AArch64GlobalOpt>(f, *loopInfo);
81 #endif
82 #if TARGARM32
83 globalOpt = GetPhaseAllocator()->New<Arm32GlobalOpt>(f, *loopInfo);
84 #endif
85 globalOpt->Run();
86 if (live != nullptr) {
87 live->ClearInOutDataInfo();
88 }
89 return true;
90 }
91
GetAnalysisDependence(maple::AnalysisDep & aDep) const92 void CgGlobalOpt::GetAnalysisDependence(maple::AnalysisDep &aDep) const
93 {
94 aDep.AddRequired<CgReachingDefinition>();
95 aDep.AddRequired<CgLiveAnalysis>();
96 aDep.AddRequired<CgLoopAnalysis>();
97 aDep.PreservedAllExcept<CgLiveAnalysis>();
98 }
99 MAPLE_TRANSFORM_PHASE_REGISTER_CANSKIP(CgGlobalOpt, globalopt)
100
101 } /* namespace maplebe */
102