1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang<zhangqing@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/io.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/syscore_ops.h>
14 #include <dt-bindings/clock/px30-cru.h>
15 #include "clk.h"
16
17 #define PX30_GRF_SOC_STATUS0 0x480
18 #define PX30_FRAC_MAX_PRATE 600000000
19
20 enum px30_plls {
21 apll,
22 dpll,
23 cpll,
24 npll,
25 apll_b_h,
26 apll_b_l,
27 };
28
29 enum px30_pmu_plls {
30 gpll,
31 };
32
33 static struct rockchip_pll_rate_table px30_pll_rates[] = {
34 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
35 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
46 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
47 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
48 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
49 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
50 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
51 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
52 RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0), RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
53 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
54 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
55 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
56 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), { },
57 };
58
59 #define PX30_DIV_ACLKM_MASK 0x7
60 #define PX30_DIV_ACLKM_SHIFT 12
61 #define PX30_DIV_PCLK_DBG_MASK 0xf
62 #define PX30_DIV_PCLK_DBG_SHIFT 8
63
64 #define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \
65 { \
66 .reg = PX30_CLKSEL_CON(0), \
67 .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, PX30_DIV_ACLKM_SHIFT) | \
68 HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, PX30_DIV_PCLK_DBG_SHIFT), \
69 }
70
71 #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
72 { \
73 .prate = (_prate), \
74 .divs = { \
75 PX30_CLKSEL0(_aclk_core, _pclk_dbg), \
76 }, \
77 }
78
79 static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
80 PX30_CPUCLK_RATE(1608000000, 1, 7), PX30_CPUCLK_RATE(1584000000, 1, 7), PX30_CPUCLK_RATE(1560000000, 1, 7),
81 PX30_CPUCLK_RATE(1536000000, 1, 7), PX30_CPUCLK_RATE(1512000000, 1, 7), PX30_CPUCLK_RATE(1488000000, 1, 5),
82 PX30_CPUCLK_RATE(1464000000, 1, 5), PX30_CPUCLK_RATE(1440000000, 1, 5), PX30_CPUCLK_RATE(1416000000, 1, 5),
83 PX30_CPUCLK_RATE(1392000000, 1, 5), PX30_CPUCLK_RATE(1368000000, 1, 5), PX30_CPUCLK_RATE(1344000000, 1, 5),
84 PX30_CPUCLK_RATE(1320000000, 1, 5), PX30_CPUCLK_RATE(1296000000, 1, 5), PX30_CPUCLK_RATE(1272000000, 1, 5),
85 PX30_CPUCLK_RATE(1248000000, 1, 5), PX30_CPUCLK_RATE(1224000000, 1, 5), PX30_CPUCLK_RATE(1200000000, 1, 5),
86 PX30_CPUCLK_RATE(1104000000, 1, 5), PX30_CPUCLK_RATE(1008000000, 1, 5), PX30_CPUCLK_RATE(912000000, 1, 5),
87 PX30_CPUCLK_RATE(816000000, 1, 3), PX30_CPUCLK_RATE(696000000, 1, 3), PX30_CPUCLK_RATE(600000000, 1, 3),
88 PX30_CPUCLK_RATE(408000000, 1, 1), PX30_CPUCLK_RATE(312000000, 1, 1), PX30_CPUCLK_RATE(216000000, 1, 1),
89 PX30_CPUCLK_RATE(96000000, 1, 1),
90 };
91
92 static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
93 .core_reg[0] = PX30_CLKSEL_CON(0),
94 .div_core_shift[0] = 0,
95 .div_core_mask[0] = 0xf,
96 .num_cores = 1,
97 .mux_core_alt = 1,
98 .mux_core_main = 0,
99 .mux_core_shift = 7,
100 .mux_core_mask = 0x1,
101 .pll_name = "pll_apll",
102 };
103
104 PNAME(mux_pll_p) = {"xin24m"};
105 PNAME(mux_usb480m_p) = {"xin24m", "usb480m_phy", "clk_rtc32k_pmu"};
106 PNAME(mux_ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
107 PNAME(mux_ddrstdby_p) = {"clk_ddrphy1x", "clk_stdby_2wrap"};
108 PNAME(mux_gpll_dmycpll_usb480m_npll_p) = {"gpll", "dummy_cpll", "usb480m", "npll"};
109 PNAME(mux_gpll_dmycpll_usb480m_dmynpll_p) = {"gpll", "dummy_cpll", "usb480m", "dummy_npll"};
110 PNAME(mux_cpll_npll_p) = {"cpll", "npll"};
111 PNAME(mux_npll_cpll_p) = {"npll", "cpll"};
112 PNAME(mux_gpll_cpll_p) = {"gpll", "dummy_cpll"};
113 PNAME(mux_gpll_npll_p) = {"gpll", "dummy_npll"};
114 PNAME(mux_gpll_xin24m_p) = {"gpll", "xin24m"};
115 PNAME(mux_gpll_cpll_npll_p) = {"gpll", "dummy_cpll", "dummy_npll"};
116 PNAME(mux_gpll_cpll_npll_xin24m_p) = {"gpll", "dummy_cpll", "dummy_npll", "xin24m"};
117 PNAME(mux_gpll_xin24m_npll_p) = {"gpll", "xin24m", "dummy_npll"};
118 PNAME(mux_pdm_p) = {"clk_pdm_src", "clk_pdm_frac"};
119 PNAME(mux_i2s0_tx_p) = {"clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
120 PNAME(mux_i2s0_rx_p) = {"clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"};
121 PNAME(mux_i2s1_p) = {"clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"};
122 PNAME(mux_i2s2_p) = {"clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"};
123 PNAME(mux_i2s0_tx_out_p) = {"clk_i2s0_tx", "xin12m", "clk_i2s0_rx"};
124 PNAME(mux_i2s0_rx_out_p) = {"clk_i2s0_rx", "xin12m", "clk_i2s0_tx"};
125 PNAME(mux_i2s1_out_p) = {"clk_i2s1", "xin12m"};
126 PNAME(mux_i2s2_out_p) = {"clk_i2s2", "xin12m"};
127 PNAME(mux_i2s0_tx_rx_p) = {"clk_i2s0_tx_mux", "clk_i2s0_rx_mux"};
128 PNAME(mux_i2s0_rx_tx_p) = {"clk_i2s0_rx_mux", "clk_i2s0_tx_mux"};
129 PNAME(mux_uart_src_p) = {"gpll", "xin24m", "usb480m", "dummy_npll"};
130 PNAME(mux_uart1_p) = {"clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac"};
131 PNAME(mux_uart2_p) = {"clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac"};
132 PNAME(mux_uart3_p) = {"clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac"};
133 PNAME(mux_uart4_p) = {"clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac"};
134 PNAME(mux_uart5_p) = {"clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac"};
135 PNAME(mux_cif_out_p) = {"xin24m", "dummy_cpll", "dummy_npll", "usb480m"};
136 PNAME(mux_dclk_vopb_p) = {"dclk_vopb_src", "dclk_vopb_frac", "xin24m"};
137 PNAME(mux_dclk_vopl_p) = {"dclk_vopl_src", "dclk_vopl_frac", "xin24m"};
138 PNAME(mux_nandc_p) = {"clk_nandc_div", "clk_nandc_div50"};
139 PNAME(mux_sdio_p) = {"clk_sdio_div", "clk_sdio_div50"};
140 PNAME(mux_emmc_p) = {"clk_emmc_div", "clk_emmc_div50"};
141 PNAME(mux_sdmmc_p) = {"clk_sdmmc_div", "clk_sdmmc_div50"};
142 PNAME(mux_gmac_p) = {"clk_gmac_src", "gmac_clkin"};
143 PNAME(mux_gmac_rmii_sel_p) = {"clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2"};
144 PNAME(mux_rtc32k_pmu_p) = {
145 "xin32k",
146 "pmu_pvtm_32k",
147 "clk_rtc32k_frac",
148 };
149 PNAME(mux_wifi_pmu_p) = {"xin24m", "clk_wifi_pmu_src"};
150 PNAME(mux_uart0_pmu_p) = {"clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac"};
151 PNAME(mux_usbphy_ref_p) = {"xin24m", "clk_ref24m_pmu"};
152 PNAME(mux_mipidsiphy_ref_p) = {"xin24m", "clk_ref24m_pmu"};
153 PNAME(mux_gpu_p) = {"clk_gpu_div", "clk_gpu_np5"};
154
155 static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
156 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, PX30_PLL_CON(0), PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
157 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, PX30_PLL_CON(8), PX30_MODE_CON, 4, 1, 0, NULL),
158 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, PX30_PLL_CON(16), PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
159 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, CLK_IS_CRITICAL, PX30_PLL_CON(24), PX30_MODE_CON, 6, 4, 0,
160 px30_pll_rates),
161 };
162
163 static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = {
164 [gpll] =
165 PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0), PX30_PMU_MODE, 0, 3, 0, px30_pll_rates),
166 };
167
168 #define MFLAGS CLK_MUX_HIWORD_MASK
169 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
170 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
171
172 static struct rockchip_clk_branch px30_pdm_fracmux __initdata =
173 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
174
175 static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata =
176 MUX(SCLK_I2S0_TX_MUX, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
177
178 static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata =
179 MUX(SCLK_I2S0_RX_MUX, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
180
181 static struct rockchip_clk_branch px30_i2s1_fracmux __initdata =
182 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(30), 10, 2, MFLAGS);
183
184 static struct rockchip_clk_branch px30_i2s2_fracmux __initdata =
185 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(32), 10, 2, MFLAGS);
186
187 static struct rockchip_clk_branch px30_uart1_fracmux __initdata =
188 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
189
190 static struct rockchip_clk_branch px30_uart2_fracmux __initdata =
191 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
192
193 static struct rockchip_clk_branch px30_uart3_fracmux __initdata =
194 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
195
196 static struct rockchip_clk_branch px30_uart4_fracmux __initdata =
197 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(44), 14, 2, MFLAGS);
198
199 static struct rockchip_clk_branch px30_uart5_fracmux __initdata =
200 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(47), 14, 2, MFLAGS);
201
202 static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata =
203 MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(5), 14, 2, MFLAGS);
204
205 static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata =
206 MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(8), 14, 2, MFLAGS);
207
208 static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata = MUX(
209 SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT, PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
210
211 static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata =
212 MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT, PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
213
214 static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
215 /*
216 * Clock-Architecture Diagram 1
217 */
218
219 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, PX30_MODE_CON, 8, 2, MFLAGS),
220 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
221
222 /*
223 * Clock-Architecture Diagram 3
224 */
225
226 /* PD_CORE */
227 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 0, GFLAGS),
228 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 0, GFLAGS),
229 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(0), 8, 4,
230 DFLAGS | CLK_DIVIDER_READ_ONLY, PX30_CLKGATE_CON(0), 2, GFLAGS),
231 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(0), 12, 3,
232 DFLAGS | CLK_DIVIDER_READ_ONLY, PX30_CLKGATE_CON(0), 1, GFLAGS),
233 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 4, GFLAGS),
234 GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(17), 5, GFLAGS),
235 GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 5, GFLAGS),
236 GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 6, GFLAGS),
237 GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(17), 6, GFLAGS),
238
239 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 3, GFLAGS),
240 GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0, PX30_CLKGATE_CON(17), 4, GFLAGS),
241
242 /* PD_GPU */
243 GATE(SCLK_GPU, "clk_gpu", "clk_gpu_src", 0, PX30_CLKGATE_CON(0), 10, GFLAGS),
244 COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
245 PX30_CLKGATE_CON(17), 10, GFLAGS),
246 GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IS_CRITICAL, PX30_CLKGATE_CON(0), 11, GFLAGS),
247 GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(17), 8, GFLAGS),
248 GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(17), 9, GFLAGS),
249
250 /*
251 * Clock-Architecture Diagram 4
252 */
253
254 /* PD_DDR */
255 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 7, GFLAGS),
256 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 13, GFLAGS),
257 COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3,
258 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
259 COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3,
260 DFLAGS),
261 FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, PX30_CLKGATE_CON(0), 14, GFLAGS),
262 FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, PX30_CLKGATE_CON(1), 0, GFLAGS),
263 COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 4, 1, MFLAGS,
264 PX30_CLKGATE_CON(1), 13, GFLAGS),
265 GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 15, GFLAGS),
266 GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 8, GFLAGS),
267 GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 5, GFLAGS),
268 GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 6, GFLAGS),
269 GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 6, GFLAGS),
270 GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 11, GFLAGS),
271
272 GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 15, GFLAGS),
273
274 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 8, 5, DFLAGS,
275 PX30_CLKGATE_CON(1), 1, GFLAGS),
276 GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 10, GFLAGS),
277 GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 7, GFLAGS),
278 GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 9, GFLAGS),
279 GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 12, GFLAGS),
280 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 14, GFLAGS),
281 GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(1), 3, GFLAGS),
282
283 /*
284 * Clock-Architecture Diagram 5
285 */
286
287 /* PD_VI */
288 COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
289 PX30_CLKGATE_CON(4), 8, GFLAGS),
290 COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0, PX30_CLKSEL_CON(11), 8, 4, DFLAGS,
291 PX30_CLKGATE_CON(4), 12, GFLAGS),
292 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
293 PX30_CLKGATE_CON(4), 9, GFLAGS),
294 COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0, PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS,
295 PX30_CLKGATE_CON(4), 11, GFLAGS),
296 GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0, PX30_CLKGATE_CON(4), 13, GFLAGS),
297 GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0, PX30_CLKGATE_CON(4), 14, GFLAGS),
298
299 /*
300 * Clock-Architecture Diagram 6
301 */
302
303 /* PD_VO */
304 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS,
305 PX30_CLKGATE_CON(2), 0, GFLAGS),
306 COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0, PX30_CLKSEL_CON(3), 8, 4, DFLAGS, PX30_CLKGATE_CON(2),
307 12, GFLAGS),
308 COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0, PX30_CLKSEL_CON(3), 12, 4, DFLAGS,
309 PX30_CLKGATE_CON(2), 13, GFLAGS),
310 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
311 PX30_CLKGATE_CON(2), 1, GFLAGS),
312
313 COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS,
314 PX30_CLKGATE_CON(2), 5, GFLAGS),
315 COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PX30_CLKSEL_CON(5),
316 11, 1, MFLAGS, 0, 8, DFLAGS, PX30_CLKGATE_CON(2), 2, GFLAGS),
317 COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(6), 0,
318 PX30_CLKGATE_CON(2), 3, GFLAGS, &px30_dclk_vopb_fracmux, 0),
319 GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(2), 4, GFLAGS),
320 COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PX30_CLKSEL_CON(8),
321 11, 1, MFLAGS, 0, 8, DFLAGS, PX30_CLKGATE_CON(2), 6, GFLAGS),
322 COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(9), 0,
323 PX30_CLKGATE_CON(2), 7, GFLAGS, &px30_dclk_vopl_fracmux, 0),
324 GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(2), 8, GFLAGS),
325
326 /* PD_VPU */
327 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
328 PX30_CLKGATE_CON(4), 0, GFLAGS),
329 COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, PX30_CLKSEL_CON(10), 8, 4, DFLAGS, PX30_CLKGATE_CON(4), 2,
330 GFLAGS),
331 COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS,
332 PX30_CLKGATE_CON(4), 1, GFLAGS),
333
334 /*
335 * Clock-Architecture Diagram 7
336 */
337
338 COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, PX30_CLKSEL_CON(14), 15, 1,
339 MFLAGS, PX30_CLKGATE_CON(5), 7, GFLAGS),
340 COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IS_CRITICAL, PX30_CLKSEL_CON(14), 0, 5, DFLAGS,
341 PX30_CLKGATE_CON(5), 8, GFLAGS),
342 DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IS_CRITICAL, PX30_CLKSEL_CON(14), 8, 5, DFLAGS),
343
344 /* PD_MMC_NAND */
345 GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0, PX30_CLKGATE_CON(6), 0, GFLAGS),
346 COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
347 PX30_CLKGATE_CON(5), 11, GFLAGS),
348 COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 8, 5,
349 DFLAGS, PX30_CLKGATE_CON(5), 12, GFLAGS),
350 COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
351 PX30_CLKSEL_CON(15), 15, 1, MFLAGS, PX30_CLKGATE_CON(5), 13, GFLAGS),
352
353 COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0, PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8,
354 DFLAGS, PX30_CLKGATE_CON(6), 1, GFLAGS),
355 COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50", mux_gpll_cpll_npll_xin24m_p, 0, PX30_CLKSEL_CON(18), 14, 2,
356 MFLAGS, PX30_CLKSEL_CON(19), 0, 8, DFLAGS, PX30_CLKGATE_CON(6), 2, GFLAGS),
357 COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
358 PX30_CLKSEL_CON(19), 15, 1, MFLAGS, PX30_CLKGATE_CON(6), 3, GFLAGS),
359
360 COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0, PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8,
361 DFLAGS, PX30_CLKGATE_CON(6), 4, GFLAGS),
362 COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0, PX30_CLKSEL_CON(20), 14, 2,
363 MFLAGS, PX30_CLKSEL_CON(21), 0, 8, DFLAGS, PX30_CLKGATE_CON(6), 5, GFLAGS),
364 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
365 PX30_CLKSEL_CON(21), 15, 1, MFLAGS, PX30_CLKGATE_CON(6), 6, GFLAGS),
366
367 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0, PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS,
368 PX30_CLKGATE_CON(6), 7, GFLAGS),
369
370 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", PX30_SDMMC_CON0, 1),
371 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", PX30_SDMMC_CON1, 1),
372
373 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", PX30_SDIO_CON0, 1),
374 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", PX30_SDIO_CON1, 1),
375
376 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", PX30_EMMC_CON0, 1),
377 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", PX30_EMMC_CON1, 1),
378
379 /* PD_SDCARD */
380 GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0, PX30_CLKGATE_CON(6), 12, GFLAGS),
381 COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0, PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8,
382 DFLAGS, PX30_CLKGATE_CON(6), 13, GFLAGS),
383 COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_gpll_cpll_npll_xin24m_p, 0, PX30_CLKSEL_CON(16), 14,
384 2, MFLAGS, PX30_CLKSEL_CON(17), 0, 8, DFLAGS, PX30_CLKGATE_CON(6), 14, GFLAGS),
385 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
386 PX30_CLKSEL_CON(17), 15, 1, MFLAGS, PX30_CLKGATE_CON(6), 15, GFLAGS),
387
388 /* PD_USB */
389 GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(7), 2, GFLAGS),
390 GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0, PX30_CLKGATE_CON(7), 3, GFLAGS),
391
392 /* PD_GMAC */
393 COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS,
394 PX30_CLKGATE_CON(7), 11, GFLAGS),
395 MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(23), 6, 1, MFLAGS),
396 GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0, PX30_CLKGATE_CON(7), 15, GFLAGS),
397 GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0, PX30_CLKGATE_CON(7), 13, GFLAGS),
398 FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2),
399 FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20),
400 MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(23), 7, 1,
401 MFLAGS),
402
403 GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0, PX30_CLKGATE_CON(7), 10, GFLAGS),
404 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, PX30_CLKSEL_CON(23), 0, 4, DFLAGS, PX30_CLKGATE_CON(7), 12,
405 GFLAGS),
406
407 COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
408 PX30_CLKGATE_CON(8), 5, GFLAGS),
409
410 /*
411 * Clock-Architecture Diagram 8
412 */
413
414 /* PD_BUS */
415 COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, PX30_CLKSEL_CON(23), 15, 1, MFLAGS,
416 PX30_CLKGATE_CON(8), 6, GFLAGS),
417 COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IS_CRITICAL, PX30_CLKSEL_CON(24), 0, 5, DFLAGS,
418 PX30_CLKGATE_CON(8), 8, GFLAGS),
419 COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IS_CRITICAL, PX30_CLKSEL_CON(23), 8, 5, DFLAGS,
420 PX30_CLKGATE_CON(8), 7, GFLAGS),
421 COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL, PX30_CLKSEL_CON(24), 8, 2, DFLAGS,
422 PX30_CLKGATE_CON(8), 9, GFLAGS),
423 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(8), 10, GFLAGS),
424
425 COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0, PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS,
426 PX30_CLKGATE_CON(9), 9, GFLAGS),
427 COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(27), 0,
428 PX30_CLKGATE_CON(9), 10, GFLAGS, &px30_pdm_fracmux, PX30_FRAC_MAX_PRATE),
429 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(9), 11, GFLAGS),
430
431 COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0, PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS,
432 PX30_CLKGATE_CON(9), 12, GFLAGS),
433 COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(29), 0,
434 PX30_CLKGATE_CON(9), 13, GFLAGS, &px30_i2s0_tx_fracmux, PX30_FRAC_MAX_PRATE),
435 COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(28), 12, 1,
436 MFLAGS, PX30_CLKGATE_CON(9), 14, GFLAGS),
437 COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(28), 14, 2,
438 MFLAGS, PX30_CLKGATE_CON(9), 15, GFLAGS),
439 GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 8,
440 CLK_GATE_HIWORD_MASK),
441
442 COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0, PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS,
443 PX30_CLKGATE_CON(17), 0, GFLAGS),
444 COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(59), 0,
445 PX30_CLKGATE_CON(17), 1, GFLAGS, &px30_i2s0_rx_fracmux, PX30_FRAC_MAX_PRATE),
446 COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(58), 12, 1,
447 MFLAGS, PX30_CLKGATE_CON(17), 2, GFLAGS),
448 COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0, PX30_CLKSEL_CON(58), 14, 2, MFLAGS,
449 PX30_CLKGATE_CON(17), 3, GFLAGS),
450 GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 11,
451 CLK_GATE_HIWORD_MASK),
452
453 COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0, PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS,
454 PX30_CLKGATE_CON(10), 0, GFLAGS),
455 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(31), 0,
456 PX30_CLKGATE_CON(10), 1, GFLAGS, &px30_i2s1_fracmux, PX30_FRAC_MAX_PRATE),
457 GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 2, GFLAGS),
458 COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(30), 15, 1, MFLAGS,
459 PX30_CLKGATE_CON(10), 3, GFLAGS),
460 GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 9,
461 CLK_GATE_HIWORD_MASK),
462
463 COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0, PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS,
464 PX30_CLKGATE_CON(10), 4, GFLAGS),
465 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(33), 0,
466 PX30_CLKGATE_CON(10), 5, GFLAGS, &px30_i2s2_fracmux, PX30_FRAC_MAX_PRATE),
467 GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 6, GFLAGS),
468 COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0, PX30_CLKSEL_CON(32), 15, 1, MFLAGS, PX30_CLKGATE_CON(10),
469 7, GFLAGS),
470 GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 10,
471 CLK_GATE_HIWORD_MASK),
472
473 COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT, PX30_CLKSEL_CON(34), 14, 2,
474 MFLAGS, 0, 5, DFLAGS, PX30_CLKGATE_CON(10), 12, GFLAGS),
475 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0, PX30_CLKSEL_CON(35), 0, 5, DFLAGS,
476 PX30_CLKGATE_CON(10), 13, GFLAGS),
477 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(36), 0,
478 PX30_CLKGATE_CON(10), 14, GFLAGS, &px30_uart1_fracmux, PX30_FRAC_MAX_PRATE),
479 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 15, GFLAGS),
480
481 COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0, PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS,
482 PX30_CLKGATE_CON(11), 0, GFLAGS),
483 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0, PX30_CLKSEL_CON(38), 0, 5, DFLAGS,
484 PX30_CLKGATE_CON(11), 1, GFLAGS),
485 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(39), 0,
486 PX30_CLKGATE_CON(11), 2, GFLAGS, &px30_uart2_fracmux, PX30_FRAC_MAX_PRATE),
487 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, PX30_CLKGATE_CON(11), 3,
488 GFLAGS),
489
490 COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0, PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS,
491 PX30_CLKGATE_CON(11), 4, GFLAGS),
492 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0, PX30_CLKSEL_CON(41), 0, 5, DFLAGS,
493 PX30_CLKGATE_CON(11), 5, GFLAGS),
494 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(42), 0,
495 PX30_CLKGATE_CON(11), 6, GFLAGS, &px30_uart3_fracmux, PX30_FRAC_MAX_PRATE),
496 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(11), 7, GFLAGS),
497
498 COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0, PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS,
499 PX30_CLKGATE_CON(11), 8, GFLAGS),
500 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0, PX30_CLKSEL_CON(44), 0, 5, DFLAGS,
501 PX30_CLKGATE_CON(11), 9, GFLAGS),
502 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(45), 0,
503 PX30_CLKGATE_CON(11), 10, GFLAGS, &px30_uart4_fracmux, PX30_FRAC_MAX_PRATE),
504 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(11), 11, GFLAGS),
505
506 COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0, PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS,
507 PX30_CLKGATE_CON(11), 12, GFLAGS),
508 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0, PX30_CLKSEL_CON(47), 0, 5, DFLAGS,
509 PX30_CLKGATE_CON(11), 13, GFLAGS),
510 COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(48), 0,
511 PX30_CLKGATE_CON(11), 14, GFLAGS, &px30_uart5_fracmux, PX30_FRAC_MAX_PRATE),
512 GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(11), 15, GFLAGS),
513
514 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS,
515 PX30_CLKGATE_CON(12), 0, GFLAGS),
516 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS,
517 PX30_CLKGATE_CON(12), 1, GFLAGS),
518 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS,
519 PX30_CLKGATE_CON(12), 2, GFLAGS),
520 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS,
521 PX30_CLKGATE_CON(12), 3, GFLAGS),
522 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS,
523 PX30_CLKGATE_CON(12), 5, GFLAGS),
524 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS,
525 PX30_CLKGATE_CON(12), 6, GFLAGS),
526 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS,
527 PX30_CLKGATE_CON(12), 7, GFLAGS),
528 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS,
529 PX30_CLKGATE_CON(12), 8, GFLAGS),
530
531 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, PX30_CLKGATE_CON(13), 0, GFLAGS),
532 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, PX30_CLKGATE_CON(13), 1, GFLAGS),
533 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, PX30_CLKGATE_CON(13), 2, GFLAGS),
534 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, PX30_CLKGATE_CON(13), 3, GFLAGS),
535 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, PX30_CLKGATE_CON(13), 4, GFLAGS),
536 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, PX30_CLKGATE_CON(13), 5, GFLAGS),
537
538 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0, PX30_CLKSEL_CON(54), 0, 11, DFLAGS, PX30_CLKGATE_CON(12), 9,
539 GFLAGS),
540 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, PX30_CLKSEL_CON(55), 0, 11, DFLAGS, PX30_CLKGATE_CON(12),
541 10, GFLAGS),
542 COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0, PX30_CLKSEL_CON(56), 0, 3, DFLAGS, PX30_CLKGATE_CON(12), 11,
543 GFLAGS),
544 COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0, PX30_CLKSEL_CON(56), 4, 2, DFLAGS, PX30_CLKGATE_CON(13),
545 6, GFLAGS),
546
547 GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(12), 12, GFLAGS),
548
549 /* PD_CRYPTO */
550 GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0, PX30_CLKGATE_CON(8), 12, GFLAGS),
551 GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0, PX30_CLKGATE_CON(8), 13, GFLAGS),
552 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
553 PX30_CLKGATE_CON(8), 14, GFLAGS),
554 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5,
555 DFLAGS, PX30_CLKGATE_CON(8), 15, GFLAGS),
556
557 /*
558 * Clock-Architecture Diagram 9
559 */
560
561 /* PD_BUS_TOP */
562 GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS),
563 GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS),
564 GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS),
565 GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
566 GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
567 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),
568 GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(16), 6, GFLAGS),
569 GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
570
571 /* PD_VI */
572 GATE(0, "aclk_vi_niu", "aclk_vi_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(4), 15, GFLAGS),
573 GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS),
574 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS),
575 GATE(0, "hclk_vi_niu", "hclk_vi_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(5), 0, GFLAGS),
576 GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS),
577 GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS),
578
579 /* PD_VO */
580 GATE(0, "aclk_vo_niu", "aclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 0, GFLAGS),
581 GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS),
582 GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
583 GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS),
584
585 GATE(0, "hclk_vo_niu", "hclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 1, GFLAGS),
586 GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS),
587 GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
588 GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS),
589
590 GATE(0, "pclk_vo_niu", "pclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 2, GFLAGS),
591 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS),
592
593 /* PD_BUS */
594 GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS),
595 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS),
596 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
597 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
598
599 /* aclk_dmac is controlled by sgrf_soc_con1[11]. */
600 SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
601
602 GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
603 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
604 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
605 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS),
606 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS),
607 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS),
608
609 GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS),
610 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS),
611 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS),
612 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(14), 6, GFLAGS),
613 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
614 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS),
615 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
616 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS),
617 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS),
618 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS),
619 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS),
620 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS),
621 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS),
622 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS),
623 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS),
624 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS),
625 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS),
626 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS),
627 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS),
628 GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS),
629 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS),
630 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS),
631 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS),
632 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS),
633 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS),
634 GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS),
635
636 /* PD_VPU */
637 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS),
638 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS),
639 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS),
640 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS),
641
642 /* PD_CRYPTO */
643 GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS),
644 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS),
645 GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS),
646 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS),
647
648 /* PD_SDCARD */
649 GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS),
650 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS),
651
652 /* PD_PERI */
653 GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(5), 9, GFLAGS),
654
655 /* PD_MMC_NAND */
656 GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
657 GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS),
658 GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS),
659 GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS),
660 GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS),
661
662 /* PD_USB */
663 GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IS_CRITICAL, PX30_CLKGATE_CON(7), 4, GFLAGS),
664 GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS),
665 GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS),
666 GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS),
667
668 /* PD_GMAC */
669 GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(8), 0, GFLAGS),
670 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, PX30_CLKGATE_CON(8), 2, GFLAGS),
671 GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(8), 1, GFLAGS),
672 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, PX30_CLKGATE_CON(8), 3, GFLAGS),
673 };
674
675 static struct rockchip_clk_branch px30_gpu_src_clk[] __initdata = {
676 COMPOSITE(0, "clk_gpu_src", mux_gpll_dmycpll_usb480m_dmynpll_p, 0, PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS,
677 PX30_CLKGATE_CON(0), 8, GFLAGS),
678 };
679
680 static struct rockchip_clk_branch rk3326_gpu_src_clk[] __initdata = {
681 COMPOSITE(0, "clk_gpu_src", mux_gpll_dmycpll_usb480m_npll_p, 0, PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS,
682 PX30_CLKGATE_CON(0), 8, GFLAGS),
683 };
684
685 static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
686 /*
687 * Clock-Architecture Diagram 2
688 */
689
690 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, PX30_PMU_CLKSEL_CON(1), 0,
691 PX30_PMU_CLKGATE_CON(0), 13, GFLAGS, &px30_rtc32k_pmu_fracmux, 0),
692
693 COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED, PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
694 PX30_PMU_CLKGATE_CON(0), 12, GFLAGS),
695
696 COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0, PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS, PX30_PMU_CLKGATE_CON(0), 14,
697 GFLAGS),
698 COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, PX30_PMU_CLKSEL_CON(2), 15, 1,
699 MFLAGS, PX30_PMU_CLKGATE_CON(0), 15, GFLAGS),
700
701 COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0, PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS,
702 PX30_PMU_CLKGATE_CON(1), 0, GFLAGS),
703 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0, PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS,
704 PX30_PMU_CLKGATE_CON(1), 1, GFLAGS),
705 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT, PX30_PMU_CLKSEL_CON(5), 0,
706 PX30_PMU_CLKGATE_CON(1), 2, GFLAGS, &px30_uart0_pmu_fracmux, PX30_FRAC_MAX_PRATE),
707 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT, PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),
708
709 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, PX30_PMU_CLKGATE_CON(1), 4, GFLAGS),
710
711 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", CLK_IS_CRITICAL, PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
712 PX30_PMU_CLKGATE_CON(0), 0, GFLAGS),
713
714 COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0, PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
715 PX30_PMU_CLKGATE_CON(1), 8, GFLAGS),
716 COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT, PX30_PMU_CLKSEL_CON(2), 6,
717 1, MFLAGS, PX30_PMU_CLKGATE_CON(1), 9, GFLAGS),
718 COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
719 PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS, PX30_PMU_CLKGATE_CON(1), 10, GFLAGS),
720
721 /*
722 * Clock-Architecture Diagram 9
723 */
724
725 /* PD_PMU */
726 GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS),
727 GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS),
728 GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS),
729 GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS),
730 GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS),
731 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS),
732 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),
733 GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
734 };
735
736 static struct rockchip_clk_provider *cru_ctx;
px30_clk_init(struct device_node * np)737 static void __init px30_clk_init(struct device_node *np)
738 {
739 struct rockchip_clk_provider *ctx;
740 void __iomem *reg_base;
741
742 reg_base = of_iomap(np, 0);
743 if (!reg_base) {
744 pr_err("%s: could not map cru region\n", __func__);
745 return;
746 }
747
748 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
749 if (IS_ERR(ctx)) {
750 pr_err("%s: rockchip clk init failed\n", __func__);
751 iounmap(reg_base);
752 return;
753 }
754
755 rockchip_clk_register_plls(ctx, px30_pll_clks, ARRAY_SIZE(px30_pll_clks), PX30_GRF_SOC_STATUS0);
756 rockchip_clk_register_branches(ctx, px30_clk_branches, ARRAY_SIZE(px30_clk_branches));
757 if (of_machine_is_compatible("rockchip,px30")) {
758 rockchip_clk_register_branches(ctx, px30_gpu_src_clk, ARRAY_SIZE(px30_gpu_src_clk));
759 } else {
760 rockchip_clk_register_branches(ctx, rk3326_gpu_src_clk, ARRAY_SIZE(rk3326_gpu_src_clk));
761 }
762
763 rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK);
764
765 rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL);
766
767 rockchip_clk_of_add_provider(np, ctx);
768
769 cru_ctx = ctx;
770 }
771 CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
772
px30_pmu_clk_init(struct device_node * np)773 static void __init px30_pmu_clk_init(struct device_node *np)
774 {
775 struct rockchip_clk_provider *ctx;
776 void __iomem *reg_base;
777 struct clk **pmucru_clks, **cru_clks;
778
779 reg_base = of_iomap(np, 0);
780 if (!reg_base) {
781 pr_err("%s: could not map cru pmu region\n", __func__);
782 return;
783 }
784
785 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
786 if (IS_ERR(ctx)) {
787 pr_err("%s: rockchip pmu clk init failed\n", __func__);
788 return;
789 }
790 pmucru_clks = ctx->clk_data.clks;
791 cru_clks = cru_ctx->clk_data.clks;
792
793 rockchip_clk_register_plls(ctx, px30_pmu_pll_clks, ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0);
794
795 rockchip_clk_register_armclk(cru_ctx, ARMCLK, "armclk", 2, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL],
796 &px30_cpuclk_data, px30_cpuclk_rates, ARRAY_SIZE(px30_cpuclk_rates));
797
798 rockchip_clk_register_branches(ctx, px30_clk_pmu_branches, ARRAY_SIZE(px30_clk_pmu_branches));
799
800 rockchip_clk_of_add_provider(np, ctx);
801 }
802 CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);
803
804 struct clk_px30_inits {
805 void (*inits)(struct device_node *np);
806 };
807
808 static const struct clk_px30_inits clk_px30_init = {
809 .inits = px30_clk_init,
810 };
811
812 static const struct clk_px30_inits clk_px30_pmu_init = {
813 .inits = px30_pmu_clk_init,
814 };
815
816 static const struct of_device_id clk_px30_match_table[] = {
817 {
818 .compatible = "rockchip,px30-cru",
819 .data = &clk_px30_init,
820 },
821 {
822 .compatible = "rockchip,px30-pmucru",
823 .data = &clk_px30_pmu_init,
824 },
825 {}
826 };
827 MODULE_DEVICE_TABLE(of, clk_px30_match_table);
828
clk_px30_probe(struct platform_device * pdev)829 static int __init clk_px30_probe(struct platform_device *pdev)
830 {
831 struct device_node *np = pdev->dev.of_node;
832 const struct of_device_id *match;
833 const struct clk_px30_inits *init_data;
834
835 match = of_match_device(clk_px30_match_table, &pdev->dev);
836 if (!match || !match->data) {
837 return -EINVAL;
838 }
839
840 init_data = match->data;
841 if (init_data->inits) {
842 init_data->inits(np);
843 }
844
845 return 0;
846 }
847
848 static struct platform_driver clk_px30_driver = {
849 .driver =
850 {
851 .name = "clk-px30",
852 .of_match_table = clk_px30_match_table,
853 },
854 };
855 builtin_platform_driver_probe(clk_px30_driver, clk_px30_probe);
856
857 MODULE_DESCRIPTION("Rockchip PX30 Clock Driver");
858 MODULE_LICENSE("GPL");
859