1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8996.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,apr.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32764>; 31 clock-output-names = "sleep_clk"; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 capacity-dmips-mhz = <1024>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 capacity-dmips-mhz = <1024>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 CPU2: cpu@100 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo"; 66 reg = <0x0 0x100>; 67 enable-method = "psci"; 68 cpu-idle-states = <&CPU_SLEEP_0>; 69 capacity-dmips-mhz = <1024>; 70 next-level-cache = <&L2_1>; 71 L2_1: l2-cache { 72 compatible = "cache"; 73 cache-level = <2>; 74 }; 75 }; 76 77 CPU3: cpu@101 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo"; 80 reg = <0x0 0x101>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CPU_SLEEP_0>; 83 capacity-dmips-mhz = <1024>; 84 next-level-cache = <&L2_1>; 85 }; 86 87 cpu-map { 88 cluster0 { 89 core0 { 90 cpu = <&CPU0>; 91 }; 92 93 core1 { 94 cpu = <&CPU1>; 95 }; 96 }; 97 98 cluster1 { 99 core0 { 100 cpu = <&CPU2>; 101 }; 102 103 core1 { 104 cpu = <&CPU3>; 105 }; 106 }; 107 }; 108 109 idle-states { 110 entry-method = "psci"; 111 112 CPU_SLEEP_0: cpu-sleep-0 { 113 compatible = "arm,idle-state"; 114 idle-state-name = "standalone-power-collapse"; 115 arm,psci-suspend-param = <0x00000004>; 116 entry-latency-us = <130>; 117 exit-latency-us = <80>; 118 min-residency-us = <300>; 119 }; 120 }; 121 }; 122 123 firmware { 124 scm { 125 compatible = "qcom,scm-msm8996"; 126 qcom,dload-mode = <&tcsr 0x13000>; 127 }; 128 }; 129 130 tcsr_mutex: hwlock { 131 compatible = "qcom,tcsr-mutex"; 132 syscon = <&tcsr_mutex_regs 0 0x1000>; 133 #hwlock-cells = <1>; 134 }; 135 136 memory { 137 device_type = "memory"; 138 /* We expect the bootloader to fill in the reg */ 139 reg = <0 0 0 0>; 140 }; 141 142 psci { 143 compatible = "arm,psci-1.0"; 144 method = "smc"; 145 }; 146 147 reserved-memory { 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 mba_region: mba@91500000 { 153 reg = <0x0 0x91500000 0x0 0x200000>; 154 no-map; 155 }; 156 157 slpi_region: slpi@90b00000 { 158 reg = <0x0 0x90b00000 0x0 0xa00000>; 159 no-map; 160 }; 161 162 venus_region: venus@90400000 { 163 reg = <0x0 0x90400000 0x0 0x700000>; 164 no-map; 165 }; 166 167 adsp_region: adsp@8ea00000 { 168 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 169 no-map; 170 }; 171 172 mpss_region: mpss@88800000 { 173 reg = <0x0 0x88800000 0x0 0x6200000>; 174 no-map; 175 }; 176 177 smem_mem: smem-mem@86000000 { 178 reg = <0x0 0x86000000 0x0 0x200000>; 179 no-map; 180 }; 181 182 memory@85800000 { 183 reg = <0x0 0x85800000 0x0 0x800000>; 184 no-map; 185 }; 186 187 memory@86200000 { 188 reg = <0x0 0x86200000 0x0 0x2600000>; 189 no-map; 190 }; 191 192 rmtfs@86700000 { 193 compatible = "qcom,rmtfs-mem"; 194 195 size = <0x0 0x200000>; 196 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 197 no-map; 198 199 qcom,client-id = <1>; 200 qcom,vmid = <15>; 201 }; 202 203 zap_shader_region: gpu@8f200000 { 204 compatible = "shared-dma-pool"; 205 reg = <0x0 0x90b00000 0x0 0xa00000>; 206 no-map; 207 }; 208 }; 209 210 rpm-glink { 211 compatible = "qcom,glink-rpm"; 212 213 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 214 215 qcom,rpm-msg-ram = <&rpm_msg_ram>; 216 217 mboxes = <&apcs_glb 0>; 218 219 rpm_requests: rpm-requests { 220 compatible = "qcom,rpm-msm8996"; 221 qcom,glink-channels = "rpm_requests"; 222 223 rpmcc: qcom,rpmcc { 224 compatible = "qcom,rpmcc-msm8996"; 225 #clock-cells = <1>; 226 }; 227 228 rpmpd: power-controller { 229 compatible = "qcom,msm8996-rpmpd"; 230 #power-domain-cells = <1>; 231 operating-points-v2 = <&rpmpd_opp_table>; 232 233 rpmpd_opp_table: opp-table { 234 compatible = "operating-points-v2"; 235 236 rpmpd_opp1: opp1 { 237 opp-level = <1>; 238 }; 239 240 rpmpd_opp2: opp2 { 241 opp-level = <2>; 242 }; 243 244 rpmpd_opp3: opp3 { 245 opp-level = <3>; 246 }; 247 248 rpmpd_opp4: opp4 { 249 opp-level = <4>; 250 }; 251 252 rpmpd_opp5: opp5 { 253 opp-level = <5>; 254 }; 255 256 rpmpd_opp6: opp6 { 257 opp-level = <6>; 258 }; 259 }; 260 }; 261 }; 262 }; 263 264 smem { 265 compatible = "qcom,smem"; 266 memory-region = <&smem_mem>; 267 hwlocks = <&tcsr_mutex 3>; 268 }; 269 270 smp2p-adsp { 271 compatible = "qcom,smp2p"; 272 qcom,smem = <443>, <429>; 273 274 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 275 276 mboxes = <&apcs_glb 10>; 277 278 qcom,local-pid = <0>; 279 qcom,remote-pid = <2>; 280 281 smp2p_adsp_out: master-kernel { 282 qcom,entry-name = "master-kernel"; 283 #qcom,smem-state-cells = <1>; 284 }; 285 286 smp2p_adsp_in: slave-kernel { 287 qcom,entry-name = "slave-kernel"; 288 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 }; 293 294 smp2p-modem { 295 compatible = "qcom,smp2p"; 296 qcom,smem = <435>, <428>; 297 298 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 299 300 mboxes = <&apcs_glb 14>; 301 302 qcom,local-pid = <0>; 303 qcom,remote-pid = <1>; 304 305 modem_smp2p_out: master-kernel { 306 qcom,entry-name = "master-kernel"; 307 #qcom,smem-state-cells = <1>; 308 }; 309 310 modem_smp2p_in: slave-kernel { 311 qcom,entry-name = "slave-kernel"; 312 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 }; 316 }; 317 318 smp2p-slpi { 319 compatible = "qcom,smp2p"; 320 qcom,smem = <481>, <430>; 321 322 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 323 324 mboxes = <&apcs_glb 26>; 325 326 qcom,local-pid = <0>; 327 qcom,remote-pid = <3>; 328 329 smp2p_slpi_in: slave-kernel { 330 qcom,entry-name = "slave-kernel"; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 }; 334 335 smp2p_slpi_out: master-kernel { 336 qcom,entry-name = "master-kernel"; 337 #qcom,smem-state-cells = <1>; 338 }; 339 }; 340 341 soc: soc { 342 #address-cells = <1>; 343 #size-cells = <1>; 344 ranges = <0 0 0 0xffffffff>; 345 compatible = "simple-bus"; 346 347 pcie_phy: phy@34000 { 348 compatible = "qcom,msm8996-qmp-pcie-phy"; 349 reg = <0x00034000 0x488>; 350 #clock-cells = <1>; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges; 354 355 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 356 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 357 <&gcc GCC_PCIE_CLKREF_CLK>; 358 clock-names = "aux", "cfg_ahb", "ref"; 359 360 resets = <&gcc GCC_PCIE_PHY_BCR>, 361 <&gcc GCC_PCIE_PHY_COM_BCR>, 362 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 363 reset-names = "phy", "common", "cfg"; 364 status = "disabled"; 365 366 pciephy_0: lane@35000 { 367 reg = <0x00035000 0x130>, 368 <0x00035200 0x200>, 369 <0x00035400 0x1dc>; 370 #phy-cells = <0>; 371 372 clock-output-names = "pcie_0_pipe_clk_src"; 373 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 374 clock-names = "pipe0"; 375 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 376 reset-names = "lane0"; 377 }; 378 379 pciephy_1: lane@36000 { 380 reg = <0x00036000 0x130>, 381 <0x00036200 0x200>, 382 <0x00036400 0x1dc>; 383 #phy-cells = <0>; 384 385 clock-output-names = "pcie_1_pipe_clk_src"; 386 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 387 clock-names = "pipe1"; 388 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 389 reset-names = "lane1"; 390 }; 391 392 pciephy_2: lane@37000 { 393 reg = <0x00037000 0x130>, 394 <0x00037200 0x200>, 395 <0x00037400 0x1dc>; 396 #phy-cells = <0>; 397 398 clock-output-names = "pcie_2_pipe_clk_src"; 399 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 400 clock-names = "pipe2"; 401 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 402 reset-names = "lane2"; 403 }; 404 }; 405 406 rpm_msg_ram: memory@68000 { 407 compatible = "qcom,rpm-msg-ram"; 408 reg = <0x00068000 0x6000>; 409 }; 410 411 qfprom@74000 { 412 compatible = "qcom,qfprom"; 413 reg = <0x00074000 0x8ff>; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 417 qusb2p_hstx_trim: hstx_trim@24e { 418 reg = <0x24e 0x2>; 419 bits = <5 4>; 420 }; 421 422 qusb2s_hstx_trim: hstx_trim@24f { 423 reg = <0x24f 0x1>; 424 bits = <1 4>; 425 }; 426 427 gpu_speed_bin: gpu_speed_bin@133 { 428 reg = <0x133 0x1>; 429 bits = <5 3>; 430 }; 431 }; 432 433 rng: rng@83000 { 434 compatible = "qcom,prng-ee"; 435 reg = <0x00083000 0x1000>; 436 clocks = <&gcc GCC_PRNG_AHB_CLK>; 437 clock-names = "core"; 438 }; 439 440 gcc: clock-controller@300000 { 441 compatible = "qcom,gcc-msm8996"; 442 #clock-cells = <1>; 443 #reset-cells = <1>; 444 #power-domain-cells = <1>; 445 reg = <0x00300000 0x90000>; 446 447 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; 448 clock-names = "cxo2"; 449 }; 450 451 tsens0: thermal-sensor@4a9000 { 452 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 453 reg = <0x004a9000 0x1000>, /* TM */ 454 <0x004a8000 0x1000>; /* SROT */ 455 #qcom,sensors = <13>; 456 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-names = "uplow", "critical"; 459 #thermal-sensor-cells = <1>; 460 }; 461 462 tsens1: thermal-sensor@4ad000 { 463 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 464 reg = <0x004ad000 0x1000>, /* TM */ 465 <0x004ac000 0x1000>; /* SROT */ 466 #qcom,sensors = <8>; 467 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 469 interrupt-names = "uplow", "critical"; 470 #thermal-sensor-cells = <1>; 471 }; 472 473 tcsr_mutex_regs: syscon@740000 { 474 compatible = "syscon"; 475 reg = <0x00740000 0x20000>; 476 }; 477 478 tcsr: syscon@7a0000 { 479 compatible = "qcom,tcsr-msm8996", "syscon"; 480 reg = <0x007a0000 0x18000>; 481 }; 482 483 mmcc: clock-controller@8c0000 { 484 compatible = "qcom,mmcc-msm8996"; 485 #clock-cells = <1>; 486 #reset-cells = <1>; 487 #power-domain-cells = <1>; 488 reg = <0x008c0000 0x40000>; 489 assigned-clocks = <&mmcc MMPLL9_PLL>, 490 <&mmcc MMPLL1_PLL>, 491 <&mmcc MMPLL3_PLL>, 492 <&mmcc MMPLL4_PLL>, 493 <&mmcc MMPLL5_PLL>; 494 assigned-clock-rates = <624000000>, 495 <810000000>, 496 <980000000>, 497 <960000000>, 498 <825000000>; 499 }; 500 501 mdss: mdss@900000 { 502 compatible = "qcom,mdss"; 503 504 reg = <0x00900000 0x1000>, 505 <0x009b0000 0x1040>, 506 <0x009b8000 0x1040>; 507 reg-names = "mdss_phys", 508 "vbif_phys", 509 "vbif_nrt_phys"; 510 511 power-domains = <&mmcc MDSS_GDSC>; 512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 513 514 interrupt-controller; 515 #interrupt-cells = <1>; 516 517 clocks = <&mmcc MDSS_AHB_CLK>; 518 clock-names = "iface"; 519 520 #address-cells = <1>; 521 #size-cells = <1>; 522 ranges; 523 524 mdp: mdp@901000 { 525 compatible = "qcom,mdp5"; 526 reg = <0x00901000 0x90000>; 527 reg-names = "mdp_phys"; 528 529 interrupt-parent = <&mdss>; 530 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 531 532 clocks = <&mmcc MDSS_AHB_CLK>, 533 <&mmcc MDSS_AXI_CLK>, 534 <&mmcc MDSS_MDP_CLK>, 535 <&mmcc SMMU_MDP_AXI_CLK>, 536 <&mmcc MDSS_VSYNC_CLK>; 537 clock-names = "iface", 538 "bus", 539 "core", 540 "iommu", 541 "vsync"; 542 543 iommus = <&mdp_smmu 0>; 544 545 ports { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 port@0 { 550 reg = <0>; 551 mdp5_intf3_out: endpoint { 552 remote-endpoint = <&hdmi_in>; 553 }; 554 }; 555 }; 556 }; 557 558 hdmi: hdmi-tx@9a0000 { 559 compatible = "qcom,hdmi-tx-8996"; 560 reg = <0x009a0000 0x50c>, 561 <0x00070000 0x6158>, 562 <0x009e0000 0xfff>; 563 reg-names = "core_physical", 564 "qfprom_physical", 565 "hdcp_physical"; 566 567 interrupt-parent = <&mdss>; 568 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 569 570 clocks = <&mmcc MDSS_MDP_CLK>, 571 <&mmcc MDSS_AHB_CLK>, 572 <&mmcc MDSS_HDMI_CLK>, 573 <&mmcc MDSS_HDMI_AHB_CLK>, 574 <&mmcc MDSS_EXTPCLK_CLK>; 575 clock-names = 576 "mdp_core", 577 "iface", 578 "core", 579 "alt_iface", 580 "extp"; 581 582 phys = <&hdmi_phy>; 583 phy-names = "hdmi_phy"; 584 #sound-dai-cells = <1>; 585 586 ports { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 590 port@0 { 591 reg = <0>; 592 hdmi_in: endpoint { 593 remote-endpoint = <&mdp5_intf3_out>; 594 }; 595 }; 596 }; 597 }; 598 599 hdmi_phy: hdmi-phy@9a0600 { 600 #phy-cells = <0>; 601 compatible = "qcom,hdmi-phy-8996"; 602 reg = <0x009a0600 0x1c4>, 603 <0x009a0a00 0x124>, 604 <0x009a0c00 0x124>, 605 <0x009a0e00 0x124>, 606 <0x009a1000 0x124>, 607 <0x009a1200 0x0c8>; 608 reg-names = "hdmi_pll", 609 "hdmi_tx_l0", 610 "hdmi_tx_l1", 611 "hdmi_tx_l2", 612 "hdmi_tx_l3", 613 "hdmi_phy"; 614 615 clocks = <&mmcc MDSS_AHB_CLK>, 616 <&gcc GCC_HDMI_CLKREF_CLK>; 617 clock-names = "iface", 618 "ref"; 619 }; 620 }; 621 gpu@b00000 { 622 compatible = "qcom,adreno-530.2", "qcom,adreno"; 623 #stream-id-cells = <16>; 624 625 reg = <0x00b00000 0x3f000>; 626 reg-names = "kgsl_3d0_reg_memory"; 627 628 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 629 630 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 631 <&mmcc GPU_AHB_CLK>, 632 <&mmcc GPU_GX_RBBMTIMER_CLK>, 633 <&gcc GCC_BIMC_GFX_CLK>, 634 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 635 636 clock-names = "core", 637 "iface", 638 "rbbmtimer", 639 "mem", 640 "mem_iface"; 641 642 power-domains = <&mmcc GPU_GX_GDSC>; 643 iommus = <&adreno_smmu 0>; 644 645 nvmem-cells = <&gpu_speed_bin>; 646 nvmem-cell-names = "speed_bin"; 647 648 operating-points-v2 = <&gpu_opp_table>; 649 650 gpu_opp_table: opp-table { 651 compatible ="operating-points-v2"; 652 653 /* 654 * 624Mhz is only available on speed bins 0 and 3. 655 * 560Mhz is only available on speed bins 0, 2 and 3. 656 * All the rest are available on all bins of the hardware. 657 */ 658 opp-624000000 { 659 opp-hz = /bits/ 64 <624000000>; 660 opp-supported-hw = <0x09>; 661 }; 662 opp-560000000 { 663 opp-hz = /bits/ 64 <560000000>; 664 opp-supported-hw = <0x0d>; 665 }; 666 opp-510000000 { 667 opp-hz = /bits/ 64 <510000000>; 668 opp-supported-hw = <0xFF>; 669 }; 670 opp-401800000 { 671 opp-hz = /bits/ 64 <401800000>; 672 opp-supported-hw = <0xFF>; 673 }; 674 opp-315000000 { 675 opp-hz = /bits/ 64 <315000000>; 676 opp-supported-hw = <0xFF>; 677 }; 678 opp-214000000 { 679 opp-hz = /bits/ 64 <214000000>; 680 opp-supported-hw = <0xFF>; 681 }; 682 opp-133000000 { 683 opp-hz = /bits/ 64 <133000000>; 684 opp-supported-hw = <0xFF>; 685 }; 686 }; 687 688 zap-shader { 689 memory-region = <&zap_shader_region>; 690 }; 691 }; 692 693 msmgpio: pinctrl@1010000 { 694 compatible = "qcom,msm8996-pinctrl"; 695 reg = <0x01010000 0x300000>; 696 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 697 gpio-controller; 698 gpio-ranges = <&msmgpio 0 0 150>; 699 #gpio-cells = <2>; 700 interrupt-controller; 701 #interrupt-cells = <2>; 702 }; 703 704 spmi_bus: qcom,spmi@400f000 { 705 compatible = "qcom,spmi-pmic-arb"; 706 reg = <0x0400f000 0x1000>, 707 <0x04400000 0x800000>, 708 <0x04c00000 0x800000>, 709 <0x05800000 0x200000>, 710 <0x0400a000 0x002100>; 711 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 712 interrupt-names = "periph_irq"; 713 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 714 qcom,ee = <0>; 715 qcom,channel = <0>; 716 #address-cells = <2>; 717 #size-cells = <0>; 718 interrupt-controller; 719 #interrupt-cells = <4>; 720 }; 721 722 agnoc@0 { 723 power-domains = <&gcc AGGRE0_NOC_GDSC>; 724 compatible = "simple-pm-bus"; 725 #address-cells = <1>; 726 #size-cells = <1>; 727 ranges; 728 729 pcie0: pcie@600000 { 730 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 731 status = "disabled"; 732 power-domains = <&gcc PCIE0_GDSC>; 733 bus-range = <0x00 0xff>; 734 num-lanes = <1>; 735 736 reg = <0x00600000 0x2000>, 737 <0x0c000000 0xf1d>, 738 <0x0c000f20 0xa8>, 739 <0x0c100000 0x100000>; 740 reg-names = "parf", "dbi", "elbi","config"; 741 742 phys = <&pciephy_0>; 743 phy-names = "pciephy"; 744 745 #address-cells = <3>; 746 #size-cells = <2>; 747 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 748 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 749 750 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 751 interrupt-names = "msi"; 752 #interrupt-cells = <1>; 753 interrupt-map-mask = <0 0 0 0x7>; 754 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 755 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 756 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 757 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 758 759 pinctrl-names = "default", "sleep"; 760 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; 761 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; 762 763 linux,pci-domain = <0>; 764 765 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 766 <&gcc GCC_PCIE_0_AUX_CLK>, 767 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 768 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 769 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 770 771 clock-names = "pipe", 772 "aux", 773 "cfg", 774 "bus_master", 775 "bus_slave"; 776 777 }; 778 779 pcie1: pcie@608000 { 780 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 781 power-domains = <&gcc PCIE1_GDSC>; 782 bus-range = <0x00 0xff>; 783 num-lanes = <1>; 784 785 status = "disabled"; 786 787 reg = <0x00608000 0x2000>, 788 <0x0d000000 0xf1d>, 789 <0x0d000f20 0xa8>, 790 <0x0d100000 0x100000>; 791 792 reg-names = "parf", "dbi", "elbi","config"; 793 794 phys = <&pciephy_1>; 795 phy-names = "pciephy"; 796 797 #address-cells = <3>; 798 #size-cells = <2>; 799 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 800 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 801 802 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 803 interrupt-names = "msi"; 804 #interrupt-cells = <1>; 805 interrupt-map-mask = <0 0 0 0x7>; 806 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 807 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 808 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 809 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 810 811 pinctrl-names = "default", "sleep"; 812 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; 813 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; 814 815 linux,pci-domain = <1>; 816 817 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 818 <&gcc GCC_PCIE_1_AUX_CLK>, 819 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 820 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 821 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 822 823 clock-names = "pipe", 824 "aux", 825 "cfg", 826 "bus_master", 827 "bus_slave"; 828 }; 829 830 pcie2: pcie@610000 { 831 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 832 power-domains = <&gcc PCIE2_GDSC>; 833 bus-range = <0x00 0xff>; 834 num-lanes = <1>; 835 status = "disabled"; 836 reg = <0x00610000 0x2000>, 837 <0x0e000000 0xf1d>, 838 <0x0e000f20 0xa8>, 839 <0x0e100000 0x100000>; 840 841 reg-names = "parf", "dbi", "elbi","config"; 842 843 phys = <&pciephy_2>; 844 phy-names = "pciephy"; 845 846 #address-cells = <3>; 847 #size-cells = <2>; 848 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 849 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 850 851 device_type = "pci"; 852 853 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 854 interrupt-names = "msi"; 855 #interrupt-cells = <1>; 856 interrupt-map-mask = <0 0 0 0x7>; 857 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 858 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 859 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 860 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 861 862 pinctrl-names = "default", "sleep"; 863 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; 864 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; 865 866 linux,pci-domain = <2>; 867 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 868 <&gcc GCC_PCIE_2_AUX_CLK>, 869 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 870 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 871 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 872 873 clock-names = "pipe", 874 "aux", 875 "cfg", 876 "bus_master", 877 "bus_slave"; 878 }; 879 }; 880 881 ufshc: ufshc@624000 { 882 compatible = "qcom,ufshc"; 883 reg = <0x00624000 0x2500>; 884 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 885 886 phys = <&ufsphy_lane>; 887 phy-names = "ufsphy"; 888 889 power-domains = <&gcc UFS_GDSC>; 890 891 clock-names = 892 "core_clk_src", 893 "core_clk", 894 "bus_clk", 895 "bus_aggr_clk", 896 "iface_clk", 897 "core_clk_unipro_src", 898 "core_clk_unipro", 899 "core_clk_ice", 900 "ref_clk", 901 "tx_lane0_sync_clk", 902 "rx_lane0_sync_clk"; 903 clocks = 904 <&gcc UFS_AXI_CLK_SRC>, 905 <&gcc GCC_UFS_AXI_CLK>, 906 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 907 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 908 <&gcc GCC_UFS_AHB_CLK>, 909 <&gcc UFS_ICE_CORE_CLK_SRC>, 910 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 911 <&gcc GCC_UFS_ICE_CORE_CLK>, 912 <&rpmcc RPM_SMD_LN_BB_CLK>, 913 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 914 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 915 freq-table-hz = 916 <100000000 200000000>, 917 <0 0>, 918 <0 0>, 919 <0 0>, 920 <0 0>, 921 <150000000 300000000>, 922 <0 0>, 923 <0 0>, 924 <0 0>, 925 <0 0>, 926 <0 0>; 927 928 lanes-per-direction = <1>; 929 #reset-cells = <1>; 930 status = "disabled"; 931 932 ufs_variant { 933 compatible = "qcom,ufs_variant"; 934 }; 935 }; 936 937 ufsphy: phy@627000 { 938 compatible = "qcom,msm8996-qmp-ufs-phy"; 939 reg = <0x00627000 0x1c4>; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 ranges; 943 944 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 945 clock-names = "ref"; 946 947 resets = <&ufshc 0>; 948 reset-names = "ufsphy"; 949 status = "disabled"; 950 951 ufsphy_lane: lanes@627400 { 952 reg = <0x627400 0x12c>, 953 <0x627600 0x200>, 954 <0x627c00 0x1b4>; 955 #phy-cells = <0>; 956 }; 957 }; 958 959 camss: camss@a34000 { 960 compatible = "qcom,msm8996-camss"; 961 reg = <0x00a34000 0x1000>, 962 <0x00a00030 0x4>, 963 <0x00a35000 0x1000>, 964 <0x00a00038 0x4>, 965 <0x00a36000 0x1000>, 966 <0x00a00040 0x4>, 967 <0x00a30000 0x100>, 968 <0x00a30400 0x100>, 969 <0x00a30800 0x100>, 970 <0x00a30c00 0x100>, 971 <0x00a31000 0x500>, 972 <0x00a00020 0x10>, 973 <0x00a10000 0x1000>, 974 <0x00a14000 0x1000>; 975 reg-names = "csiphy0", 976 "csiphy0_clk_mux", 977 "csiphy1", 978 "csiphy1_clk_mux", 979 "csiphy2", 980 "csiphy2_clk_mux", 981 "csid0", 982 "csid1", 983 "csid2", 984 "csid3", 985 "ispif", 986 "csi_clk_mux", 987 "vfe0", 988 "vfe1"; 989 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 990 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 991 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 992 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 993 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 994 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 995 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 996 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 997 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 998 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 999 interrupt-names = "csiphy0", 1000 "csiphy1", 1001 "csiphy2", 1002 "csid0", 1003 "csid1", 1004 "csid2", 1005 "csid3", 1006 "ispif", 1007 "vfe0", 1008 "vfe1"; 1009 power-domains = <&mmcc VFE0_GDSC>, 1010 <&mmcc VFE1_GDSC>; 1011 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1012 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1013 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1014 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1015 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1016 <&mmcc CAMSS_CSI0_AHB_CLK>, 1017 <&mmcc CAMSS_CSI0_CLK>, 1018 <&mmcc CAMSS_CSI0PHY_CLK>, 1019 <&mmcc CAMSS_CSI0PIX_CLK>, 1020 <&mmcc CAMSS_CSI0RDI_CLK>, 1021 <&mmcc CAMSS_CSI1_AHB_CLK>, 1022 <&mmcc CAMSS_CSI1_CLK>, 1023 <&mmcc CAMSS_CSI1PHY_CLK>, 1024 <&mmcc CAMSS_CSI1PIX_CLK>, 1025 <&mmcc CAMSS_CSI1RDI_CLK>, 1026 <&mmcc CAMSS_CSI2_AHB_CLK>, 1027 <&mmcc CAMSS_CSI2_CLK>, 1028 <&mmcc CAMSS_CSI2PHY_CLK>, 1029 <&mmcc CAMSS_CSI2PIX_CLK>, 1030 <&mmcc CAMSS_CSI2RDI_CLK>, 1031 <&mmcc CAMSS_CSI3_AHB_CLK>, 1032 <&mmcc CAMSS_CSI3_CLK>, 1033 <&mmcc CAMSS_CSI3PHY_CLK>, 1034 <&mmcc CAMSS_CSI3PIX_CLK>, 1035 <&mmcc CAMSS_CSI3RDI_CLK>, 1036 <&mmcc CAMSS_AHB_CLK>, 1037 <&mmcc CAMSS_VFE0_CLK>, 1038 <&mmcc CAMSS_CSI_VFE0_CLK>, 1039 <&mmcc CAMSS_VFE0_AHB_CLK>, 1040 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1041 <&mmcc CAMSS_VFE1_CLK>, 1042 <&mmcc CAMSS_CSI_VFE1_CLK>, 1043 <&mmcc CAMSS_VFE1_AHB_CLK>, 1044 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1045 <&mmcc CAMSS_VFE_AHB_CLK>, 1046 <&mmcc CAMSS_VFE_AXI_CLK>; 1047 clock-names = "top_ahb", 1048 "ispif_ahb", 1049 "csiphy0_timer", 1050 "csiphy1_timer", 1051 "csiphy2_timer", 1052 "csi0_ahb", 1053 "csi0", 1054 "csi0_phy", 1055 "csi0_pix", 1056 "csi0_rdi", 1057 "csi1_ahb", 1058 "csi1", 1059 "csi1_phy", 1060 "csi1_pix", 1061 "csi1_rdi", 1062 "csi2_ahb", 1063 "csi2", 1064 "csi2_phy", 1065 "csi2_pix", 1066 "csi2_rdi", 1067 "csi3_ahb", 1068 "csi3", 1069 "csi3_phy", 1070 "csi3_pix", 1071 "csi3_rdi", 1072 "ahb", 1073 "vfe0", 1074 "csi_vfe0", 1075 "vfe0_ahb", 1076 "vfe0_stream", 1077 "vfe1", 1078 "csi_vfe1", 1079 "vfe1_ahb", 1080 "vfe1_stream", 1081 "vfe_ahb", 1082 "vfe_axi"; 1083 iommus = <&vfe_smmu 0>, 1084 <&vfe_smmu 1>, 1085 <&vfe_smmu 2>, 1086 <&vfe_smmu 3>; 1087 status = "disabled"; 1088 ports { 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 }; 1092 }; 1093 1094 cci: cci@a0c000 { 1095 compatible = "qcom,msm8996-cci"; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 reg = <0xa0c000 0x1000>; 1099 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 1100 power-domains = <&mmcc CAMSS_GDSC>; 1101 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1102 <&mmcc CAMSS_CCI_AHB_CLK>, 1103 <&mmcc CAMSS_CCI_CLK>, 1104 <&mmcc CAMSS_AHB_CLK>; 1105 clock-names = "camss_top_ahb", 1106 "cci_ahb", 1107 "cci", 1108 "camss_ahb"; 1109 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 1110 <&mmcc CAMSS_CCI_CLK>; 1111 assigned-clock-rates = <80000000>, <37500000>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&cci0_default &cci1_default>; 1114 status = "disabled"; 1115 1116 cci_i2c0: i2c-bus@0 { 1117 reg = <0>; 1118 clock-frequency = <400000>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 }; 1122 1123 cci_i2c1: i2c-bus@1 { 1124 reg = <1>; 1125 clock-frequency = <400000>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 }; 1129 }; 1130 1131 adreno_smmu: iommu@b40000 { 1132 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1133 reg = <0x00b40000 0x10000>; 1134 1135 #global-interrupts = <1>; 1136 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1139 #iommu-cells = <1>; 1140 1141 clocks = <&mmcc GPU_AHB_CLK>, 1142 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1143 clock-names = "iface", "bus"; 1144 1145 power-domains = <&mmcc GPU_GDSC>; 1146 }; 1147 1148 video-codec@c00000 { 1149 compatible = "qcom,msm8996-venus"; 1150 reg = <0x00c00000 0xff000>; 1151 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 1152 power-domains = <&mmcc VENUS_GDSC>; 1153 clocks = <&mmcc VIDEO_CORE_CLK>, 1154 <&mmcc VIDEO_AHB_CLK>, 1155 <&mmcc VIDEO_AXI_CLK>, 1156 <&mmcc VIDEO_MAXI_CLK>; 1157 clock-names = "core", "iface", "bus", "mbus"; 1158 iommus = <&venus_smmu 0x00>, 1159 <&venus_smmu 0x01>, 1160 <&venus_smmu 0x0a>, 1161 <&venus_smmu 0x07>, 1162 <&venus_smmu 0x0e>, 1163 <&venus_smmu 0x0f>, 1164 <&venus_smmu 0x08>, 1165 <&venus_smmu 0x09>, 1166 <&venus_smmu 0x0b>, 1167 <&venus_smmu 0x0c>, 1168 <&venus_smmu 0x0d>, 1169 <&venus_smmu 0x10>, 1170 <&venus_smmu 0x11>, 1171 <&venus_smmu 0x21>, 1172 <&venus_smmu 0x28>, 1173 <&venus_smmu 0x29>, 1174 <&venus_smmu 0x2b>, 1175 <&venus_smmu 0x2c>, 1176 <&venus_smmu 0x2d>, 1177 <&venus_smmu 0x31>; 1178 memory-region = <&venus_region>; 1179 status = "okay"; 1180 1181 video-decoder { 1182 compatible = "venus-decoder"; 1183 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 1184 clock-names = "core"; 1185 power-domains = <&mmcc VENUS_CORE0_GDSC>; 1186 }; 1187 1188 video-encoder { 1189 compatible = "venus-encoder"; 1190 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 1191 clock-names = "core"; 1192 power-domains = <&mmcc VENUS_CORE1_GDSC>; 1193 }; 1194 }; 1195 1196 mdp_smmu: iommu@d00000 { 1197 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1198 reg = <0x00d00000 0x10000>; 1199 1200 #global-interrupts = <1>; 1201 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1204 #iommu-cells = <1>; 1205 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 1206 <&mmcc SMMU_MDP_AXI_CLK>; 1207 clock-names = "iface", "bus"; 1208 1209 power-domains = <&mmcc MDSS_GDSC>; 1210 }; 1211 1212 venus_smmu: iommu@d40000 { 1213 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1214 reg = <0x00d40000 0x20000>; 1215 #global-interrupts = <1>; 1216 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1224 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 1225 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, 1226 <&mmcc SMMU_VIDEO_AXI_CLK>; 1227 clock-names = "iface", "bus"; 1228 #iommu-cells = <1>; 1229 status = "okay"; 1230 }; 1231 1232 vfe_smmu: iommu@da0000 { 1233 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1234 reg = <0x00da0000 0x10000>; 1235 1236 #global-interrupts = <1>; 1237 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1240 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 1241 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 1242 <&mmcc SMMU_VFE_AXI_CLK>; 1243 clock-names = "iface", 1244 "bus"; 1245 #iommu-cells = <1>; 1246 }; 1247 1248 lpass_q6_smmu: iommu@1600000 { 1249 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1250 reg = <0x01600000 0x20000>; 1251 #iommu-cells = <1>; 1252 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 1253 1254 #global-interrupts = <1>; 1255 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 1268 1269 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 1270 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1271 clock-names = "iface", "bus"; 1272 }; 1273 1274 stm@3002000 { 1275 compatible = "arm,coresight-stm", "arm,primecell"; 1276 reg = <0x3002000 0x1000>, 1277 <0x8280000 0x180000>; 1278 reg-names = "stm-base", "stm-stimulus-base"; 1279 1280 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1281 clock-names = "apb_pclk", "atclk"; 1282 1283 out-ports { 1284 port { 1285 stm_out: endpoint { 1286 remote-endpoint = 1287 <&funnel0_in>; 1288 }; 1289 }; 1290 }; 1291 }; 1292 1293 tpiu@3020000 { 1294 compatible = "arm,coresight-tpiu", "arm,primecell"; 1295 reg = <0x3020000 0x1000>; 1296 1297 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1298 clock-names = "apb_pclk", "atclk"; 1299 1300 in-ports { 1301 port { 1302 tpiu_in: endpoint { 1303 remote-endpoint = 1304 <&replicator_out1>; 1305 }; 1306 }; 1307 }; 1308 }; 1309 1310 funnel@3021000 { 1311 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1312 reg = <0x3021000 0x1000>; 1313 1314 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1315 clock-names = "apb_pclk", "atclk"; 1316 1317 in-ports { 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 1321 port@7 { 1322 reg = <7>; 1323 funnel0_in: endpoint { 1324 remote-endpoint = 1325 <&stm_out>; 1326 }; 1327 }; 1328 }; 1329 1330 out-ports { 1331 port { 1332 funnel0_out: endpoint { 1333 remote-endpoint = 1334 <&merge_funnel_in0>; 1335 }; 1336 }; 1337 }; 1338 }; 1339 1340 funnel@3022000 { 1341 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1342 reg = <0x3022000 0x1000>; 1343 1344 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1345 clock-names = "apb_pclk", "atclk"; 1346 1347 in-ports { 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 1351 port@6 { 1352 reg = <6>; 1353 funnel1_in: endpoint { 1354 remote-endpoint = 1355 <&apss_merge_funnel_out>; 1356 }; 1357 }; 1358 }; 1359 1360 out-ports { 1361 port { 1362 funnel1_out: endpoint { 1363 remote-endpoint = 1364 <&merge_funnel_in1>; 1365 }; 1366 }; 1367 }; 1368 }; 1369 1370 funnel@3023000 { 1371 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1372 reg = <0x3023000 0x1000>; 1373 1374 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1375 clock-names = "apb_pclk", "atclk"; 1376 1377 1378 out-ports { 1379 port { 1380 funnel2_out: endpoint { 1381 remote-endpoint = 1382 <&merge_funnel_in2>; 1383 }; 1384 }; 1385 }; 1386 }; 1387 1388 funnel@3025000 { 1389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1390 reg = <0x3025000 0x1000>; 1391 1392 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1393 clock-names = "apb_pclk", "atclk"; 1394 1395 in-ports { 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 1399 port@0 { 1400 reg = <0>; 1401 merge_funnel_in0: endpoint { 1402 remote-endpoint = 1403 <&funnel0_out>; 1404 }; 1405 }; 1406 1407 port@1 { 1408 reg = <1>; 1409 merge_funnel_in1: endpoint { 1410 remote-endpoint = 1411 <&funnel1_out>; 1412 }; 1413 }; 1414 1415 port@2 { 1416 reg = <2>; 1417 merge_funnel_in2: endpoint { 1418 remote-endpoint = 1419 <&funnel2_out>; 1420 }; 1421 }; 1422 }; 1423 1424 out-ports { 1425 port { 1426 merge_funnel_out: endpoint { 1427 remote-endpoint = 1428 <&etf_in>; 1429 }; 1430 }; 1431 }; 1432 }; 1433 1434 replicator@3026000 { 1435 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1436 reg = <0x3026000 0x1000>; 1437 1438 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1439 clock-names = "apb_pclk", "atclk"; 1440 1441 in-ports { 1442 port { 1443 replicator_in: endpoint { 1444 remote-endpoint = 1445 <&etf_out>; 1446 }; 1447 }; 1448 }; 1449 1450 out-ports { 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 1454 port@0 { 1455 reg = <0>; 1456 replicator_out0: endpoint { 1457 remote-endpoint = 1458 <&etr_in>; 1459 }; 1460 }; 1461 1462 port@1 { 1463 reg = <1>; 1464 replicator_out1: endpoint { 1465 remote-endpoint = 1466 <&tpiu_in>; 1467 }; 1468 }; 1469 }; 1470 }; 1471 1472 etf@3027000 { 1473 compatible = "arm,coresight-tmc", "arm,primecell"; 1474 reg = <0x3027000 0x1000>; 1475 1476 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1477 clock-names = "apb_pclk", "atclk"; 1478 1479 in-ports { 1480 port { 1481 etf_in: endpoint { 1482 remote-endpoint = 1483 <&merge_funnel_out>; 1484 }; 1485 }; 1486 }; 1487 1488 out-ports { 1489 port { 1490 etf_out: endpoint { 1491 remote-endpoint = 1492 <&replicator_in>; 1493 }; 1494 }; 1495 }; 1496 }; 1497 1498 etr@3028000 { 1499 compatible = "arm,coresight-tmc", "arm,primecell"; 1500 reg = <0x3028000 0x1000>; 1501 1502 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1503 clock-names = "apb_pclk", "atclk"; 1504 arm,scatter-gather; 1505 1506 in-ports { 1507 port { 1508 etr_in: endpoint { 1509 remote-endpoint = 1510 <&replicator_out0>; 1511 }; 1512 }; 1513 }; 1514 }; 1515 1516 debug@3810000 { 1517 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1518 reg = <0x3810000 0x1000>; 1519 1520 clocks = <&rpmcc RPM_QDSS_CLK>; 1521 clock-names = "apb_pclk"; 1522 1523 cpu = <&CPU0>; 1524 }; 1525 1526 etm@3840000 { 1527 compatible = "arm,coresight-etm4x", "arm,primecell"; 1528 reg = <0x3840000 0x1000>; 1529 1530 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1531 clock-names = "apb_pclk", "atclk"; 1532 1533 cpu = <&CPU0>; 1534 1535 out-ports { 1536 port { 1537 etm0_out: endpoint { 1538 remote-endpoint = 1539 <&apss_funnel0_in0>; 1540 }; 1541 }; 1542 }; 1543 }; 1544 1545 debug@3910000 { 1546 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1547 reg = <0x3910000 0x1000>; 1548 1549 clocks = <&rpmcc RPM_QDSS_CLK>; 1550 clock-names = "apb_pclk"; 1551 1552 cpu = <&CPU1>; 1553 }; 1554 1555 etm@3940000 { 1556 compatible = "arm,coresight-etm4x", "arm,primecell"; 1557 reg = <0x3940000 0x1000>; 1558 1559 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1560 clock-names = "apb_pclk", "atclk"; 1561 1562 cpu = <&CPU1>; 1563 1564 out-ports { 1565 port { 1566 etm1_out: endpoint { 1567 remote-endpoint = 1568 <&apss_funnel0_in1>; 1569 }; 1570 }; 1571 }; 1572 }; 1573 1574 funnel@39b0000 { /* APSS Funnel 0 */ 1575 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1576 reg = <0x39b0000 0x1000>; 1577 1578 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1579 clock-names = "apb_pclk", "atclk"; 1580 1581 in-ports { 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 1585 port@0 { 1586 reg = <0>; 1587 apss_funnel0_in0: endpoint { 1588 remote-endpoint = <&etm0_out>; 1589 }; 1590 }; 1591 1592 port@1 { 1593 reg = <1>; 1594 apss_funnel0_in1: endpoint { 1595 remote-endpoint = <&etm1_out>; 1596 }; 1597 }; 1598 }; 1599 1600 out-ports { 1601 port { 1602 apss_funnel0_out: endpoint { 1603 remote-endpoint = 1604 <&apss_merge_funnel_in0>; 1605 }; 1606 }; 1607 }; 1608 }; 1609 1610 debug@3a10000 { 1611 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1612 reg = <0x3a10000 0x1000>; 1613 1614 clocks = <&rpmcc RPM_QDSS_CLK>; 1615 clock-names = "apb_pclk"; 1616 1617 cpu = <&CPU2>; 1618 }; 1619 1620 etm@3a40000 { 1621 compatible = "arm,coresight-etm4x", "arm,primecell"; 1622 reg = <0x3a40000 0x1000>; 1623 1624 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1625 clock-names = "apb_pclk", "atclk"; 1626 1627 cpu = <&CPU2>; 1628 1629 out-ports { 1630 port { 1631 etm2_out: endpoint { 1632 remote-endpoint = 1633 <&apss_funnel1_in0>; 1634 }; 1635 }; 1636 }; 1637 }; 1638 1639 debug@3b10000 { 1640 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1641 reg = <0x3b10000 0x1000>; 1642 1643 clocks = <&rpmcc RPM_QDSS_CLK>; 1644 clock-names = "apb_pclk"; 1645 1646 cpu = <&CPU3>; 1647 }; 1648 1649 etm@3b40000 { 1650 compatible = "arm,coresight-etm4x", "arm,primecell"; 1651 reg = <0x3b40000 0x1000>; 1652 1653 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1654 clock-names = "apb_pclk", "atclk"; 1655 1656 cpu = <&CPU3>; 1657 1658 out-ports { 1659 port { 1660 etm3_out: endpoint { 1661 remote-endpoint = 1662 <&apss_funnel1_in1>; 1663 }; 1664 }; 1665 }; 1666 }; 1667 1668 funnel@3bb0000 { /* APSS Funnel 1 */ 1669 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1670 reg = <0x3bb0000 0x1000>; 1671 1672 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1673 clock-names = "apb_pclk", "atclk"; 1674 1675 in-ports { 1676 #address-cells = <1>; 1677 #size-cells = <0>; 1678 1679 port@0 { 1680 reg = <0>; 1681 apss_funnel1_in0: endpoint { 1682 remote-endpoint = <&etm2_out>; 1683 }; 1684 }; 1685 1686 port@1 { 1687 reg = <1>; 1688 apss_funnel1_in1: endpoint { 1689 remote-endpoint = <&etm3_out>; 1690 }; 1691 }; 1692 }; 1693 1694 out-ports { 1695 port { 1696 apss_funnel1_out: endpoint { 1697 remote-endpoint = 1698 <&apss_merge_funnel_in1>; 1699 }; 1700 }; 1701 }; 1702 }; 1703 1704 funnel@3bc0000 { 1705 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1706 reg = <0x3bc0000 0x1000>; 1707 1708 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1709 clock-names = "apb_pclk", "atclk"; 1710 1711 in-ports { 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 1715 port@0 { 1716 reg = <0>; 1717 apss_merge_funnel_in0: endpoint { 1718 remote-endpoint = 1719 <&apss_funnel0_out>; 1720 }; 1721 }; 1722 1723 port@1 { 1724 reg = <1>; 1725 apss_merge_funnel_in1: endpoint { 1726 remote-endpoint = 1727 <&apss_funnel1_out>; 1728 }; 1729 }; 1730 }; 1731 1732 out-ports { 1733 port { 1734 apss_merge_funnel_out: endpoint { 1735 remote-endpoint = 1736 <&funnel1_in>; 1737 }; 1738 }; 1739 }; 1740 }; 1741 kryocc: clock-controller@6400000 { 1742 compatible = "qcom,apcc-msm8996"; 1743 reg = <0x06400000 0x90000>; 1744 #clock-cells = <1>; 1745 }; 1746 1747 usb3: usb@6af8800 { 1748 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1749 reg = <0x06af8800 0x400>; 1750 #address-cells = <1>; 1751 #size-cells = <1>; 1752 ranges; 1753 1754 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 1755 <&gcc GCC_USB30_MASTER_CLK>, 1756 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1757 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1758 <&gcc GCC_USB30_SLEEP_CLK>, 1759 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1760 1761 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1762 <&gcc GCC_USB30_MASTER_CLK>; 1763 assigned-clock-rates = <19200000>, <120000000>; 1764 1765 power-domains = <&gcc USB30_GDSC>; 1766 status = "disabled"; 1767 1768 dwc3@6a00000 { 1769 compatible = "snps,dwc3"; 1770 reg = <0x06a00000 0xcc00>; 1771 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 1772 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 1773 phy-names = "usb2-phy", "usb3-phy"; 1774 snps,hird-threshold = /bits/ 8 <0>; 1775 snps,dis_u2_susphy_quirk; 1776 snps,dis_enblslpm_quirk; 1777 snps,is-utmi-l1-suspend; 1778 tx-fifo-resize; 1779 }; 1780 }; 1781 1782 usb3phy: phy@7410000 { 1783 compatible = "qcom,msm8996-qmp-usb3-phy"; 1784 reg = <0x07410000 0x1c4>; 1785 #clock-cells = <1>; 1786 #address-cells = <1>; 1787 #size-cells = <1>; 1788 ranges; 1789 1790 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1791 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1792 <&gcc GCC_USB3_CLKREF_CLK>; 1793 clock-names = "aux", "cfg_ahb", "ref"; 1794 1795 resets = <&gcc GCC_USB3_PHY_BCR>, 1796 <&gcc GCC_USB3PHY_PHY_BCR>; 1797 reset-names = "phy", "common"; 1798 status = "disabled"; 1799 1800 ssusb_phy_0: lane@7410200 { 1801 reg = <0x07410200 0x200>, 1802 <0x07410400 0x130>, 1803 <0x07410600 0x1a8>; 1804 #phy-cells = <0>; 1805 1806 clock-output-names = "usb3_phy_pipe_clk_src"; 1807 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1808 clock-names = "pipe0"; 1809 }; 1810 }; 1811 1812 hsusb_phy1: phy@7411000 { 1813 compatible = "qcom,msm8996-qusb2-phy"; 1814 reg = <0x07411000 0x180>; 1815 #phy-cells = <0>; 1816 1817 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1818 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1819 clock-names = "cfg_ahb", "ref"; 1820 1821 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1822 nvmem-cells = <&qusb2p_hstx_trim>; 1823 status = "disabled"; 1824 }; 1825 1826 hsusb_phy2: phy@7412000 { 1827 compatible = "qcom,msm8996-qusb2-phy"; 1828 reg = <0x07412000 0x180>; 1829 #phy-cells = <0>; 1830 1831 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1832 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 1833 clock-names = "cfg_ahb", "ref"; 1834 1835 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1836 nvmem-cells = <&qusb2s_hstx_trim>; 1837 status = "disabled"; 1838 }; 1839 1840 sdhc2: sdhci@74a4900 { 1841 status = "disabled"; 1842 compatible = "qcom,sdhci-msm-v4"; 1843 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 1844 reg-names = "hc_mem", "core_mem"; 1845 1846 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, 1847 <0 221 IRQ_TYPE_LEVEL_HIGH>; 1848 interrupt-names = "hc_irq", "pwr_irq"; 1849 1850 clock-names = "iface", "core", "xo"; 1851 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1852 <&gcc GCC_SDCC2_APPS_CLK>, 1853 <&xo_board>; 1854 bus-width = <4>; 1855 }; 1856 1857 blsp1_uart1: serial@7570000 { 1858 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1859 reg = <0x07570000 0x1000>; 1860 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1861 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1862 <&gcc GCC_BLSP1_AHB_CLK>; 1863 clock-names = "core", "iface"; 1864 status = "disabled"; 1865 }; 1866 1867 blsp1_spi0: spi@7575000 { 1868 compatible = "qcom,spi-qup-v2.2.1"; 1869 reg = <0x07575000 0x600>; 1870 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1871 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1872 <&gcc GCC_BLSP1_AHB_CLK>; 1873 clock-names = "core", "iface"; 1874 pinctrl-names = "default", "sleep"; 1875 pinctrl-0 = <&blsp1_spi0_default>; 1876 pinctrl-1 = <&blsp1_spi0_sleep>; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 status = "disabled"; 1880 }; 1881 1882 blsp1_i2c2: i2c@7577000 { 1883 compatible = "qcom,i2c-qup-v2.2.1"; 1884 reg = <0x07577000 0x1000>; 1885 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1886 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1887 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 1888 clock-names = "iface", "core"; 1889 pinctrl-names = "default", "sleep"; 1890 pinctrl-0 = <&blsp1_i2c2_default>; 1891 pinctrl-1 = <&blsp1_i2c2_sleep>; 1892 #address-cells = <1>; 1893 #size-cells = <0>; 1894 status = "disabled"; 1895 }; 1896 1897 blsp2_uart1: serial@75b0000 { 1898 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1899 reg = <0x075b0000 0x1000>; 1900 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1901 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1902 <&gcc GCC_BLSP2_AHB_CLK>; 1903 clock-names = "core", "iface"; 1904 status = "disabled"; 1905 }; 1906 1907 blsp2_uart2: serial@75b1000 { 1908 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1909 reg = <0x075b1000 0x1000>; 1910 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1911 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 1912 <&gcc GCC_BLSP2_AHB_CLK>; 1913 clock-names = "core", "iface"; 1914 status = "disabled"; 1915 }; 1916 1917 blsp2_i2c0: i2c@75b5000 { 1918 compatible = "qcom,i2c-qup-v2.2.1"; 1919 reg = <0x075b5000 0x1000>; 1920 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1921 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1922 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 1923 clock-names = "iface", "core"; 1924 pinctrl-names = "default", "sleep"; 1925 pinctrl-0 = <&blsp2_i2c0_default>; 1926 pinctrl-1 = <&blsp2_i2c0_sleep>; 1927 #address-cells = <1>; 1928 #size-cells = <0>; 1929 status = "disabled"; 1930 }; 1931 1932 blsp2_i2c1: i2c@75b6000 { 1933 compatible = "qcom,i2c-qup-v2.2.1"; 1934 reg = <0x075b6000 0x1000>; 1935 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1936 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1937 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 1938 clock-names = "iface", "core"; 1939 pinctrl-names = "default", "sleep"; 1940 pinctrl-0 = <&blsp2_i2c1_default>; 1941 pinctrl-1 = <&blsp2_i2c1_sleep>; 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 status = "disabled"; 1945 }; 1946 1947 blsp2_spi5: spi@75ba000{ 1948 compatible = "qcom,spi-qup-v2.2.1"; 1949 reg = <0x075ba000 0x600>; 1950 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1951 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 1952 <&gcc GCC_BLSP2_AHB_CLK>; 1953 clock-names = "core", "iface"; 1954 pinctrl-names = "default", "sleep"; 1955 pinctrl-0 = <&blsp2_spi5_default>; 1956 pinctrl-1 = <&blsp2_spi5_sleep>; 1957 #address-cells = <1>; 1958 #size-cells = <0>; 1959 status = "disabled"; 1960 }; 1961 1962 usb2: usb@76f8800 { 1963 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1964 reg = <0x076f8800 0x400>; 1965 #address-cells = <1>; 1966 #size-cells = <1>; 1967 ranges; 1968 1969 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1970 interrupt-names = "hs_phy_irq"; 1971 1972 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 1973 <&gcc GCC_USB20_MASTER_CLK>, 1974 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1975 <&gcc GCC_USB20_SLEEP_CLK>, 1976 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1977 1978 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1979 <&gcc GCC_USB20_MASTER_CLK>; 1980 assigned-clock-rates = <19200000>, <60000000>; 1981 1982 power-domains = <&gcc USB30_GDSC>; 1983 status = "disabled"; 1984 1985 dwc3@7600000 { 1986 compatible = "snps,dwc3"; 1987 reg = <0x07600000 0xcc00>; 1988 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 1989 phys = <&hsusb_phy2>; 1990 phy-names = "usb2-phy"; 1991 snps,dis_u2_susphy_quirk; 1992 snps,dis_enblslpm_quirk; 1993 }; 1994 }; 1995 1996 slimbam: dma@9184000 { 1997 compatible = "qcom,bam-v1.7.0"; 1998 qcom,controlled-remotely; 1999 reg = <0x09184000 0x32000>; 2000 num-channels = <31>; 2001 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 2002 #dma-cells = <1>; 2003 qcom,ee = <1>; 2004 qcom,num-ees = <2>; 2005 }; 2006 2007 slim_msm: slim@91c0000 { 2008 compatible = "qcom,slim-ngd-v1.5.0"; 2009 reg = <0x091c0000 0x2C000>; 2010 reg-names = "ctrl"; 2011 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 2012 dmas = <&slimbam 3>, <&slimbam 4>, 2013 <&slimbam 5>, <&slimbam 6>; 2014 dma-names = "rx", "tx", "tx2", "rx2"; 2015 #address-cells = <1>; 2016 #size-cells = <0>; 2017 ngd@1 { 2018 reg = <1>; 2019 #address-cells = <1>; 2020 #size-cells = <1>; 2021 2022 tasha_ifd: tas-ifd { 2023 compatible = "slim217,1a0"; 2024 reg = <0 0>; 2025 }; 2026 2027 wcd9335: codec@1{ 2028 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 2029 pinctrl-names = "default"; 2030 2031 compatible = "slim217,1a0"; 2032 reg = <1 0>; 2033 2034 interrupt-parent = <&msmgpio>; 2035 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 2036 <53 IRQ_TYPE_LEVEL_HIGH>; 2037 interrupt-names = "intr1", "intr2"; 2038 interrupt-controller; 2039 #interrupt-cells = <1>; 2040 reset-gpios = <&msmgpio 64 0>; 2041 2042 slim-ifc-dev = <&tasha_ifd>; 2043 2044 #sound-dai-cells = <1>; 2045 }; 2046 }; 2047 }; 2048 2049 adsp_pil: remoteproc@9300000 { 2050 compatible = "qcom,msm8996-adsp-pil"; 2051 reg = <0x09300000 0x80000>; 2052 2053 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 2054 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2055 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2056 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2057 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2058 interrupt-names = "wdog", "fatal", "ready", 2059 "handover", "stop-ack"; 2060 2061 clocks = <&xo_board>; 2062 clock-names = "xo"; 2063 2064 memory-region = <&adsp_region>; 2065 2066 qcom,smem-states = <&smp2p_adsp_out 0>; 2067 qcom,smem-state-names = "stop"; 2068 2069 smd-edge { 2070 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2071 2072 label = "lpass"; 2073 mboxes = <&apcs_glb 8>; 2074 qcom,smd-edge = <1>; 2075 qcom,remote-pid = <2>; 2076 #address-cells = <1>; 2077 #size-cells = <0>; 2078 apr { 2079 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 2080 compatible = "qcom,apr-v2"; 2081 qcom,smd-channels = "apr_audio_svc"; 2082 qcom,apr-domain = <APR_DOMAIN_ADSP>; 2083 #address-cells = <1>; 2084 #size-cells = <0>; 2085 2086 q6core { 2087 reg = <APR_SVC_ADSP_CORE>; 2088 compatible = "qcom,q6core"; 2089 }; 2090 2091 q6afe: q6afe { 2092 compatible = "qcom,q6afe"; 2093 reg = <APR_SVC_AFE>; 2094 q6afedai: dais { 2095 compatible = "qcom,q6afe-dais"; 2096 #address-cells = <1>; 2097 #size-cells = <0>; 2098 #sound-dai-cells = <1>; 2099 hdmi@1 { 2100 reg = <1>; 2101 }; 2102 }; 2103 }; 2104 2105 q6asm: q6asm { 2106 compatible = "qcom,q6asm"; 2107 reg = <APR_SVC_ASM>; 2108 q6asmdai: dais { 2109 compatible = "qcom,q6asm-dais"; 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 #sound-dai-cells = <1>; 2113 iommus = <&lpass_q6_smmu 1>; 2114 }; 2115 }; 2116 2117 q6adm: q6adm { 2118 compatible = "qcom,q6adm"; 2119 reg = <APR_SVC_ADM>; 2120 q6routing: routing { 2121 compatible = "qcom,q6adm-routing"; 2122 #sound-dai-cells = <0>; 2123 }; 2124 }; 2125 }; 2126 2127 }; 2128 }; 2129 2130 apcs_glb: mailbox@9820000 { 2131 compatible = "qcom,msm8996-apcs-hmss-global"; 2132 reg = <0x09820000 0x1000>; 2133 2134 #mbox-cells = <1>; 2135 }; 2136 2137 timer@9840000 { 2138 #address-cells = <1>; 2139 #size-cells = <1>; 2140 ranges; 2141 compatible = "arm,armv7-timer-mem"; 2142 reg = <0x09840000 0x1000>; 2143 clock-frequency = <19200000>; 2144 2145 frame@9850000 { 2146 frame-number = <0>; 2147 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2149 reg = <0x09850000 0x1000>, 2150 <0x09860000 0x1000>; 2151 }; 2152 2153 frame@9870000 { 2154 frame-number = <1>; 2155 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 2156 reg = <0x09870000 0x1000>; 2157 status = "disabled"; 2158 }; 2159 2160 frame@9880000 { 2161 frame-number = <2>; 2162 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2163 reg = <0x09880000 0x1000>; 2164 status = "disabled"; 2165 }; 2166 2167 frame@9890000 { 2168 frame-number = <3>; 2169 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2170 reg = <0x09890000 0x1000>; 2171 status = "disabled"; 2172 }; 2173 2174 frame@98a0000 { 2175 frame-number = <4>; 2176 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2177 reg = <0x098a0000 0x1000>; 2178 status = "disabled"; 2179 }; 2180 2181 frame@98b0000 { 2182 frame-number = <5>; 2183 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2184 reg = <0x098b0000 0x1000>; 2185 status = "disabled"; 2186 }; 2187 2188 frame@98c0000 { 2189 frame-number = <6>; 2190 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2191 reg = <0x098c0000 0x1000>; 2192 status = "disabled"; 2193 }; 2194 }; 2195 2196 saw3: syscon@9a10000 { 2197 compatible = "syscon"; 2198 reg = <0x09a10000 0x1000>; 2199 }; 2200 2201 intc: interrupt-controller@9bc0000 { 2202 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 2203 #interrupt-cells = <3>; 2204 interrupt-controller; 2205 #redistributor-regions = <1>; 2206 redistributor-stride = <0x0 0x40000>; 2207 reg = <0x09bc0000 0x10000>, 2208 <0x09c00000 0x100000>; 2209 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2210 }; 2211 }; 2212 2213 sound: sound { 2214 }; 2215 2216 thermal-zones { 2217 cpu0-thermal { 2218 polling-delay-passive = <250>; 2219 polling-delay = <1000>; 2220 2221 thermal-sensors = <&tsens0 3>; 2222 2223 trips { 2224 cpu0_alert0: trip-point0 { 2225 temperature = <75000>; 2226 hysteresis = <2000>; 2227 type = "passive"; 2228 }; 2229 2230 cpu0_crit: cpu_crit { 2231 temperature = <110000>; 2232 hysteresis = <2000>; 2233 type = "critical"; 2234 }; 2235 }; 2236 }; 2237 2238 cpu1-thermal { 2239 polling-delay-passive = <250>; 2240 polling-delay = <1000>; 2241 2242 thermal-sensors = <&tsens0 5>; 2243 2244 trips { 2245 cpu1_alert0: trip-point0 { 2246 temperature = <75000>; 2247 hysteresis = <2000>; 2248 type = "passive"; 2249 }; 2250 2251 cpu1_crit: cpu_crit { 2252 temperature = <110000>; 2253 hysteresis = <2000>; 2254 type = "critical"; 2255 }; 2256 }; 2257 }; 2258 2259 cpu2-thermal { 2260 polling-delay-passive = <250>; 2261 polling-delay = <1000>; 2262 2263 thermal-sensors = <&tsens0 8>; 2264 2265 trips { 2266 cpu2_alert0: trip-point0 { 2267 temperature = <75000>; 2268 hysteresis = <2000>; 2269 type = "passive"; 2270 }; 2271 2272 cpu2_crit: cpu_crit { 2273 temperature = <110000>; 2274 hysteresis = <2000>; 2275 type = "critical"; 2276 }; 2277 }; 2278 }; 2279 2280 cpu3-thermal { 2281 polling-delay-passive = <250>; 2282 polling-delay = <1000>; 2283 2284 thermal-sensors = <&tsens0 10>; 2285 2286 trips { 2287 cpu3_alert0: trip-point0 { 2288 temperature = <75000>; 2289 hysteresis = <2000>; 2290 type = "passive"; 2291 }; 2292 2293 cpu3_crit: cpu_crit { 2294 temperature = <110000>; 2295 hysteresis = <2000>; 2296 type = "critical"; 2297 }; 2298 }; 2299 }; 2300 2301 gpu-thermal-top { 2302 polling-delay-passive = <250>; 2303 polling-delay = <1000>; 2304 2305 thermal-sensors = <&tsens1 6>; 2306 2307 trips { 2308 gpu1_alert0: trip-point0 { 2309 temperature = <90000>; 2310 hysteresis = <2000>; 2311 type = "hot"; 2312 }; 2313 }; 2314 }; 2315 2316 gpu-thermal-bottom { 2317 polling-delay-passive = <250>; 2318 polling-delay = <1000>; 2319 2320 thermal-sensors = <&tsens1 7>; 2321 2322 trips { 2323 gpu2_alert0: trip-point0 { 2324 temperature = <90000>; 2325 hysteresis = <2000>; 2326 type = "hot"; 2327 }; 2328 }; 2329 }; 2330 2331 m4m-thermal { 2332 polling-delay-passive = <250>; 2333 polling-delay = <1000>; 2334 2335 thermal-sensors = <&tsens0 1>; 2336 2337 trips { 2338 m4m_alert0: trip-point0 { 2339 temperature = <90000>; 2340 hysteresis = <2000>; 2341 type = "hot"; 2342 }; 2343 }; 2344 }; 2345 2346 l3-or-venus-thermal { 2347 polling-delay-passive = <250>; 2348 polling-delay = <1000>; 2349 2350 thermal-sensors = <&tsens0 2>; 2351 2352 trips { 2353 l3_or_venus_alert0: trip-point0 { 2354 temperature = <90000>; 2355 hysteresis = <2000>; 2356 type = "hot"; 2357 }; 2358 }; 2359 }; 2360 2361 cluster0-l2-thermal { 2362 polling-delay-passive = <250>; 2363 polling-delay = <1000>; 2364 2365 thermal-sensors = <&tsens0 7>; 2366 2367 trips { 2368 cluster0_l2_alert0: trip-point0 { 2369 temperature = <90000>; 2370 hysteresis = <2000>; 2371 type = "hot"; 2372 }; 2373 }; 2374 }; 2375 2376 cluster1-l2-thermal { 2377 polling-delay-passive = <250>; 2378 polling-delay = <1000>; 2379 2380 thermal-sensors = <&tsens0 12>; 2381 2382 trips { 2383 cluster1_l2_alert0: trip-point0 { 2384 temperature = <90000>; 2385 hysteresis = <2000>; 2386 type = "hot"; 2387 }; 2388 }; 2389 }; 2390 2391 camera-thermal { 2392 polling-delay-passive = <250>; 2393 polling-delay = <1000>; 2394 2395 thermal-sensors = <&tsens1 1>; 2396 2397 trips { 2398 camera_alert0: trip-point0 { 2399 temperature = <90000>; 2400 hysteresis = <2000>; 2401 type = "hot"; 2402 }; 2403 }; 2404 }; 2405 2406 q6-dsp-thermal { 2407 polling-delay-passive = <250>; 2408 polling-delay = <1000>; 2409 2410 thermal-sensors = <&tsens1 2>; 2411 2412 trips { 2413 q6_dsp_alert0: trip-point0 { 2414 temperature = <90000>; 2415 hysteresis = <2000>; 2416 type = "hot"; 2417 }; 2418 }; 2419 }; 2420 2421 mem-thermal { 2422 polling-delay-passive = <250>; 2423 polling-delay = <1000>; 2424 2425 thermal-sensors = <&tsens1 3>; 2426 2427 trips { 2428 mem_alert0: trip-point0 { 2429 temperature = <90000>; 2430 hysteresis = <2000>; 2431 type = "hot"; 2432 }; 2433 }; 2434 }; 2435 2436 modemtx-thermal { 2437 polling-delay-passive = <250>; 2438 polling-delay = <1000>; 2439 2440 thermal-sensors = <&tsens1 4>; 2441 2442 trips { 2443 modemtx_alert0: trip-point0 { 2444 temperature = <90000>; 2445 hysteresis = <2000>; 2446 type = "hot"; 2447 }; 2448 }; 2449 }; 2450 }; 2451 2452 timer { 2453 compatible = "arm,armv8-timer"; 2454 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2455 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2456 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2457 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2458 }; 2459}; 2460#include "msm8996-pins.dtsi" 2461