1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
34
35 #include "core.h"
36 #include "gadget.h"
37 #include "io.h"
38
39 #include "debug.h"
40
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43 /**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
dwc3_get_dr_mode(struct dwc3 * dwc)47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
48 {
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103 }
104
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
106 {
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 dwc->current_dr_role = mode;
115 }
116
__dwc3_set_mode(struct work_struct * work)117 static void __dwc3_set_mode(struct work_struct *work)
118 {
119 struct dwc3 *dwc = work_to_dwc(work);
120 unsigned long flags;
121 int ret;
122 u32 reg;
123 u32 desired_dr_role;
124
125 mutex_lock(&dwc->mutex);
126 spin_lock_irqsave(&dwc->lock, flags);
127 desired_dr_role = dwc->desired_dr_role;
128 spin_unlock_irqrestore(&dwc->lock, flags);
129
130 pm_runtime_get_sync(dwc->dev);
131
132 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
133 dwc3_otg_update(dwc, 0);
134
135 if (!desired_dr_role)
136 goto out;
137
138 if (desired_dr_role == dwc->current_dr_role)
139 goto out;
140
141 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
142 goto out;
143
144 switch (dwc->current_dr_role) {
145 case DWC3_GCTL_PRTCAP_HOST:
146 dwc3_host_exit(dwc);
147 break;
148 case DWC3_GCTL_PRTCAP_DEVICE:
149 dwc3_gadget_exit(dwc);
150 dwc3_event_buffers_cleanup(dwc);
151 break;
152 case DWC3_GCTL_PRTCAP_OTG:
153 dwc3_otg_exit(dwc);
154 spin_lock_irqsave(&dwc->lock, flags);
155 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
156 spin_unlock_irqrestore(&dwc->lock, flags);
157 dwc3_otg_update(dwc, 1);
158 break;
159 default:
160 break;
161 }
162
163 /*
164 * When current_dr_role is not set, there's no role switching.
165 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
166 */
167 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
168 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
169 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
170 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
171 reg |= DWC3_GCTL_CORESOFTRESET;
172 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
173
174 /*
175 * Wait for internal clocks to synchronized. DWC_usb31 and
176 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
177 * keep it consistent across different IPs, let's wait up to
178 * 100ms before clearing GCTL.CORESOFTRESET.
179 */
180 msleep(100);
181
182 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
183 reg &= ~DWC3_GCTL_CORESOFTRESET;
184 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
185 }
186
187 spin_lock_irqsave(&dwc->lock, flags);
188
189 dwc3_set_prtcap(dwc, desired_dr_role);
190
191 spin_unlock_irqrestore(&dwc->lock, flags);
192
193 switch (desired_dr_role) {
194 case DWC3_GCTL_PRTCAP_HOST:
195 ret = dwc3_host_init(dwc);
196 if (ret) {
197 dev_err(dwc->dev, "failed to initialize host\n");
198 } else {
199 if (dwc->usb2_phy)
200 otg_set_vbus(dwc->usb2_phy->otg, true);
201 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
202 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
203 if (dwc->dis_split_quirk) {
204 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
205 reg |= DWC3_GUCTL3_SPLITDISABLE;
206 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
207 }
208 }
209 break;
210 case DWC3_GCTL_PRTCAP_DEVICE:
211 dwc3_core_soft_reset(dwc);
212
213 dwc3_event_buffers_setup(dwc);
214
215 if (dwc->usb2_phy)
216 otg_set_vbus(dwc->usb2_phy->otg, false);
217 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
218 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
219
220 ret = dwc3_gadget_init(dwc);
221 if (ret)
222 dev_err(dwc->dev, "failed to initialize peripheral\n");
223 break;
224 case DWC3_GCTL_PRTCAP_OTG:
225 dwc3_otg_init(dwc);
226 dwc3_otg_update(dwc, 0);
227 break;
228 default:
229 break;
230 }
231
232 out:
233 pm_runtime_mark_last_busy(dwc->dev);
234 pm_runtime_put_autosuspend(dwc->dev);
235 mutex_unlock(&dwc->mutex);
236 }
237
dwc3_set_mode(struct dwc3 * dwc,u32 mode)238 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
239 {
240 unsigned long flags;
241
242 if (dwc->dr_mode != USB_DR_MODE_OTG)
243 return;
244
245 spin_lock_irqsave(&dwc->lock, flags);
246 dwc->desired_dr_role = mode;
247 spin_unlock_irqrestore(&dwc->lock, flags);
248
249 queue_work(system_freezable_wq, &dwc->drd_work);
250 }
251
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)252 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
253 {
254 struct dwc3 *dwc = dep->dwc;
255 u32 reg;
256
257 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
258 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
259 DWC3_GDBGFIFOSPACE_TYPE(type));
260
261 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
262
263 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
264 }
265
266 /**
267 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
268 * @dwc: pointer to our context structure
269 */
dwc3_core_soft_reset(struct dwc3 * dwc)270 int dwc3_core_soft_reset(struct dwc3 *dwc)
271 {
272 u32 reg;
273 int retries = 1000;
274
275 /*
276 * We're resetting only the device side because, if we're in host mode,
277 * XHCI driver will reset the host block. If dwc3 was configured for
278 * host-only mode or current role is host, then we can return early.
279 */
280 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
281 return 0;
282
283 /*
284 * If the dr_mode is host and the dwc->current_dr_role is not the
285 * corresponding DWC3_GCTL_PRTCAP_HOST, then the dwc3_core_init_mode
286 * isn't executed yet. Ensure the phy is ready before the controller
287 * updates the GCTL.PRTCAPDIR or other settings by soft-resetting
288 * the phy.
289 *
290 * Note: GUSB3PIPECTL[n] and GUSB2PHYCFG[n] are port settings where n
291 * is port index. If this is a multiport host, then we need to reset
292 * all active ports.
293 */
294 if (dwc->dr_mode == USB_DR_MODE_HOST) {
295 u32 usb3_port;
296 u32 usb2_port;
297
298 usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
299 usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
300 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
301
302 usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
303 usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
304 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
305
306 /* Small delay for phy reset assertion */
307 usleep_range(1000, 2000);
308
309 usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
310 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
311
312 usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
313 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
314
315 /* Wait for clock synchronization */
316 msleep(50);
317 return 0;
318 }
319
320 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
321 reg |= DWC3_DCTL_CSFTRST;
322 reg &= ~DWC3_DCTL_RUN_STOP;
323 dwc3_gadget_dctl_write_safe(dwc, reg);
324
325 /*
326 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
327 * is cleared only after all the clocks are synchronized. This can
328 * take a little more than 50ms. Set the polling rate at 20ms
329 * for 10 times instead.
330 */
331 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
332 retries = 10;
333
334 do {
335 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
336 if (!(reg & DWC3_DCTL_CSFTRST))
337 goto done;
338
339 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
340 msleep(20);
341 else
342 udelay(1);
343 } while (--retries);
344
345 return -ETIMEDOUT;
346
347 done:
348 /*
349 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
350 * is cleared, we must wait at least 50ms before accessing the PHY
351 * domain (synchronization delay).
352 */
353 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
354 msleep(50);
355
356 return 0;
357 }
358
359 /*
360 * dwc3_frame_length_adjustment - Adjusts frame length if required
361 * @dwc3: Pointer to our controller context structure
362 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)363 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
364 {
365 u32 reg;
366 u32 dft;
367
368 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
369 return;
370
371 if (dwc->fladj == 0)
372 return;
373
374 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
375 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
376 if (dft != dwc->fladj) {
377 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
378 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
379 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
380 }
381 }
382
383 /**
384 * dwc3_free_one_event_buffer - Frees one event buffer
385 * @dwc: Pointer to our controller context structure
386 * @evt: Pointer to event buffer to be freed
387 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)388 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
389 struct dwc3_event_buffer *evt)
390 {
391 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
392 }
393
394 /**
395 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
396 * @dwc: Pointer to our controller context structure
397 * @length: size of the event buffer
398 *
399 * Returns a pointer to the allocated event buffer structure on success
400 * otherwise ERR_PTR(errno).
401 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)402 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
403 unsigned length)
404 {
405 struct dwc3_event_buffer *evt;
406
407 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
408 if (!evt)
409 return ERR_PTR(-ENOMEM);
410
411 evt->dwc = dwc;
412 evt->length = length;
413 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
414 if (!evt->cache)
415 return ERR_PTR(-ENOMEM);
416
417 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
418 &evt->dma, GFP_KERNEL);
419 if (!evt->buf)
420 return ERR_PTR(-ENOMEM);
421
422 return evt;
423 }
424
425 /**
426 * dwc3_free_event_buffers - frees all allocated event buffers
427 * @dwc: Pointer to our controller context structure
428 */
dwc3_free_event_buffers(struct dwc3 * dwc)429 static void dwc3_free_event_buffers(struct dwc3 *dwc)
430 {
431 struct dwc3_event_buffer *evt;
432
433 evt = dwc->ev_buf;
434 if (evt)
435 dwc3_free_one_event_buffer(dwc, evt);
436 }
437
438 /**
439 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
440 * @dwc: pointer to our controller context structure
441 * @length: size of event buffer
442 *
443 * Returns 0 on success otherwise negative errno. In the error case, dwc
444 * may contain some buffers allocated but not all which were requested.
445 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)446 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
447 {
448 struct dwc3_event_buffer *evt;
449
450 evt = dwc3_alloc_one_event_buffer(dwc, length);
451 if (IS_ERR(evt)) {
452 dev_err(dwc->dev, "can't allocate event buffer\n");
453 return PTR_ERR(evt);
454 }
455 dwc->ev_buf = evt;
456
457 return 0;
458 }
459
460 /**
461 * dwc3_event_buffers_setup - setup our allocated event buffers
462 * @dwc: pointer to our controller context structure
463 *
464 * Returns 0 on success otherwise negative errno.
465 */
dwc3_event_buffers_setup(struct dwc3 * dwc)466 int dwc3_event_buffers_setup(struct dwc3 *dwc)
467 {
468 struct dwc3_event_buffer *evt;
469
470 evt = dwc->ev_buf;
471 evt->lpos = 0;
472 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
473 lower_32_bits(evt->dma));
474 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
475 upper_32_bits(evt->dma));
476 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
477 DWC3_GEVNTSIZ_SIZE(evt->length));
478 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
479
480 return 0;
481 }
482
dwc3_event_buffers_cleanup(struct dwc3 * dwc)483 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
484 {
485 struct dwc3_event_buffer *evt;
486
487 evt = dwc->ev_buf;
488
489 evt->lpos = 0;
490
491 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
492 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
493 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
494 | DWC3_GEVNTSIZ_SIZE(0));
495 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
496 }
497
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)498 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
499 {
500 if (!dwc->has_hibernation)
501 return 0;
502
503 if (!dwc->nr_scratch)
504 return 0;
505
506 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
507 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
508 if (!dwc->scratchbuf)
509 return -ENOMEM;
510
511 return 0;
512 }
513
dwc3_setup_scratch_buffers(struct dwc3 * dwc)514 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
515 {
516 dma_addr_t scratch_addr;
517 u32 param;
518 int ret;
519
520 if (!dwc->has_hibernation)
521 return 0;
522
523 if (!dwc->nr_scratch)
524 return 0;
525
526 /* should never fall here */
527 if (!WARN_ON(dwc->scratchbuf))
528 return 0;
529
530 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
531 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
532 DMA_BIDIRECTIONAL);
533 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
534 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
535 ret = -EFAULT;
536 goto err0;
537 }
538
539 dwc->scratch_addr = scratch_addr;
540
541 param = lower_32_bits(scratch_addr);
542
543 ret = dwc3_send_gadget_generic_command(dwc,
544 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
545 if (ret < 0)
546 goto err1;
547
548 param = upper_32_bits(scratch_addr);
549
550 ret = dwc3_send_gadget_generic_command(dwc,
551 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
552 if (ret < 0)
553 goto err1;
554
555 return 0;
556
557 err1:
558 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
559 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
560
561 err0:
562 return ret;
563 }
564
dwc3_free_scratch_buffers(struct dwc3 * dwc)565 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
566 {
567 if (!dwc->has_hibernation)
568 return;
569
570 if (!dwc->nr_scratch)
571 return;
572
573 /* should never fall here */
574 if (!WARN_ON(dwc->scratchbuf))
575 return;
576
577 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
578 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
579 kfree(dwc->scratchbuf);
580 }
581
dwc3_core_num_eps(struct dwc3 * dwc)582 static void dwc3_core_num_eps(struct dwc3 *dwc)
583 {
584 struct dwc3_hwparams *parms = &dwc->hwparams;
585
586 dwc->num_eps = DWC3_NUM_EPS(parms);
587 }
588
dwc3_cache_hwparams(struct dwc3 * dwc)589 static void dwc3_cache_hwparams(struct dwc3 *dwc)
590 {
591 struct dwc3_hwparams *parms = &dwc->hwparams;
592
593 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
594 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
595 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
596 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
597 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
598 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
599 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
600 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
601 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
602 }
603
dwc3_core_ulpi_init(struct dwc3 * dwc)604 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
605 {
606 int intf;
607 int ret = 0;
608
609 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
610
611 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
612 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
613 dwc->hsphy_interface &&
614 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
615 ret = dwc3_ulpi_init(dwc);
616
617 return ret;
618 }
619
620 /**
621 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
622 * @dwc: Pointer to our controller context structure
623 *
624 * Returns 0 on success. The USB PHY interfaces are configured but not
625 * initialized. The PHY interfaces and the PHYs get initialized together with
626 * the core in dwc3_core_init.
627 */
dwc3_phy_setup(struct dwc3 * dwc)628 static int dwc3_phy_setup(struct dwc3 *dwc)
629 {
630 unsigned int hw_mode;
631 u32 reg;
632
633 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
634
635 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
636
637 /*
638 * Make sure UX_EXIT_PX is cleared as that causes issues with some
639 * PHYs. Also, this bit is not supposed to be used in normal operation.
640 */
641 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
642
643 /*
644 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
645 * to '0' during coreConsultant configuration. So default value
646 * will be '0' when the core is reset. Application needs to set it
647 * to '1' after the core initialization is completed.
648 */
649 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
650 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
651
652 /*
653 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
654 * power-on reset, and it can be set after core initialization, which is
655 * after device soft-reset during initialization.
656 */
657 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
658 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
659
660 if (dwc->u2ss_inp3_quirk)
661 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
662
663 if (dwc->dis_rxdet_inp3_quirk)
664 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
665
666 if (dwc->req_p1p2p3_quirk)
667 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
668
669 if (dwc->del_p1p2p3_quirk)
670 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
671
672 if (dwc->del_phy_power_chg_quirk)
673 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
674
675 if (dwc->lfps_filter_quirk)
676 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
677
678 if (dwc->rx_detect_poll_quirk)
679 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
680
681 if (dwc->tx_de_emphasis_quirk)
682 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
683
684 if (dwc->dis_u3_susphy_quirk)
685 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
686
687 if (dwc->dis_del_phy_power_chg_quirk)
688 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
689
690 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
691
692 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
693
694 /* Select the HS PHY interface */
695 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
696 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
697 if (dwc->hsphy_interface &&
698 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
699 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
700 break;
701 } else if (dwc->hsphy_interface &&
702 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
703 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
704 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
705 } else {
706 /* Relying on default value. */
707 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
708 break;
709 }
710 fallthrough;
711 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
712 default:
713 break;
714 }
715
716 switch (dwc->hsphy_mode) {
717 case USBPHY_INTERFACE_MODE_UTMI:
718 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
719 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
720 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
721 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
722 break;
723 case USBPHY_INTERFACE_MODE_UTMIW:
724 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
725 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
726 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
727 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
728 break;
729 default:
730 break;
731 }
732
733 /*
734 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
735 * '0' during coreConsultant configuration. So default value will
736 * be '0' when the core is reset. Application needs to set it to
737 * '1' after the core initialization is completed.
738 */
739 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
740 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
741
742 /*
743 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
744 * power-on reset, and it can be set after core initialization, which is
745 * after device soft-reset during initialization.
746 */
747 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
748 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
749
750 if (dwc->dis_u2_susphy_quirk)
751 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
752
753 if (dwc->dis_enblslpm_quirk)
754 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
755 else
756 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
757
758 if (dwc->dis_u2_freeclk_exists_quirk)
759 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
760
761 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
762
763 return 0;
764 }
765
dwc3_core_exit(struct dwc3 * dwc)766 static void dwc3_core_exit(struct dwc3 *dwc)
767 {
768 dwc3_event_buffers_cleanup(dwc);
769
770 usb_phy_set_suspend(dwc->usb2_phy, 1);
771 usb_phy_set_suspend(dwc->usb3_phy, 1);
772 phy_power_off(dwc->usb2_generic_phy);
773 phy_power_off(dwc->usb3_generic_phy);
774
775 usb_phy_shutdown(dwc->usb2_phy);
776 usb_phy_shutdown(dwc->usb3_phy);
777 phy_exit(dwc->usb2_generic_phy);
778 phy_exit(dwc->usb3_generic_phy);
779
780 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
781 reset_control_assert(dwc->reset);
782 }
783
dwc3_core_is_valid(struct dwc3 * dwc)784 static bool dwc3_core_is_valid(struct dwc3 *dwc)
785 {
786 u32 reg;
787
788 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
789 dwc->ip = DWC3_GSNPS_ID(reg);
790
791 /* This should read as U3 followed by revision number */
792 if (DWC3_IP_IS(DWC3)) {
793 dwc->revision = reg;
794 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
795 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
796 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
797 } else {
798 return false;
799 }
800
801 return true;
802 }
803
dwc3_core_setup_global_control(struct dwc3 * dwc)804 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
805 {
806 u32 hwparams4 = dwc->hwparams.hwparams4;
807 u32 reg;
808
809 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
810 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
811
812 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
813 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
814 /**
815 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
816 * issue which would cause xHCI compliance tests to fail.
817 *
818 * Because of that we cannot enable clock gating on such
819 * configurations.
820 *
821 * Refers to:
822 *
823 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
824 * SOF/ITP Mode Used
825 */
826 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
827 dwc->dr_mode == USB_DR_MODE_OTG) &&
828 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
829 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
830 else
831 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
832 break;
833 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
834 /* enable hibernation here */
835 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
836
837 /*
838 * REVISIT Enabling this bit so that host-mode hibernation
839 * will work. Device-mode hibernation is not yet implemented.
840 */
841 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
842 break;
843 default:
844 /* nothing */
845 break;
846 }
847
848 /* check if current dwc3 is on simulation board */
849 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
850 dev_info(dwc->dev, "Running with FPGA optimizations\n");
851 dwc->is_fpga = true;
852 }
853
854 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
855 "disable_scramble cannot be used on non-FPGA builds\n");
856
857 if (dwc->disable_scramble_quirk && dwc->is_fpga)
858 reg |= DWC3_GCTL_DISSCRAMBLE;
859 else
860 reg &= ~DWC3_GCTL_DISSCRAMBLE;
861
862 if (dwc->u2exit_lfps_quirk)
863 reg |= DWC3_GCTL_U2EXIT_LFPS;
864
865 /*
866 * WORKAROUND: DWC3 revisions <1.90a have a bug
867 * where the device can fail to connect at SuperSpeed
868 * and falls back to high-speed mode which causes
869 * the device to enter a Connect/Disconnect loop
870 */
871 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
872 reg |= DWC3_GCTL_U2RSTECN;
873
874 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
875 }
876
877 static int dwc3_core_get_phy(struct dwc3 *dwc);
878 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
879
880 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)881 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
882 {
883 struct device *dev = dwc->dev;
884 /* incrx_mode : for INCR burst type. */
885 bool incrx_mode;
886 /* incrx_size : for size of INCRX burst. */
887 u32 incrx_size;
888 u32 *vals;
889 u32 cfg;
890 int ntype;
891 int ret;
892 int i;
893
894 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
895
896 /*
897 * Handle property "snps,incr-burst-type-adjustment".
898 * Get the number of value from this property:
899 * result <= 0, means this property is not supported.
900 * result = 1, means INCRx burst mode supported.
901 * result > 1, means undefined length burst mode supported.
902 */
903 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
904 if (ntype <= 0)
905 return;
906
907 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
908 if (!vals) {
909 dev_err(dev, "Error to get memory\n");
910 return;
911 }
912
913 /* Get INCR burst type, and parse it */
914 ret = device_property_read_u32_array(dev,
915 "snps,incr-burst-type-adjustment", vals, ntype);
916 if (ret) {
917 kfree(vals);
918 dev_err(dev, "Error to get property\n");
919 return;
920 }
921
922 incrx_size = *vals;
923
924 if (ntype > 1) {
925 /* INCRX (undefined length) burst mode */
926 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
927 for (i = 1; i < ntype; i++) {
928 if (vals[i] > incrx_size)
929 incrx_size = vals[i];
930 }
931 } else {
932 /* INCRX burst mode */
933 incrx_mode = INCRX_BURST_MODE;
934 }
935
936 kfree(vals);
937
938 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
939 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
940 if (incrx_mode)
941 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
942 switch (incrx_size) {
943 case 256:
944 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
945 break;
946 case 128:
947 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
948 break;
949 case 64:
950 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
951 break;
952 case 32:
953 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
954 break;
955 case 16:
956 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
957 break;
958 case 8:
959 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
960 break;
961 case 4:
962 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
963 break;
964 case 1:
965 break;
966 default:
967 dev_err(dev, "Invalid property\n");
968 break;
969 }
970
971 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
972 }
973
974 /**
975 * dwc3_core_init - Low-level initialization of DWC3 Core
976 * @dwc: Pointer to our controller context structure
977 *
978 * Returns 0 on success otherwise negative errno.
979 */
dwc3_core_init(struct dwc3 * dwc)980 static int dwc3_core_init(struct dwc3 *dwc)
981 {
982 unsigned int hw_mode;
983 u32 reg;
984 int ret;
985
986 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
987
988 /*
989 * Write Linux Version Code to our GUID register so it's easy to figure
990 * out which kernel version a bug was found.
991 */
992 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
993
994 ret = dwc3_phy_setup(dwc);
995 if (ret)
996 goto err0;
997
998 if (!dwc->ulpi_ready) {
999 ret = dwc3_core_ulpi_init(dwc);
1000 if (ret) {
1001 if (ret == -ETIMEDOUT) {
1002 dwc3_core_soft_reset(dwc);
1003 ret = -EPROBE_DEFER;
1004 }
1005 goto err0;
1006 }
1007 dwc->ulpi_ready = true;
1008 }
1009
1010 if (!dwc->phys_ready) {
1011 ret = dwc3_core_get_phy(dwc);
1012 if (ret)
1013 goto err0a;
1014 dwc->phys_ready = true;
1015 }
1016
1017 usb_phy_init(dwc->usb2_phy);
1018 usb_phy_init(dwc->usb3_phy);
1019 ret = phy_init(dwc->usb2_generic_phy);
1020 if (ret < 0)
1021 goto err0a;
1022
1023 ret = phy_init(dwc->usb3_generic_phy);
1024 if (ret < 0) {
1025 phy_exit(dwc->usb2_generic_phy);
1026 goto err0a;
1027 }
1028
1029 ret = dwc3_core_soft_reset(dwc);
1030 if (ret)
1031 goto err1;
1032
1033 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1034 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1035 if (!dwc->dis_u3_susphy_quirk) {
1036 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1037 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1038 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1039 }
1040
1041 if (!dwc->dis_u2_susphy_quirk) {
1042 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1043 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1044 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1045 }
1046 }
1047
1048 dwc3_core_setup_global_control(dwc);
1049 dwc3_core_num_eps(dwc);
1050
1051 ret = dwc3_setup_scratch_buffers(dwc);
1052 if (ret)
1053 goto err1;
1054
1055 /* Adjust Frame Length */
1056 dwc3_frame_length_adjustment(dwc);
1057
1058 dwc3_set_incr_burst_type(dwc);
1059
1060 usb_phy_set_suspend(dwc->usb2_phy, 0);
1061 usb_phy_set_suspend(dwc->usb3_phy, 0);
1062 ret = phy_power_on(dwc->usb2_generic_phy);
1063 if (ret < 0)
1064 goto err2;
1065
1066 ret = phy_power_on(dwc->usb3_generic_phy);
1067 if (ret < 0)
1068 goto err3;
1069
1070 ret = dwc3_event_buffers_setup(dwc);
1071 if (ret) {
1072 dev_err(dwc->dev, "failed to setup event buffers\n");
1073 goto err4;
1074 }
1075
1076 /*
1077 * ENDXFER polling is available on version 3.10a and later of
1078 * the DWC_usb3 controller. It is NOT available in the
1079 * DWC_usb31 controller.
1080 */
1081 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1082 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1083 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1084 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1085 }
1086
1087 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1088 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1089
1090 /*
1091 * Enable hardware control of sending remote wakeup
1092 * in HS when the device is in the L1 state.
1093 */
1094 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1095 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1096
1097 if (dwc->dis_tx_ipgap_linecheck_quirk)
1098 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1099
1100 if (dwc->parkmode_disable_ss_quirk)
1101 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1102
1103 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1104 }
1105
1106 /*
1107 * Must config both number of packets and max burst settings to enable
1108 * RX and/or TX threshold.
1109 */
1110 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1111 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1112 u8 rx_maxburst = dwc->rx_max_burst_prd;
1113 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1114 u8 tx_maxburst = dwc->tx_max_burst_prd;
1115
1116 if (rx_thr_num && rx_maxburst) {
1117 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1118 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1119
1120 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1121 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1122
1123 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1124 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1125
1126 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1127 }
1128
1129 if (tx_thr_num && tx_maxburst) {
1130 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1131 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1132
1133 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1134 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1135
1136 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1137 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1138
1139 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1140 }
1141 }
1142
1143 return 0;
1144
1145 err4:
1146 phy_power_off(dwc->usb3_generic_phy);
1147
1148 err3:
1149 phy_power_off(dwc->usb2_generic_phy);
1150
1151 err2:
1152 usb_phy_set_suspend(dwc->usb2_phy, 1);
1153 usb_phy_set_suspend(dwc->usb3_phy, 1);
1154
1155 err1:
1156 usb_phy_shutdown(dwc->usb2_phy);
1157 usb_phy_shutdown(dwc->usb3_phy);
1158 phy_exit(dwc->usb2_generic_phy);
1159 phy_exit(dwc->usb3_generic_phy);
1160
1161 err0a:
1162 dwc3_ulpi_exit(dwc);
1163
1164 err0:
1165 return ret;
1166 }
1167
dwc3_core_get_phy(struct dwc3 * dwc)1168 static int dwc3_core_get_phy(struct dwc3 *dwc)
1169 {
1170 struct device *dev = dwc->dev;
1171 struct device_node *node = dev->of_node;
1172 int ret;
1173
1174 if (node) {
1175 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1176 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1177 } else {
1178 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1179 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1180 }
1181
1182 if (IS_ERR(dwc->usb2_phy)) {
1183 ret = PTR_ERR(dwc->usb2_phy);
1184 if (ret == -ENXIO || ret == -ENODEV) {
1185 dwc->usb2_phy = NULL;
1186 } else if (ret == -EPROBE_DEFER) {
1187 return ret;
1188 } else {
1189 dev_err(dev, "no usb2 phy configured\n");
1190 return ret;
1191 }
1192 }
1193
1194 if (IS_ERR(dwc->usb3_phy)) {
1195 ret = PTR_ERR(dwc->usb3_phy);
1196 if (ret == -ENXIO || ret == -ENODEV) {
1197 dwc->usb3_phy = NULL;
1198 } else if (ret == -EPROBE_DEFER) {
1199 return ret;
1200 } else {
1201 dev_err(dev, "no usb3 phy configured\n");
1202 return ret;
1203 }
1204 }
1205
1206 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1207 if (IS_ERR(dwc->usb2_generic_phy)) {
1208 ret = PTR_ERR(dwc->usb2_generic_phy);
1209 if (ret == -ENOSYS || ret == -ENODEV) {
1210 dwc->usb2_generic_phy = NULL;
1211 } else if (ret == -EPROBE_DEFER) {
1212 return ret;
1213 } else {
1214 dev_err(dev, "no usb2 phy configured\n");
1215 return ret;
1216 }
1217 }
1218
1219 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1220 if (IS_ERR(dwc->usb3_generic_phy)) {
1221 ret = PTR_ERR(dwc->usb3_generic_phy);
1222 if (ret == -ENOSYS || ret == -ENODEV) {
1223 dwc->usb3_generic_phy = NULL;
1224 } else if (ret == -EPROBE_DEFER) {
1225 return ret;
1226 } else {
1227 dev_err(dev, "no usb3 phy configured\n");
1228 return ret;
1229 }
1230 }
1231
1232 return 0;
1233 }
1234
dwc3_core_init_mode(struct dwc3 * dwc)1235 static int dwc3_core_init_mode(struct dwc3 *dwc)
1236 {
1237 struct device *dev = dwc->dev;
1238 int ret;
1239
1240 switch (dwc->dr_mode) {
1241 case USB_DR_MODE_PERIPHERAL:
1242 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1243
1244 if (dwc->usb2_phy)
1245 otg_set_vbus(dwc->usb2_phy->otg, false);
1246 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1247 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1248
1249 ret = dwc3_gadget_init(dwc);
1250 if (ret) {
1251 if (ret != -EPROBE_DEFER)
1252 dev_err(dev, "failed to initialize gadget\n");
1253 return ret;
1254 }
1255 break;
1256 case USB_DR_MODE_HOST:
1257 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1258
1259 if (dwc->usb2_phy)
1260 otg_set_vbus(dwc->usb2_phy->otg, true);
1261 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1262 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1263
1264 ret = dwc3_host_init(dwc);
1265 if (ret) {
1266 if (ret != -EPROBE_DEFER)
1267 dev_err(dev, "failed to initialize host\n");
1268 return ret;
1269 }
1270 break;
1271 case USB_DR_MODE_OTG:
1272 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1273 ret = dwc3_drd_init(dwc);
1274 if (ret) {
1275 if (ret != -EPROBE_DEFER)
1276 dev_err(dev, "failed to initialize dual-role\n");
1277 return ret;
1278 }
1279 break;
1280 default:
1281 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1282 return -EINVAL;
1283 }
1284
1285 return 0;
1286 }
1287
dwc3_core_exit_mode(struct dwc3 * dwc)1288 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1289 {
1290 switch (dwc->dr_mode) {
1291 case USB_DR_MODE_PERIPHERAL:
1292 dwc3_gadget_exit(dwc);
1293 break;
1294 case USB_DR_MODE_HOST:
1295 dwc3_host_exit(dwc);
1296 break;
1297 case USB_DR_MODE_OTG:
1298 dwc3_drd_exit(dwc);
1299 break;
1300 default:
1301 /* do nothing */
1302 break;
1303 }
1304
1305 /* de-assert DRVVBUS for HOST and OTG mode */
1306 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1307 }
1308
dwc3_get_properties(struct dwc3 * dwc)1309 static void dwc3_get_properties(struct dwc3 *dwc)
1310 {
1311 struct device *dev = dwc->dev;
1312 u8 lpm_nyet_threshold;
1313 u8 tx_de_emphasis;
1314 u8 hird_threshold;
1315 u8 rx_thr_num_pkt_prd = 0;
1316 u8 rx_max_burst_prd = 0;
1317 u8 tx_thr_num_pkt_prd = 0;
1318 u8 tx_max_burst_prd = 0;
1319
1320 /* default to highest possible threshold */
1321 lpm_nyet_threshold = 0xf;
1322
1323 /* default to -3.5dB de-emphasis */
1324 tx_de_emphasis = 1;
1325
1326 /*
1327 * default to assert utmi_sleep_n and use maximum allowed HIRD
1328 * threshold value of 0b1100
1329 */
1330 hird_threshold = 12;
1331
1332 dwc->maximum_speed = usb_get_maximum_speed(dev);
1333 dwc->dr_mode = usb_get_dr_mode(dev);
1334 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1335
1336 dwc->sysdev_is_parent = device_property_read_bool(dev,
1337 "linux,sysdev_is_parent");
1338 if (dwc->sysdev_is_parent)
1339 dwc->sysdev = dwc->dev->parent;
1340 else
1341 dwc->sysdev = dwc->dev;
1342
1343 dwc->has_lpm_erratum = device_property_read_bool(dev,
1344 "snps,has-lpm-erratum");
1345 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1346 &lpm_nyet_threshold);
1347 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1348 "snps,is-utmi-l1-suspend");
1349 device_property_read_u8(dev, "snps,hird-threshold",
1350 &hird_threshold);
1351 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1352 "snps,dis-start-transfer-quirk");
1353 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1354 "snps,usb3_lpm_capable");
1355 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1356 "snps,usb2-lpm-disable");
1357 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1358 "snps,usb2-gadget-lpm-disable");
1359 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1360 &rx_thr_num_pkt_prd);
1361 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1362 &rx_max_burst_prd);
1363 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1364 &tx_thr_num_pkt_prd);
1365 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1366 &tx_max_burst_prd);
1367
1368 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1369 "snps,disable_scramble_quirk");
1370 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1371 "snps,u2exit_lfps_quirk");
1372 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1373 "snps,u2ss_inp3_quirk");
1374 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1375 "snps,req_p1p2p3_quirk");
1376 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1377 "snps,del_p1p2p3_quirk");
1378 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1379 "snps,del_phy_power_chg_quirk");
1380 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1381 "snps,lfps_filter_quirk");
1382 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1383 "snps,rx_detect_poll_quirk");
1384 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1385 "snps,dis_u3_susphy_quirk");
1386 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1387 "snps,dis_u2_susphy_quirk");
1388 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1389 "snps,dis_enblslpm_quirk");
1390 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1391 "snps,dis-u1-entry-quirk");
1392 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1393 "snps,dis-u2-entry-quirk");
1394 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1395 "snps,dis_rxdet_inp3_quirk");
1396 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1397 "snps,dis-u2-freeclk-exists-quirk");
1398 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1399 "snps,dis-del-phy-power-chg-quirk");
1400 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1401 "snps,dis-tx-ipgap-linecheck-quirk");
1402 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1403 "snps,parkmode-disable-ss-quirk");
1404
1405 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1406 "snps,tx_de_emphasis_quirk");
1407 device_property_read_u8(dev, "snps,tx_de_emphasis",
1408 &tx_de_emphasis);
1409 device_property_read_string(dev, "snps,hsphy_interface",
1410 &dwc->hsphy_interface);
1411 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1412 &dwc->fladj);
1413
1414 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1415 "snps,dis_metastability_quirk");
1416
1417 dwc->dis_split_quirk = device_property_read_bool(dev,
1418 "snps,dis-split-quirk");
1419
1420 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1421 dwc->tx_de_emphasis = tx_de_emphasis;
1422
1423 dwc->hird_threshold = hird_threshold;
1424
1425 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1426 dwc->rx_max_burst_prd = rx_max_burst_prd;
1427
1428 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1429 dwc->tx_max_burst_prd = tx_max_burst_prd;
1430
1431 dwc->imod_interval = 0;
1432 }
1433
1434 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1435 bool dwc3_has_imod(struct dwc3 *dwc)
1436 {
1437 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1438 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1439 DWC3_IP_IS(DWC32);
1440 }
1441
dwc3_check_params(struct dwc3 * dwc)1442 static void dwc3_check_params(struct dwc3 *dwc)
1443 {
1444 struct device *dev = dwc->dev;
1445 unsigned int hwparam_gen =
1446 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1447
1448 /* Check for proper value of imod_interval */
1449 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1450 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1451 dwc->imod_interval = 0;
1452 }
1453
1454 /*
1455 * Workaround for STAR 9000961433 which affects only version
1456 * 3.00a of the DWC_usb3 core. This prevents the controller
1457 * interrupt from being masked while handling events. IMOD
1458 * allows us to work around this issue. Enable it for the
1459 * affected version.
1460 */
1461 if (!dwc->imod_interval &&
1462 DWC3_VER_IS(DWC3, 300A))
1463 dwc->imod_interval = 1;
1464
1465 /* Check the maximum_speed parameter */
1466 switch (dwc->maximum_speed) {
1467 case USB_SPEED_LOW:
1468 case USB_SPEED_FULL:
1469 case USB_SPEED_HIGH:
1470 break;
1471 case USB_SPEED_SUPER:
1472 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1473 dev_warn(dev, "UDC doesn't support Gen 1\n");
1474 break;
1475 case USB_SPEED_SUPER_PLUS:
1476 if ((DWC3_IP_IS(DWC32) &&
1477 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1478 (!DWC3_IP_IS(DWC32) &&
1479 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1480 dev_warn(dev, "UDC doesn't support SSP\n");
1481 break;
1482 default:
1483 dev_err(dev, "invalid maximum_speed parameter %d\n",
1484 dwc->maximum_speed);
1485 fallthrough;
1486 case USB_SPEED_UNKNOWN:
1487 switch (hwparam_gen) {
1488 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1489 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1490 break;
1491 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1492 if (DWC3_IP_IS(DWC32))
1493 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1494 else
1495 dwc->maximum_speed = USB_SPEED_SUPER;
1496 break;
1497 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1498 dwc->maximum_speed = USB_SPEED_HIGH;
1499 break;
1500 default:
1501 dwc->maximum_speed = USB_SPEED_SUPER;
1502 break;
1503 }
1504 break;
1505 }
1506 }
1507
dwc3_probe(struct platform_device * pdev)1508 static int dwc3_probe(struct platform_device *pdev)
1509 {
1510 struct device *dev = &pdev->dev;
1511 struct resource *res, dwc_res;
1512 struct dwc3 *dwc;
1513
1514 int ret;
1515
1516 void __iomem *regs;
1517
1518 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1519 if (!dwc)
1520 return -ENOMEM;
1521
1522 dwc->dev = dev;
1523
1524 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1525 if (!res) {
1526 dev_err(dev, "missing memory resource\n");
1527 return -ENODEV;
1528 }
1529
1530 dwc->xhci_resources[0].start = res->start;
1531 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1532 DWC3_XHCI_REGS_END;
1533 dwc->xhci_resources[0].flags = res->flags;
1534 dwc->xhci_resources[0].name = res->name;
1535
1536 /*
1537 * Request memory region but exclude xHCI regs,
1538 * since it will be requested by the xhci-plat driver.
1539 */
1540 dwc_res = *res;
1541 dwc_res.start += DWC3_GLOBALS_REGS_START;
1542
1543 regs = devm_ioremap_resource(dev, &dwc_res);
1544 if (IS_ERR(regs))
1545 return PTR_ERR(regs);
1546
1547 dwc->regs = regs;
1548 dwc->regs_size = resource_size(&dwc_res);
1549
1550 dwc3_get_properties(dwc);
1551
1552 dwc->reset = devm_reset_control_array_get(dev, true, true);
1553 if (IS_ERR(dwc->reset))
1554 return PTR_ERR(dwc->reset);
1555
1556 if (dev->of_node) {
1557 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1558 if (ret == -EPROBE_DEFER)
1559 return ret;
1560 /*
1561 * Clocks are optional, but new DT platforms should support all
1562 * clocks as required by the DT-binding.
1563 */
1564 if (ret < 0)
1565 dwc->num_clks = 0;
1566 else
1567 dwc->num_clks = ret;
1568
1569 }
1570
1571 ret = reset_control_deassert(dwc->reset);
1572 if (ret)
1573 return ret;
1574
1575 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1576 if (ret)
1577 goto assert_reset;
1578
1579 if (!dwc3_core_is_valid(dwc)) {
1580 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1581 ret = -ENODEV;
1582 goto disable_clks;
1583 }
1584
1585 platform_set_drvdata(pdev, dwc);
1586 dwc3_cache_hwparams(dwc);
1587
1588 spin_lock_init(&dwc->lock);
1589 mutex_init(&dwc->mutex);
1590
1591 pm_runtime_get_noresume(dev);
1592 pm_runtime_set_active(dev);
1593 pm_runtime_use_autosuspend(dev);
1594 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1595 pm_runtime_enable(dev);
1596
1597 pm_runtime_forbid(dev);
1598
1599 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1600 if (ret) {
1601 dev_err(dwc->dev, "failed to allocate event buffers\n");
1602 ret = -ENOMEM;
1603 goto err2;
1604 }
1605
1606 ret = dwc3_get_dr_mode(dwc);
1607 if (ret)
1608 goto err3;
1609
1610 ret = dwc3_alloc_scratch_buffers(dwc);
1611 if (ret)
1612 goto err3;
1613
1614 ret = dwc3_core_init(dwc);
1615 if (ret) {
1616 if (ret != -EPROBE_DEFER)
1617 dev_err(dev, "failed to initialize core: %d\n", ret);
1618 goto err4;
1619 }
1620
1621 dwc3_check_params(dwc);
1622 dwc3_debugfs_init(dwc);
1623
1624 ret = dwc3_core_init_mode(dwc);
1625 if (ret)
1626 goto err5;
1627
1628 pm_runtime_put(dev);
1629
1630 dma_set_max_seg_size(dev, UINT_MAX);
1631
1632 return 0;
1633
1634 err5:
1635 dwc3_debugfs_exit(dwc);
1636 dwc3_event_buffers_cleanup(dwc);
1637
1638 usb_phy_set_suspend(dwc->usb2_phy, 1);
1639 usb_phy_set_suspend(dwc->usb3_phy, 1);
1640 phy_power_off(dwc->usb2_generic_phy);
1641 phy_power_off(dwc->usb3_generic_phy);
1642
1643 usb_phy_shutdown(dwc->usb2_phy);
1644 usb_phy_shutdown(dwc->usb3_phy);
1645 phy_exit(dwc->usb2_generic_phy);
1646 phy_exit(dwc->usb3_generic_phy);
1647
1648 dwc3_ulpi_exit(dwc);
1649
1650 err4:
1651 dwc3_free_scratch_buffers(dwc);
1652
1653 err3:
1654 dwc3_free_event_buffers(dwc);
1655
1656 err2:
1657 pm_runtime_allow(dev);
1658 pm_runtime_disable(dev);
1659 pm_runtime_set_suspended(dev);
1660 pm_runtime_put_noidle(dev);
1661 disable_clks:
1662 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1663 assert_reset:
1664 reset_control_assert(dwc->reset);
1665
1666 return ret;
1667 }
1668
dwc3_remove(struct platform_device * pdev)1669 static int dwc3_remove(struct platform_device *pdev)
1670 {
1671 struct dwc3 *dwc = platform_get_drvdata(pdev);
1672
1673 pm_runtime_get_sync(&pdev->dev);
1674
1675 dwc3_core_exit_mode(dwc);
1676 dwc3_debugfs_exit(dwc);
1677
1678 dwc3_core_exit(dwc);
1679 dwc3_ulpi_exit(dwc);
1680
1681 pm_runtime_allow(&pdev->dev);
1682 pm_runtime_disable(&pdev->dev);
1683 pm_runtime_put_noidle(&pdev->dev);
1684 pm_runtime_set_suspended(&pdev->dev);
1685
1686 dwc3_free_event_buffers(dwc);
1687 dwc3_free_scratch_buffers(dwc);
1688
1689 return 0;
1690 }
1691
1692 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)1693 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1694 {
1695 int ret;
1696
1697 ret = reset_control_deassert(dwc->reset);
1698 if (ret)
1699 return ret;
1700
1701 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1702 if (ret)
1703 goto assert_reset;
1704
1705 ret = dwc3_core_init(dwc);
1706 if (ret)
1707 goto disable_clks;
1708
1709 return 0;
1710
1711 disable_clks:
1712 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1713 assert_reset:
1714 reset_control_assert(dwc->reset);
1715
1716 return ret;
1717 }
1718
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)1719 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1720 {
1721 unsigned long flags;
1722 u32 reg;
1723
1724 switch (dwc->current_dr_role) {
1725 case DWC3_GCTL_PRTCAP_DEVICE:
1726 if (pm_runtime_suspended(dwc->dev))
1727 break;
1728 spin_lock_irqsave(&dwc->lock, flags);
1729 dwc3_gadget_suspend(dwc);
1730 spin_unlock_irqrestore(&dwc->lock, flags);
1731 synchronize_irq(dwc->irq_gadget);
1732 dwc3_core_exit(dwc);
1733 break;
1734 case DWC3_GCTL_PRTCAP_HOST:
1735 if (!PMSG_IS_AUTO(msg)) {
1736 dwc3_core_exit(dwc);
1737 break;
1738 }
1739
1740 /* Let controller to suspend HSPHY before PHY driver suspends */
1741 if (dwc->dis_u2_susphy_quirk ||
1742 dwc->dis_enblslpm_quirk) {
1743 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1744 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1745 DWC3_GUSB2PHYCFG_SUSPHY;
1746 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1747
1748 /* Give some time for USB2 PHY to suspend */
1749 usleep_range(5000, 6000);
1750 }
1751
1752 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1753 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1754 break;
1755 case DWC3_GCTL_PRTCAP_OTG:
1756 /* do nothing during runtime_suspend */
1757 if (PMSG_IS_AUTO(msg))
1758 break;
1759
1760 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1761 spin_lock_irqsave(&dwc->lock, flags);
1762 dwc3_gadget_suspend(dwc);
1763 spin_unlock_irqrestore(&dwc->lock, flags);
1764 synchronize_irq(dwc->irq_gadget);
1765 }
1766
1767 dwc3_otg_exit(dwc);
1768 dwc3_core_exit(dwc);
1769 break;
1770 default:
1771 /* do nothing */
1772 break;
1773 }
1774
1775 return 0;
1776 }
1777
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)1778 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1779 {
1780 unsigned long flags;
1781 int ret;
1782 u32 reg;
1783
1784 switch (dwc->current_dr_role) {
1785 case DWC3_GCTL_PRTCAP_DEVICE:
1786 ret = dwc3_core_init_for_resume(dwc);
1787 if (ret)
1788 return ret;
1789
1790 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1791 spin_lock_irqsave(&dwc->lock, flags);
1792 dwc3_gadget_resume(dwc);
1793 spin_unlock_irqrestore(&dwc->lock, flags);
1794 break;
1795 case DWC3_GCTL_PRTCAP_HOST:
1796 if (!PMSG_IS_AUTO(msg)) {
1797 ret = dwc3_core_init_for_resume(dwc);
1798 if (ret)
1799 return ret;
1800 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1801 break;
1802 }
1803 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1804 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1805 if (dwc->dis_u2_susphy_quirk)
1806 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1807
1808 if (dwc->dis_enblslpm_quirk)
1809 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1810
1811 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1812
1813 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1814 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1815 break;
1816 case DWC3_GCTL_PRTCAP_OTG:
1817 /* nothing to do on runtime_resume */
1818 if (PMSG_IS_AUTO(msg))
1819 break;
1820
1821 ret = dwc3_core_init_for_resume(dwc);
1822 if (ret)
1823 return ret;
1824
1825 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1826
1827 dwc3_otg_init(dwc);
1828 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1829 dwc3_otg_host_init(dwc);
1830 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1831 spin_lock_irqsave(&dwc->lock, flags);
1832 dwc3_gadget_resume(dwc);
1833 spin_unlock_irqrestore(&dwc->lock, flags);
1834 }
1835
1836 break;
1837 default:
1838 /* do nothing */
1839 break;
1840 }
1841
1842 return 0;
1843 }
1844
dwc3_runtime_checks(struct dwc3 * dwc)1845 static int dwc3_runtime_checks(struct dwc3 *dwc)
1846 {
1847 switch (dwc->current_dr_role) {
1848 case DWC3_GCTL_PRTCAP_DEVICE:
1849 if (dwc->connected)
1850 return -EBUSY;
1851 break;
1852 case DWC3_GCTL_PRTCAP_HOST:
1853 default:
1854 /* do nothing */
1855 break;
1856 }
1857
1858 return 0;
1859 }
1860
dwc3_runtime_suspend(struct device * dev)1861 static int dwc3_runtime_suspend(struct device *dev)
1862 {
1863 struct dwc3 *dwc = dev_get_drvdata(dev);
1864 int ret;
1865
1866 if (dwc3_runtime_checks(dwc))
1867 return -EBUSY;
1868
1869 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1870 if (ret)
1871 return ret;
1872
1873 device_init_wakeup(dev, true);
1874
1875 return 0;
1876 }
1877
dwc3_runtime_resume(struct device * dev)1878 static int dwc3_runtime_resume(struct device *dev)
1879 {
1880 struct dwc3 *dwc = dev_get_drvdata(dev);
1881 int ret;
1882
1883 device_init_wakeup(dev, false);
1884
1885 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1886 if (ret)
1887 return ret;
1888
1889 switch (dwc->current_dr_role) {
1890 case DWC3_GCTL_PRTCAP_DEVICE:
1891 dwc3_gadget_process_pending_events(dwc);
1892 break;
1893 case DWC3_GCTL_PRTCAP_HOST:
1894 default:
1895 /* do nothing */
1896 break;
1897 }
1898
1899 pm_runtime_mark_last_busy(dev);
1900
1901 return 0;
1902 }
1903
dwc3_runtime_idle(struct device * dev)1904 static int dwc3_runtime_idle(struct device *dev)
1905 {
1906 struct dwc3 *dwc = dev_get_drvdata(dev);
1907
1908 switch (dwc->current_dr_role) {
1909 case DWC3_GCTL_PRTCAP_DEVICE:
1910 if (dwc3_runtime_checks(dwc))
1911 return -EBUSY;
1912 break;
1913 case DWC3_GCTL_PRTCAP_HOST:
1914 default:
1915 /* do nothing */
1916 break;
1917 }
1918
1919 pm_runtime_mark_last_busy(dev);
1920 pm_runtime_autosuspend(dev);
1921
1922 return 0;
1923 }
1924 #endif /* CONFIG_PM */
1925
1926 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)1927 static int dwc3_suspend(struct device *dev)
1928 {
1929 struct dwc3 *dwc = dev_get_drvdata(dev);
1930 int ret;
1931
1932 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1933 if (ret)
1934 return ret;
1935
1936 pinctrl_pm_select_sleep_state(dev);
1937
1938 return 0;
1939 }
1940
dwc3_resume(struct device * dev)1941 static int dwc3_resume(struct device *dev)
1942 {
1943 struct dwc3 *dwc = dev_get_drvdata(dev);
1944 int ret;
1945
1946 pinctrl_pm_select_default_state(dev);
1947
1948 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1949 if (ret)
1950 return ret;
1951
1952 pm_runtime_disable(dev);
1953 pm_runtime_set_active(dev);
1954 pm_runtime_enable(dev);
1955
1956 return 0;
1957 }
1958
dwc3_complete(struct device * dev)1959 static void dwc3_complete(struct device *dev)
1960 {
1961 struct dwc3 *dwc = dev_get_drvdata(dev);
1962 u32 reg;
1963
1964 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1965 dwc->dis_split_quirk) {
1966 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1967 reg |= DWC3_GUCTL3_SPLITDISABLE;
1968 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1969 }
1970 }
1971 #else
1972 #define dwc3_complete NULL
1973 #endif /* CONFIG_PM_SLEEP */
1974
1975 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1976 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1977 .complete = dwc3_complete,
1978 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1979 dwc3_runtime_idle)
1980 };
1981
1982 #ifdef CONFIG_OF
1983 static const struct of_device_id of_dwc3_match[] = {
1984 {
1985 .compatible = "snps,dwc3"
1986 },
1987 {
1988 .compatible = "synopsys,dwc3"
1989 },
1990 { },
1991 };
1992 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1993 #endif
1994
1995 #ifdef CONFIG_ACPI
1996
1997 #define ACPI_ID_INTEL_BSW "808622B7"
1998
1999 static const struct acpi_device_id dwc3_acpi_match[] = {
2000 { ACPI_ID_INTEL_BSW, 0 },
2001 { },
2002 };
2003 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2004 #endif
2005
2006 static struct platform_driver dwc3_driver = {
2007 .probe = dwc3_probe,
2008 .remove = dwc3_remove,
2009 .driver = {
2010 .name = "dwc3",
2011 .of_match_table = of_match_ptr(of_dwc3_match),
2012 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2013 .pm = &dwc3_dev_pm_ops,
2014 },
2015 };
2016
2017 module_platform_driver(dwc3_driver);
2018
2019 MODULE_ALIAS("platform:dwc3");
2020 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2021 MODULE_LICENSE("GPL v2");
2022 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2023