1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_BACKEND_MIPS64_INSTRUCTION_CODES_MIPS64_H_ 6 #define V8_COMPILER_BACKEND_MIPS64_INSTRUCTION_CODES_MIPS64_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // MIPS64-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 15 #define TARGET_ARCH_OPCODE_LIST(V) \ 16 V(Mips64Add) \ 17 V(Mips64Dadd) \ 18 V(Mips64DaddOvf) \ 19 V(Mips64Sub) \ 20 V(Mips64Dsub) \ 21 V(Mips64DsubOvf) \ 22 V(Mips64Mul) \ 23 V(Mips64MulOvf) \ 24 V(Mips64MulHigh) \ 25 V(Mips64DMulHigh) \ 26 V(Mips64MulHighU) \ 27 V(Mips64Dmul) \ 28 V(Mips64Div) \ 29 V(Mips64Ddiv) \ 30 V(Mips64DivU) \ 31 V(Mips64DdivU) \ 32 V(Mips64Mod) \ 33 V(Mips64Dmod) \ 34 V(Mips64ModU) \ 35 V(Mips64DmodU) \ 36 V(Mips64And) \ 37 V(Mips64And32) \ 38 V(Mips64Or) \ 39 V(Mips64Or32) \ 40 V(Mips64Nor) \ 41 V(Mips64Nor32) \ 42 V(Mips64Xor) \ 43 V(Mips64Xor32) \ 44 V(Mips64Clz) \ 45 V(Mips64Lsa) \ 46 V(Mips64Dlsa) \ 47 V(Mips64Shl) \ 48 V(Mips64Shr) \ 49 V(Mips64Sar) \ 50 V(Mips64Ext) \ 51 V(Mips64Ins) \ 52 V(Mips64Dext) \ 53 V(Mips64Dins) \ 54 V(Mips64Dclz) \ 55 V(Mips64Ctz) \ 56 V(Mips64Dctz) \ 57 V(Mips64Popcnt) \ 58 V(Mips64Dpopcnt) \ 59 V(Mips64Dshl) \ 60 V(Mips64Dshr) \ 61 V(Mips64Dsar) \ 62 V(Mips64Ror) \ 63 V(Mips64Dror) \ 64 V(Mips64Mov) \ 65 V(Mips64Tst) \ 66 V(Mips64Cmp) \ 67 V(Mips64CmpS) \ 68 V(Mips64AddS) \ 69 V(Mips64SubS) \ 70 V(Mips64MulS) \ 71 V(Mips64DivS) \ 72 V(Mips64AbsS) \ 73 V(Mips64NegS) \ 74 V(Mips64SqrtS) \ 75 V(Mips64MaxS) \ 76 V(Mips64MinS) \ 77 V(Mips64CmpD) \ 78 V(Mips64AddD) \ 79 V(Mips64SubD) \ 80 V(Mips64MulD) \ 81 V(Mips64DivD) \ 82 V(Mips64ModD) \ 83 V(Mips64AbsD) \ 84 V(Mips64NegD) \ 85 V(Mips64SqrtD) \ 86 V(Mips64MaxD) \ 87 V(Mips64MinD) \ 88 V(Mips64Float64RoundDown) \ 89 V(Mips64Float64RoundTruncate) \ 90 V(Mips64Float64RoundUp) \ 91 V(Mips64Float64RoundTiesEven) \ 92 V(Mips64Float32RoundDown) \ 93 V(Mips64Float32RoundTruncate) \ 94 V(Mips64Float32RoundUp) \ 95 V(Mips64Float32RoundTiesEven) \ 96 V(Mips64CvtSD) \ 97 V(Mips64CvtDS) \ 98 V(Mips64TruncWD) \ 99 V(Mips64RoundWD) \ 100 V(Mips64FloorWD) \ 101 V(Mips64CeilWD) \ 102 V(Mips64TruncWS) \ 103 V(Mips64RoundWS) \ 104 V(Mips64FloorWS) \ 105 V(Mips64CeilWS) \ 106 V(Mips64TruncLS) \ 107 V(Mips64TruncLD) \ 108 V(Mips64TruncUwD) \ 109 V(Mips64TruncUwS) \ 110 V(Mips64TruncUlS) \ 111 V(Mips64TruncUlD) \ 112 V(Mips64CvtDW) \ 113 V(Mips64CvtSL) \ 114 V(Mips64CvtSW) \ 115 V(Mips64CvtSUw) \ 116 V(Mips64CvtSUl) \ 117 V(Mips64CvtDL) \ 118 V(Mips64CvtDUw) \ 119 V(Mips64CvtDUl) \ 120 V(Mips64Lb) \ 121 V(Mips64Lbu) \ 122 V(Mips64Sb) \ 123 V(Mips64Lh) \ 124 V(Mips64Ulh) \ 125 V(Mips64Lhu) \ 126 V(Mips64Ulhu) \ 127 V(Mips64Sh) \ 128 V(Mips64Ush) \ 129 V(Mips64Ld) \ 130 V(Mips64Uld) \ 131 V(Mips64Lw) \ 132 V(Mips64Ulw) \ 133 V(Mips64Lwu) \ 134 V(Mips64Ulwu) \ 135 V(Mips64Sw) \ 136 V(Mips64Usw) \ 137 V(Mips64Sd) \ 138 V(Mips64Usd) \ 139 V(Mips64Lwc1) \ 140 V(Mips64Ulwc1) \ 141 V(Mips64Swc1) \ 142 V(Mips64Uswc1) \ 143 V(Mips64Ldc1) \ 144 V(Mips64Uldc1) \ 145 V(Mips64Sdc1) \ 146 V(Mips64Usdc1) \ 147 V(Mips64BitcastDL) \ 148 V(Mips64BitcastLD) \ 149 V(Mips64Float64ExtractLowWord32) \ 150 V(Mips64Float64ExtractHighWord32) \ 151 V(Mips64Float64InsertLowWord32) \ 152 V(Mips64Float64InsertHighWord32) \ 153 V(Mips64Float32Max) \ 154 V(Mips64Float64Max) \ 155 V(Mips64Float32Min) \ 156 V(Mips64Float64Min) \ 157 V(Mips64Float64SilenceNaN) \ 158 V(Mips64Push) \ 159 V(Mips64Peek) \ 160 V(Mips64StoreToStackSlot) \ 161 V(Mips64ByteSwap64) \ 162 V(Mips64ByteSwap32) \ 163 V(Mips64StackClaim) \ 164 V(Mips64Seb) \ 165 V(Mips64Seh) \ 166 V(Mips64Sync) \ 167 V(Mips64AssertEqual) \ 168 V(Mips64S128Const) \ 169 V(Mips64S128Zero) \ 170 V(Mips64S128AllOnes) \ 171 V(Mips64I32x4Splat) \ 172 V(Mips64I32x4ExtractLane) \ 173 V(Mips64I32x4ReplaceLane) \ 174 V(Mips64I32x4Add) \ 175 V(Mips64I32x4Sub) \ 176 V(Mips64F64x2Abs) \ 177 V(Mips64F64x2Neg) \ 178 V(Mips64F32x4Splat) \ 179 V(Mips64F32x4ExtractLane) \ 180 V(Mips64F32x4ReplaceLane) \ 181 V(Mips64F32x4SConvertI32x4) \ 182 V(Mips64F32x4UConvertI32x4) \ 183 V(Mips64I32x4Mul) \ 184 V(Mips64I32x4MaxS) \ 185 V(Mips64I32x4MinS) \ 186 V(Mips64I32x4Eq) \ 187 V(Mips64I32x4Ne) \ 188 V(Mips64I32x4Shl) \ 189 V(Mips64I32x4ShrS) \ 190 V(Mips64I32x4ShrU) \ 191 V(Mips64I32x4MaxU) \ 192 V(Mips64I32x4MinU) \ 193 V(Mips64F64x2Sqrt) \ 194 V(Mips64F64x2Add) \ 195 V(Mips64F64x2Sub) \ 196 V(Mips64F64x2Mul) \ 197 V(Mips64F64x2Div) \ 198 V(Mips64F64x2Min) \ 199 V(Mips64F64x2Max) \ 200 V(Mips64F64x2Eq) \ 201 V(Mips64F64x2Ne) \ 202 V(Mips64F64x2Lt) \ 203 V(Mips64F64x2Le) \ 204 V(Mips64F64x2Splat) \ 205 V(Mips64F64x2ExtractLane) \ 206 V(Mips64F64x2ReplaceLane) \ 207 V(Mips64F64x2Pmin) \ 208 V(Mips64F64x2Pmax) \ 209 V(Mips64F64x2Ceil) \ 210 V(Mips64F64x2Floor) \ 211 V(Mips64F64x2Trunc) \ 212 V(Mips64F64x2NearestInt) \ 213 V(Mips64F64x2ConvertLowI32x4S) \ 214 V(Mips64F64x2ConvertLowI32x4U) \ 215 V(Mips64F64x2PromoteLowF32x4) \ 216 V(Mips64I64x2Splat) \ 217 V(Mips64I64x2ExtractLane) \ 218 V(Mips64I64x2ReplaceLane) \ 219 V(Mips64I64x2Add) \ 220 V(Mips64I64x2Sub) \ 221 V(Mips64I64x2Mul) \ 222 V(Mips64I64x2Neg) \ 223 V(Mips64I64x2Shl) \ 224 V(Mips64I64x2ShrS) \ 225 V(Mips64I64x2ShrU) \ 226 V(Mips64I64x2BitMask) \ 227 V(Mips64I64x2Eq) \ 228 V(Mips64I64x2Ne) \ 229 V(Mips64I64x2GtS) \ 230 V(Mips64I64x2GeS) \ 231 V(Mips64I64x2Abs) \ 232 V(Mips64I64x2SConvertI32x4Low) \ 233 V(Mips64I64x2SConvertI32x4High) \ 234 V(Mips64I64x2UConvertI32x4Low) \ 235 V(Mips64I64x2UConvertI32x4High) \ 236 V(Mips64ExtMulLow) \ 237 V(Mips64ExtMulHigh) \ 238 V(Mips64ExtAddPairwise) \ 239 V(Mips64F32x4Abs) \ 240 V(Mips64F32x4Neg) \ 241 V(Mips64F32x4Sqrt) \ 242 V(Mips64F32x4RecipApprox) \ 243 V(Mips64F32x4RecipSqrtApprox) \ 244 V(Mips64F32x4Add) \ 245 V(Mips64F32x4Sub) \ 246 V(Mips64F32x4Mul) \ 247 V(Mips64F32x4Div) \ 248 V(Mips64F32x4Max) \ 249 V(Mips64F32x4Min) \ 250 V(Mips64F32x4Eq) \ 251 V(Mips64F32x4Ne) \ 252 V(Mips64F32x4Lt) \ 253 V(Mips64F32x4Le) \ 254 V(Mips64F32x4Pmin) \ 255 V(Mips64F32x4Pmax) \ 256 V(Mips64F32x4Ceil) \ 257 V(Mips64F32x4Floor) \ 258 V(Mips64F32x4Trunc) \ 259 V(Mips64F32x4NearestInt) \ 260 V(Mips64F32x4DemoteF64x2Zero) \ 261 V(Mips64I32x4SConvertF32x4) \ 262 V(Mips64I32x4UConvertF32x4) \ 263 V(Mips64I32x4Neg) \ 264 V(Mips64I32x4GtS) \ 265 V(Mips64I32x4GeS) \ 266 V(Mips64I32x4GtU) \ 267 V(Mips64I32x4GeU) \ 268 V(Mips64I32x4Abs) \ 269 V(Mips64I32x4BitMask) \ 270 V(Mips64I32x4DotI16x8S) \ 271 V(Mips64I32x4TruncSatF64x2SZero) \ 272 V(Mips64I32x4TruncSatF64x2UZero) \ 273 V(Mips64I16x8Splat) \ 274 V(Mips64I16x8ExtractLaneU) \ 275 V(Mips64I16x8ExtractLaneS) \ 276 V(Mips64I16x8ReplaceLane) \ 277 V(Mips64I16x8Neg) \ 278 V(Mips64I16x8Shl) \ 279 V(Mips64I16x8ShrS) \ 280 V(Mips64I16x8ShrU) \ 281 V(Mips64I16x8Add) \ 282 V(Mips64I16x8AddSatS) \ 283 V(Mips64I16x8Sub) \ 284 V(Mips64I16x8SubSatS) \ 285 V(Mips64I16x8Mul) \ 286 V(Mips64I16x8MaxS) \ 287 V(Mips64I16x8MinS) \ 288 V(Mips64I16x8Eq) \ 289 V(Mips64I16x8Ne) \ 290 V(Mips64I16x8GtS) \ 291 V(Mips64I16x8GeS) \ 292 V(Mips64I16x8AddSatU) \ 293 V(Mips64I16x8SubSatU) \ 294 V(Mips64I16x8MaxU) \ 295 V(Mips64I16x8MinU) \ 296 V(Mips64I16x8GtU) \ 297 V(Mips64I16x8GeU) \ 298 V(Mips64I16x8RoundingAverageU) \ 299 V(Mips64I16x8Abs) \ 300 V(Mips64I16x8BitMask) \ 301 V(Mips64I16x8Q15MulRSatS) \ 302 V(Mips64I8x16Splat) \ 303 V(Mips64I8x16ExtractLaneU) \ 304 V(Mips64I8x16ExtractLaneS) \ 305 V(Mips64I8x16ReplaceLane) \ 306 V(Mips64I8x16Neg) \ 307 V(Mips64I8x16Shl) \ 308 V(Mips64I8x16ShrS) \ 309 V(Mips64I8x16Add) \ 310 V(Mips64I8x16AddSatS) \ 311 V(Mips64I8x16Sub) \ 312 V(Mips64I8x16SubSatS) \ 313 V(Mips64I8x16MaxS) \ 314 V(Mips64I8x16MinS) \ 315 V(Mips64I8x16Eq) \ 316 V(Mips64I8x16Ne) \ 317 V(Mips64I8x16GtS) \ 318 V(Mips64I8x16GeS) \ 319 V(Mips64I8x16ShrU) \ 320 V(Mips64I8x16AddSatU) \ 321 V(Mips64I8x16SubSatU) \ 322 V(Mips64I8x16MaxU) \ 323 V(Mips64I8x16MinU) \ 324 V(Mips64I8x16GtU) \ 325 V(Mips64I8x16GeU) \ 326 V(Mips64I8x16RoundingAverageU) \ 327 V(Mips64I8x16Abs) \ 328 V(Mips64I8x16Popcnt) \ 329 V(Mips64I8x16BitMask) \ 330 V(Mips64S128And) \ 331 V(Mips64S128Or) \ 332 V(Mips64S128Xor) \ 333 V(Mips64S128Not) \ 334 V(Mips64S128Select) \ 335 V(Mips64S128AndNot) \ 336 V(Mips64I64x2AllTrue) \ 337 V(Mips64I32x4AllTrue) \ 338 V(Mips64I16x8AllTrue) \ 339 V(Mips64I8x16AllTrue) \ 340 V(Mips64V128AnyTrue) \ 341 V(Mips64S32x4InterleaveRight) \ 342 V(Mips64S32x4InterleaveLeft) \ 343 V(Mips64S32x4PackEven) \ 344 V(Mips64S32x4PackOdd) \ 345 V(Mips64S32x4InterleaveEven) \ 346 V(Mips64S32x4InterleaveOdd) \ 347 V(Mips64S32x4Shuffle) \ 348 V(Mips64S16x8InterleaveRight) \ 349 V(Mips64S16x8InterleaveLeft) \ 350 V(Mips64S16x8PackEven) \ 351 V(Mips64S16x8PackOdd) \ 352 V(Mips64S16x8InterleaveEven) \ 353 V(Mips64S16x8InterleaveOdd) \ 354 V(Mips64S16x4Reverse) \ 355 V(Mips64S16x2Reverse) \ 356 V(Mips64S8x16InterleaveRight) \ 357 V(Mips64S8x16InterleaveLeft) \ 358 V(Mips64S8x16PackEven) \ 359 V(Mips64S8x16PackOdd) \ 360 V(Mips64S8x16InterleaveEven) \ 361 V(Mips64S8x16InterleaveOdd) \ 362 V(Mips64I8x16Shuffle) \ 363 V(Mips64I8x16Swizzle) \ 364 V(Mips64S8x16Concat) \ 365 V(Mips64S8x8Reverse) \ 366 V(Mips64S8x4Reverse) \ 367 V(Mips64S8x2Reverse) \ 368 V(Mips64S128LoadSplat) \ 369 V(Mips64S128Load8x8S) \ 370 V(Mips64S128Load8x8U) \ 371 V(Mips64S128Load16x4S) \ 372 V(Mips64S128Load16x4U) \ 373 V(Mips64S128Load32x2S) \ 374 V(Mips64S128Load32x2U) \ 375 V(Mips64S128Load32Zero) \ 376 V(Mips64S128Load64Zero) \ 377 V(Mips64S128LoadLane) \ 378 V(Mips64S128StoreLane) \ 379 V(Mips64MsaLd) \ 380 V(Mips64MsaSt) \ 381 V(Mips64I32x4SConvertI16x8Low) \ 382 V(Mips64I32x4SConvertI16x8High) \ 383 V(Mips64I32x4UConvertI16x8Low) \ 384 V(Mips64I32x4UConvertI16x8High) \ 385 V(Mips64I16x8SConvertI8x16Low) \ 386 V(Mips64I16x8SConvertI8x16High) \ 387 V(Mips64I16x8SConvertI32x4) \ 388 V(Mips64I16x8UConvertI32x4) \ 389 V(Mips64I16x8UConvertI8x16Low) \ 390 V(Mips64I16x8UConvertI8x16High) \ 391 V(Mips64I8x16SConvertI16x8) \ 392 V(Mips64I8x16UConvertI16x8) \ 393 V(Mips64StoreCompressTagged) \ 394 V(Mips64Word64AtomicLoadUint64) \ 395 V(Mips64Word64AtomicStoreWord64) \ 396 V(Mips64Word64AtomicAddUint64) \ 397 V(Mips64Word64AtomicSubUint64) \ 398 V(Mips64Word64AtomicAndUint64) \ 399 V(Mips64Word64AtomicOrUint64) \ 400 V(Mips64Word64AtomicXorUint64) \ 401 V(Mips64Word64AtomicExchangeUint64) \ 402 V(Mips64Word64AtomicCompareExchangeUint64) 403 404 // Addressing modes represent the "shape" of inputs to an instruction. 405 // Many instructions support multiple addressing modes. Addressing modes 406 // are encoded into the InstructionCode of the instruction and tell the 407 // code generator after register allocation which assembler method to call. 408 // 409 // We use the following local notation for addressing modes: 410 // 411 // R = register 412 // O = register or stack slot 413 // D = double register 414 // I = immediate (handle, external, int32) 415 // MRI = [register + immediate] 416 // MRR = [register + register] 417 // TODO(plind): Add the new r6 address modes. 418 #define TARGET_ADDRESSING_MODE_LIST(V) \ 419 V(MRI) /* [%r0 + K] */ \ 420 V(MRR) /* [%r0 + %r1] */ 421 422 } // namespace compiler 423 } // namespace internal 424 } // namespace v8 425 426 #endif // V8_COMPILER_BACKEND_MIPS64_INSTRUCTION_CODES_MIPS64_H_ 427