Searched +full:0 +full:x11210000 (Results 1 – 14 of 14) sorted by relevance
140 reg = <0x11210000 0x9000>;
116 reg = <0x11210000 0x2000>;
26 #size-cells = <0>;28 cpu0: cpu@0 {32 reg = <0x000>;39 reg = <0x100>;46 reg = <0x200>;53 reg = <0x300>;60 reg = <0x400>;67 reg = <0x500>;74 reg = <0x600>;81 reg = <0x700>;[all …]
34 #clock-cells = <0>;43 #clock-cells = <0>;50 #clock-cells = <0>;57 #size-cells = <0>;59 cpu0: cpu@0 {62 reg = <0x000>;73 performance-domains = <&performance 0>;80 reg = <0x100>;91 performance-domains = <&performance 0>;98 reg = <0x200>;[all …]
327 #size-cells = <0>;365 cpu0: cpu@0 {368 reg = <0x000>;392 reg = <0x100>;416 reg = <0x200>;440 reg = <0x300>;464 reg = <0x400>;488 reg = <0x500>;512 reg = <0x600>;536 reg = <0x700>;[all …]
25 #size-cells = <0>;28 cpu@0 {31 reg = <0x0>;36 reg = <0x1>;41 reg = <0x2>;46 reg = <0x3>;57 reg = <0 0x80002000 0 0x1000>;64 #clock-cells = <0>;70 #clock-cells = <0>;73 clk26m: oscillator@0 {[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0>;169 reg = <0x02020000 0x30000>;172 ranges = <0 0x02020000 0x30000>;174 smp-sram@0 {176 reg = <0x0 0x1000>;181 reg = <0x2f000 0x1000>;187 reg = <0x10044000 0x20>;188 #power-domain-cells = <0>;[all …]
162 reg = <0x10d20000 0x1000>;163 ranges = <0x0 0x10d20000 0x6000>;168 reg = <0x4000 0x1000>;173 reg = <0x5000 0x1000>;179 reg = <0x10010000 0x30000>;185 reg = <0x03810000 0x0C>;195 reg = <0x11000000 0x10000>;208 #size-cells = <0>;209 reg = <0x12200000 0x2000>;212 fifo-depth = <0x40>;[all …]
73 #size-cells = <0>;76 cpu0: cpu@0 {79 reg = <0x0>;91 reg = <0x1>;103 reg = <0x2>;115 reg = <0x3>;137 #clock-cells = <0>;142 #clock-cells = <0>;147 clk26m: oscillator-0 {149 #clock-cells = <0>;[all …]
47 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;80 cpu0_opp_table: opp-table-0 {176 reg = <0x02020000 0x30000>;179 ranges = <0 0x02020000 0x30000>;181 smp-sram@0 {183 reg = <0x0 0x1000>;188 reg = <0x2f000 0x1000>;194 reg = <0x10044000 0x20>;[all …]
153 cluster_a15_opp_table: opp-table-0 {270 reg = <0x10d20000 0x1000>;271 ranges = <0x0 0x10d20000 0x6000>;276 reg = <0x4000 0x1000>;281 reg = <0x5000 0x1000>;287 reg = <0x10010000 0x30000>;293 reg = <0x03810000 0x0c>;303 reg = <0x11000000 0x10000>;316 #size-cells = <0>;317 reg = <0x12200000 0x2000>;[all …]
2 index 1877da816..0b45060b7 100644188 @@ -0,0 +1,240 @@218 + #size-cells = <0>;220 + cpu@0 {223 + reg = <0>;261 + opp-freq = <0 1 2 3 4>;271 + reg = <0x80000000 0x40000000>;309 + spidev@0 {311 + reg = <0>;312 + pl022,interface = <0>;[all …]
47 index 0b3cd7a33..763d37e86 100644118 @@ -0,0 +1,270 @@148 + reg = <0x82000000 0x20000000>;233 + spidev@0 {235 + reg = <0>;236 + pl022,interface = <0>;237 + pl022,com-mode = <0>;245 + spidev@0 {247 + reg = <0>;248 + pl022,interface = <0>;[all …]