1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_BACKEND_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_BACKEND_ARM64_INSTRUCTION_CODES_ARM64_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // ARM64-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 15 // Opcodes that support a MemoryAccessMode. 16 #define TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \ 17 V(Arm64Ldr) \ 18 V(Arm64Ldrb) \ 19 V(Arm64LdrD) \ 20 V(Arm64Ldrh) \ 21 V(Arm64LdrQ) \ 22 V(Arm64LdrS) \ 23 V(Arm64Ldrsb) \ 24 V(Arm64LdrsbW) \ 25 V(Arm64Ldrsh) \ 26 V(Arm64LdrshW) \ 27 V(Arm64Ldrsw) \ 28 V(Arm64LdrW) \ 29 V(Arm64LoadLane) \ 30 V(Arm64LoadSplat) \ 31 V(Arm64S128Load16x4S) \ 32 V(Arm64S128Load16x4U) \ 33 V(Arm64S128Load32x2S) \ 34 V(Arm64S128Load32x2U) \ 35 V(Arm64S128Load8x8S) \ 36 V(Arm64S128Load8x8U) \ 37 V(Arm64StoreLane) \ 38 V(Arm64Str) \ 39 V(Arm64Strb) \ 40 V(Arm64StrD) \ 41 V(Arm64Strh) \ 42 V(Arm64StrQ) \ 43 V(Arm64StrS) \ 44 V(Arm64StrW) 45 46 #define TARGET_ARCH_OPCODE_LIST(V) \ 47 TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \ 48 V(Arm64Add) \ 49 V(Arm64Add32) \ 50 V(Arm64And) \ 51 V(Arm64And32) \ 52 V(Arm64Bic) \ 53 V(Arm64Bic32) \ 54 V(Arm64Clz) \ 55 V(Arm64Clz32) \ 56 V(Arm64Cmp) \ 57 V(Arm64Cmp32) \ 58 V(Arm64Cmn) \ 59 V(Arm64Cmn32) \ 60 V(Arm64Cnt) \ 61 V(Arm64Cnt32) \ 62 V(Arm64Cnt64) \ 63 V(Arm64Tst) \ 64 V(Arm64Tst32) \ 65 V(Arm64Or) \ 66 V(Arm64Or32) \ 67 V(Arm64Orn) \ 68 V(Arm64Orn32) \ 69 V(Arm64Eor) \ 70 V(Arm64Eor32) \ 71 V(Arm64Eon) \ 72 V(Arm64Eon32) \ 73 V(Arm64Sadalp) \ 74 V(Arm64Saddlp) \ 75 V(Arm64Sub) \ 76 V(Arm64Sub32) \ 77 V(Arm64Mul) \ 78 V(Arm64Mul32) \ 79 V(Arm64Smlal) \ 80 V(Arm64Smlal2) \ 81 V(Arm64Smull) \ 82 V(Arm64Smull2) \ 83 V(Arm64Uadalp) \ 84 V(Arm64Uaddlp) \ 85 V(Arm64Umlal) \ 86 V(Arm64Umlal2) \ 87 V(Arm64Umull) \ 88 V(Arm64Umull2) \ 89 V(Arm64Madd) \ 90 V(Arm64Madd32) \ 91 V(Arm64Msub) \ 92 V(Arm64Msub32) \ 93 V(Arm64Mneg) \ 94 V(Arm64Mneg32) \ 95 V(Arm64Idiv) \ 96 V(Arm64Idiv32) \ 97 V(Arm64Udiv) \ 98 V(Arm64Udiv32) \ 99 V(Arm64Imod) \ 100 V(Arm64Imod32) \ 101 V(Arm64Umod) \ 102 V(Arm64Umod32) \ 103 V(Arm64Not) \ 104 V(Arm64Not32) \ 105 V(Arm64Lsl) \ 106 V(Arm64Lsl32) \ 107 V(Arm64Lsr) \ 108 V(Arm64Lsr32) \ 109 V(Arm64Asr) \ 110 V(Arm64Asr32) \ 111 V(Arm64Ror) \ 112 V(Arm64Ror32) \ 113 V(Arm64Mov32) \ 114 V(Arm64Sxtb32) \ 115 V(Arm64Sxth32) \ 116 V(Arm64Sxtb) \ 117 V(Arm64Sxth) \ 118 V(Arm64Sxtw) \ 119 V(Arm64Sbfx) \ 120 V(Arm64Sbfx32) \ 121 V(Arm64Ubfx) \ 122 V(Arm64Ubfx32) \ 123 V(Arm64Ubfiz32) \ 124 V(Arm64Bfi) \ 125 V(Arm64Rbit) \ 126 V(Arm64Rbit32) \ 127 V(Arm64Rev) \ 128 V(Arm64Rev32) \ 129 V(Arm64TestAndBranch32) \ 130 V(Arm64TestAndBranch) \ 131 V(Arm64CompareAndBranch32) \ 132 V(Arm64CompareAndBranch) \ 133 V(Arm64Claim) \ 134 V(Arm64Poke) \ 135 V(Arm64PokePair) \ 136 V(Arm64Peek) \ 137 V(Arm64Float32Cmp) \ 138 V(Arm64Float32Add) \ 139 V(Arm64Float32Sub) \ 140 V(Arm64Float32Mul) \ 141 V(Arm64Float32Div) \ 142 V(Arm64Float32Abs) \ 143 V(Arm64Float32Abd) \ 144 V(Arm64Float32Neg) \ 145 V(Arm64Float32Sqrt) \ 146 V(Arm64Float32Fnmul) \ 147 V(Arm64Float32RoundDown) \ 148 V(Arm64Float32Max) \ 149 V(Arm64Float32Min) \ 150 V(Arm64Float64Cmp) \ 151 V(Arm64Float64Add) \ 152 V(Arm64Float64Sub) \ 153 V(Arm64Float64Mul) \ 154 V(Arm64Float64Div) \ 155 V(Arm64Float64Mod) \ 156 V(Arm64Float64Max) \ 157 V(Arm64Float64Min) \ 158 V(Arm64Float64Abs) \ 159 V(Arm64Float64Abd) \ 160 V(Arm64Float64Neg) \ 161 V(Arm64Float64Sqrt) \ 162 V(Arm64Float64Fnmul) \ 163 V(Arm64Float64RoundDown) \ 164 V(Arm64Float32RoundUp) \ 165 V(Arm64Float64RoundUp) \ 166 V(Arm64Float64RoundTiesAway) \ 167 V(Arm64Float32RoundTruncate) \ 168 V(Arm64Float64RoundTruncate) \ 169 V(Arm64Float32RoundTiesEven) \ 170 V(Arm64Float64RoundTiesEven) \ 171 V(Arm64Float64SilenceNaN) \ 172 V(Arm64Float32ToFloat64) \ 173 V(Arm64Float64ToFloat32) \ 174 V(Arm64Float32ToInt32) \ 175 V(Arm64Float64ToInt32) \ 176 V(Arm64Float32ToUint32) \ 177 V(Arm64Float64ToUint32) \ 178 V(Arm64Float32ToInt64) \ 179 V(Arm64Float64ToInt64) \ 180 V(Arm64Float32ToUint64) \ 181 V(Arm64Float64ToUint64) \ 182 V(Arm64Int32ToFloat32) \ 183 V(Arm64Int32ToFloat64) \ 184 V(Arm64Int64ToFloat32) \ 185 V(Arm64Int64ToFloat64) \ 186 V(Arm64Uint32ToFloat32) \ 187 V(Arm64Uint32ToFloat64) \ 188 V(Arm64Uint64ToFloat32) \ 189 V(Arm64Uint64ToFloat64) \ 190 V(Arm64Float64ExtractLowWord32) \ 191 V(Arm64Float64ExtractHighWord32) \ 192 V(Arm64Float64InsertLowWord32) \ 193 V(Arm64Float64InsertHighWord32) \ 194 V(Arm64Float64MoveU64) \ 195 V(Arm64U64MoveFloat64) \ 196 V(Arm64LdrDecompressTaggedSigned) \ 197 V(Arm64LdrDecompressTaggedPointer) \ 198 V(Arm64LdrDecompressAnyTagged) \ 199 V(Arm64LdarDecompressTaggedSigned) \ 200 V(Arm64LdarDecompressTaggedPointer) \ 201 V(Arm64LdarDecompressAnyTagged) \ 202 V(Arm64StrCompressTagged) \ 203 V(Arm64StlrCompressTagged) \ 204 V(Arm64LdrDecodeSandboxedPointer) \ 205 V(Arm64StrEncodeSandboxedPointer) \ 206 V(Arm64DmbIsh) \ 207 V(Arm64DsbIsb) \ 208 V(Arm64Sxtl) \ 209 V(Arm64Sxtl2) \ 210 V(Arm64Uxtl) \ 211 V(Arm64Uxtl2) \ 212 V(Arm64FSplat) \ 213 V(Arm64FAbs) \ 214 V(Arm64FSqrt) \ 215 V(Arm64FNeg) \ 216 V(Arm64FExtractLane) \ 217 V(Arm64FReplaceLane) \ 218 V(Arm64FAdd) \ 219 V(Arm64FSub) \ 220 V(Arm64FMul) \ 221 V(Arm64FMulElement) \ 222 V(Arm64FDiv) \ 223 V(Arm64FMin) \ 224 V(Arm64FMax) \ 225 V(Arm64FEq) \ 226 V(Arm64FNe) \ 227 V(Arm64FLt) \ 228 V(Arm64FLe) \ 229 V(Arm64FGt) \ 230 V(Arm64FGe) \ 231 V(Arm64F64x2Qfma) \ 232 V(Arm64F64x2Qfms) \ 233 V(Arm64F64x2Pmin) \ 234 V(Arm64F64x2Pmax) \ 235 V(Arm64F64x2ConvertLowI32x4S) \ 236 V(Arm64F64x2ConvertLowI32x4U) \ 237 V(Arm64F64x2PromoteLowF32x4) \ 238 V(Arm64F32x4SConvertI32x4) \ 239 V(Arm64F32x4UConvertI32x4) \ 240 V(Arm64F32x4RecipApprox) \ 241 V(Arm64F32x4RecipSqrtApprox) \ 242 V(Arm64F32x4Qfma) \ 243 V(Arm64F32x4Qfms) \ 244 V(Arm64F32x4Pmin) \ 245 V(Arm64F32x4Pmax) \ 246 V(Arm64F32x4DemoteF64x2Zero) \ 247 V(Arm64ISplat) \ 248 V(Arm64IAbs) \ 249 V(Arm64INeg) \ 250 V(Arm64IExtractLane) \ 251 V(Arm64IReplaceLane) \ 252 V(Arm64I64x2Shl) \ 253 V(Arm64I64x2ShrS) \ 254 V(Arm64IAdd) \ 255 V(Arm64ISub) \ 256 V(Arm64I64x2Mul) \ 257 V(Arm64IEq) \ 258 V(Arm64INe) \ 259 V(Arm64IGtS) \ 260 V(Arm64IGeS) \ 261 V(Arm64ILtS) \ 262 V(Arm64ILeS) \ 263 V(Arm64I64x2ShrU) \ 264 V(Arm64I64x2BitMask) \ 265 V(Arm64I32x4SConvertF32x4) \ 266 V(Arm64I32x4Shl) \ 267 V(Arm64I32x4ShrS) \ 268 V(Arm64I32x4Mul) \ 269 V(Arm64Mla) \ 270 V(Arm64Mls) \ 271 V(Arm64IMinS) \ 272 V(Arm64IMaxS) \ 273 V(Arm64I32x4UConvertF32x4) \ 274 V(Arm64I32x4ShrU) \ 275 V(Arm64IMinU) \ 276 V(Arm64IMaxU) \ 277 V(Arm64IGtU) \ 278 V(Arm64IGeU) \ 279 V(Arm64I32x4BitMask) \ 280 V(Arm64I32x4DotI16x8S) \ 281 V(Arm64I32x4TruncSatF64x2SZero) \ 282 V(Arm64I32x4TruncSatF64x2UZero) \ 283 V(Arm64IExtractLaneU) \ 284 V(Arm64IExtractLaneS) \ 285 V(Arm64I16x8Shl) \ 286 V(Arm64I16x8ShrS) \ 287 V(Arm64I16x8SConvertI32x4) \ 288 V(Arm64IAddSatS) \ 289 V(Arm64ISubSatS) \ 290 V(Arm64I16x8Mul) \ 291 V(Arm64I16x8ShrU) \ 292 V(Arm64I16x8UConvertI32x4) \ 293 V(Arm64IAddSatU) \ 294 V(Arm64ISubSatU) \ 295 V(Arm64RoundingAverageU) \ 296 V(Arm64I16x8Q15MulRSatS) \ 297 V(Arm64I16x8BitMask) \ 298 V(Arm64I8x16Shl) \ 299 V(Arm64I8x16ShrS) \ 300 V(Arm64I8x16SConvertI16x8) \ 301 V(Arm64I8x16ShrU) \ 302 V(Arm64I8x16UConvertI16x8) \ 303 V(Arm64I8x16BitMask) \ 304 V(Arm64S128Const) \ 305 V(Arm64S128Zero) \ 306 V(Arm64S128Dup) \ 307 V(Arm64S128And) \ 308 V(Arm64S128Or) \ 309 V(Arm64S128Xor) \ 310 V(Arm64S128Not) \ 311 V(Arm64S128Select) \ 312 V(Arm64S128AndNot) \ 313 V(Arm64Ssra) \ 314 V(Arm64Usra) \ 315 V(Arm64S32x4ZipLeft) \ 316 V(Arm64S32x4ZipRight) \ 317 V(Arm64S32x4UnzipLeft) \ 318 V(Arm64S32x4UnzipRight) \ 319 V(Arm64S32x4TransposeLeft) \ 320 V(Arm64S32x4TransposeRight) \ 321 V(Arm64S32x4Shuffle) \ 322 V(Arm64S16x8ZipLeft) \ 323 V(Arm64S16x8ZipRight) \ 324 V(Arm64S16x8UnzipLeft) \ 325 V(Arm64S16x8UnzipRight) \ 326 V(Arm64S16x8TransposeLeft) \ 327 V(Arm64S16x8TransposeRight) \ 328 V(Arm64S8x16ZipLeft) \ 329 V(Arm64S8x16ZipRight) \ 330 V(Arm64S8x16UnzipLeft) \ 331 V(Arm64S8x16UnzipRight) \ 332 V(Arm64S8x16TransposeLeft) \ 333 V(Arm64S8x16TransposeRight) \ 334 V(Arm64S8x16Concat) \ 335 V(Arm64I8x16Swizzle) \ 336 V(Arm64I8x16Shuffle) \ 337 V(Arm64S32x2Reverse) \ 338 V(Arm64S16x4Reverse) \ 339 V(Arm64S16x2Reverse) \ 340 V(Arm64S8x8Reverse) \ 341 V(Arm64S8x4Reverse) \ 342 V(Arm64S8x2Reverse) \ 343 V(Arm64V128AnyTrue) \ 344 V(Arm64I64x2AllTrue) \ 345 V(Arm64I32x4AllTrue) \ 346 V(Arm64I16x8AllTrue) \ 347 V(Arm64I8x16AllTrue) \ 348 V(Arm64Word64AtomicLoadUint64) \ 349 V(Arm64Word64AtomicStoreWord64) \ 350 V(Arm64Word64AtomicAddUint64) \ 351 V(Arm64Word64AtomicSubUint64) \ 352 V(Arm64Word64AtomicAndUint64) \ 353 V(Arm64Word64AtomicOrUint64) \ 354 V(Arm64Word64AtomicXorUint64) \ 355 V(Arm64Word64AtomicExchangeUint64) \ 356 V(Arm64Word64AtomicCompareExchangeUint64) 357 358 // Addressing modes represent the "shape" of inputs to an instruction. 359 // Many instructions support multiple addressing modes. Addressing modes 360 // are encoded into the InstructionCode of the instruction and tell the 361 // code generator after register allocation which assembler method to call. 362 // 363 // We use the following local notation for addressing modes: 364 // 365 // R = register 366 // O = register or stack slot 367 // D = double register 368 // I = immediate (handle, external, int32) 369 // MRI = [register + immediate] 370 // MRR = [register + register] 371 #define TARGET_ADDRESSING_MODE_LIST(V) \ 372 V(MRI) /* [%r0 + K] */ \ 373 V(MRR) /* [%r0 + %r1] */ \ 374 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ 375 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ 376 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 377 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ 378 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \ 379 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */ \ 380 V(Operand2_R_SXTB) /* %r0 SXTB (signed extend byte) */ \ 381 V(Operand2_R_SXTH) /* %r0 SXTH (signed extend halfword) */ \ 382 V(Operand2_R_SXTW) /* %r0 SXTW (signed extend word) */ \ 383 V(Root) /* [%rr + K] */ 384 385 } // namespace compiler 386 } // namespace internal 387 } // namespace v8 388 389 #endif // V8_COMPILER_BACKEND_ARM64_INSTRUCTION_CODES_ARM64_H_ 390