| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v10_0.c | 35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
[all …]
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| D | imu_v11_0.c | 31 #include "gc/gc_11_0_0_offset.h"
32 #include "gc/gc_11_0_0_sh_mask.h"
100 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v11_0_load_microcode()
103 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v11_0_load_microcode()
105 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
112 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v11_0_load_microcode()
115 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v11_0_load_microcode()
117 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
127 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v11_0_wait_for_reset_status()
146 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); in imu_v11_0_setup()
[all …]
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| D | imu_v11_0_3.c | 27 #include "gc/gc_11_0_3_offset.h"
28 #include "gc/gc_11_0_3_sh_mask.h"
31 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
32 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
33 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
34 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
35 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000),
36 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
37 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
38 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
[all …]
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| D | gfxhub_v1_2.c | 28 #include "gc/gc_9_4_3_offset.h"
29 #include "gc/gc_9_4_3_sh_mask.h"
39 return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24; in gfxhub_v1_2_get_mc_fb_offset()
52 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_setup_vm_pt_regs()
57 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_setup_vm_pt_regs()
92 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
95 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
99 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
102 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
106 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
[all …]
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| D | gfx_v9_4.c | 33 #include "gc/gc_9_4_1_offset.h"
34 #include "gc/gc_9_4_1_sh_mask.h"
42 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
43 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
45 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
46 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
47 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
49 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
50 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
52 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
[all …]
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| D | gfxhub_v2_1.c | 27 #include "gc/gc_10_3_0_offset.h"
28 #include "gc/gc_10_3_0_sh_mask.h"
29 #include "gc/gc_10_3_0_default.h"
110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_1_get_fb_location()
120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_1_get_mc_fb_offset()
128 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_1_setup_vm_pt_regs()
132 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_1_setup_vm_pt_regs()
143 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs()
145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_1_init_gart_aperture_regs()
148 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs()
[all …]
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| D | gfx_v9_4_2.c | 27 #include "gc/gc_9_4_2_offset.h"
28 #include "gc/gc_9_4_2_sh_mask.h"
64 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920),
65 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0x3b458b93),
66 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x1a4f5583),
67 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0x317717f6),
68 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x107cc1e6),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x351),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x2591aa38),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0xac9e88b),
[all …]
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| D | gfxhub_v1_0.c | 27 #include "gc/gc_9_0_offset.h"
28 #include "gc/gc_9_0_sh_mask.h"
29 #include "gc/gc_9_0_default.h"
36 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; in gfxhub_v1_0_get_mc_fb_offset()
45 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v1_0_setup_vm_pt_regs()
49 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v1_0_setup_vm_pt_regs()
69 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
71 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
74 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
76 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v10_0.c | 36 #include "gc/gc_10_1_0_offset.h"
37 #include "gc/gc_10_1_0_sh_mask.h"
176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
[all …]
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| D | gfx_v9_4.c | 33 #include "gc/gc_9_4_1_offset.h"
34 #include "gc/gc_9_4_1_sh_mask.h"
42 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
43 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
45 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
46 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
47 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
49 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
50 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
52 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
[all …]
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| D | gfxhub_v1_0.c | 26 #include "gc/gc_9_0_offset.h"
27 #include "gc/gc_9_0_sh_mask.h"
28 #include "gc/gc_9_0_default.h"
35 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; in gfxhub_v1_0_get_mc_fb_offset()
43 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v1_0_setup_vm_pt_regs()
47 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v1_0_setup_vm_pt_regs()
58 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
60 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
63 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-mmio.c | 127 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) in bgpio_line2mask() argument
129 if (gc->be_bits) in bgpio_line2mask()
130 return BIT(gc->bgpio_bits - 1 - line); in bgpio_line2mask()
134 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) in bgpio_get_set() argument
136 unsigned long pinmask = bgpio_line2mask(gc, gpio); in bgpio_get_set()
137 bool dir = !!(gc->bgpio_dir & pinmask); in bgpio_get_set()
140 return !!(gc->read_reg(gc->reg_set) & pinmask); in bgpio_get_set()
142 return !!(gc->read_reg(gc->reg_dat) & pinmask); in bgpio_get_set()
149 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, in bgpio_get_set_multiple() argument
158 set_mask = *mask & gc->bgpio_dir; in bgpio_get_set_multiple()
[all …]
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| D | gpiolib.c | 101 static void gpiochip_free_hogs(struct gpio_chip *gc);
102 static int gpiochip_add_irqchip(struct gpio_chip *gc,
105 static void gpiochip_irqchip_remove(struct gpio_chip *gc);
106 static int gpiochip_irqchip_init_hw(struct gpio_chip *gc);
107 static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gc);
108 static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gc);
152 * @gc: GPIO chip
159 struct gpio_desc *gpiochip_get_desc(struct gpio_chip *gc, in gpiochip_get_desc() argument
162 struct gpio_device *gdev = gc->gpiodev; in gpiochip_get_desc()
235 struct gpio_chip *gc; in gpiod_get_direction() local
[all …]
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-mmio.c | 125 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) in bgpio_line2mask() argument
127 if (gc->be_bits) in bgpio_line2mask()
128 return BIT(gc->bgpio_bits - 1 - line); in bgpio_line2mask()
132 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) in bgpio_get_set() argument
134 unsigned long pinmask = bgpio_line2mask(gc, gpio); in bgpio_get_set()
135 bool dir = !!(gc->bgpio_dir & pinmask); in bgpio_get_set()
138 return !!(gc->read_reg(gc->reg_set) & pinmask); in bgpio_get_set()
140 return !!(gc->read_reg(gc->reg_dat) & pinmask); in bgpio_get_set()
147 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, in bgpio_get_set_multiple() argument
156 set_mask = *mask & gc->bgpio_dir; in bgpio_get_set_multiple()
[all …]
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| D | gpiolib.c | 80 static void gpiochip_free_hogs(struct gpio_chip *gc);
81 static int gpiochip_add_irqchip(struct gpio_chip *gc,
84 static void gpiochip_irqchip_remove(struct gpio_chip *gc);
85 static int gpiochip_irqchip_init_hw(struct gpio_chip *gc);
86 static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gc);
87 static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gc);
131 * @gc: GPIO chip
138 struct gpio_desc *gpiochip_get_desc(struct gpio_chip *gc, in gpiochip_get_desc() argument
141 struct gpio_device *gdev = gc->gpiodev; in gpiochip_get_desc()
212 struct gpio_chip *gc; in gpiod_get_direction() local
[all …]
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| /kernel/linux/linux-5.10/drivers/lightnvm/ |
| D | pblk-gc.c | 16 * pblk-gc.c - pblk's garbage collector
33 struct pblk_gc *gc = &pblk->gc; in pblk_gc_write() local
37 spin_lock(&gc->w_lock); in pblk_gc_write()
38 if (list_empty(&gc->w_list)) { in pblk_gc_write()
39 spin_unlock(&gc->w_lock); in pblk_gc_write()
43 list_cut_position(&w_list, &gc->w_list, gc->w_list.prev); in pblk_gc_write()
44 gc->w_entries = 0; in pblk_gc_write()
45 spin_unlock(&gc->w_lock); in pblk_gc_write()
57 static void pblk_gc_writer_kick(struct pblk_gc *gc) in pblk_gc_writer_kick() argument
59 wake_up_process(gc->gc_writer_ts); in pblk_gc_writer_kick()
[all …]
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| /kernel/linux/linux-5.10/kernel/irq/ |
| D | generic-chip.c | 38 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in irq_gc_mask_disable_reg() local
42 irq_gc_lock(gc); in irq_gc_mask_disable_reg()
43 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_reg()
45 irq_gc_unlock(gc); in irq_gc_mask_disable_reg()
53 * and protected by gc->lock
57 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in irq_gc_mask_set_bit() local
61 irq_gc_lock(gc); in irq_gc_mask_set_bit()
63 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); in irq_gc_mask_set_bit()
64 irq_gc_unlock(gc); in irq_gc_mask_set_bit()
73 * and protected by gc->lock
[all …]
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| /kernel/linux/linux-6.6/kernel/irq/ |
| D | generic-chip.c | 39 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in irq_gc_mask_disable_reg() local
43 irq_gc_lock(gc); in irq_gc_mask_disable_reg()
44 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_reg()
46 irq_gc_unlock(gc); in irq_gc_mask_disable_reg()
55 * and protected by gc->lock
59 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in irq_gc_mask_set_bit() local
63 irq_gc_lock(gc); in irq_gc_mask_set_bit()
65 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); in irq_gc_mask_set_bit()
66 irq_gc_unlock(gc); in irq_gc_mask_set_bit()
75 * and protected by gc->lock
[all …]
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| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-atmel-aic.c | 63 struct irq_domain_chip_generic *dgc = aic_domain->gc; in aic_handle()
64 struct irq_chip_generic *gc = dgc->gc[0]; in aic_handle() local
68 irqnr = irq_reg_readl(gc, AT91_AIC_IVR); in aic_handle()
69 irqstat = irq_reg_readl(gc, AT91_AIC_ISR); in aic_handle()
72 irq_reg_writel(gc, 0, AT91_AIC_EOICR); in aic_handle()
79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in aic_retrigger() local
82 irq_gc_lock(gc); in aic_retrigger()
83 irq_reg_writel(gc, d->mask, AT91_AIC_ISCR); in aic_retrigger()
84 irq_gc_unlock(gc); in aic_retrigger()
91 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in aic_set_type() local
[all …]
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| D | irq-tb10x.c | 30 static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg, in ab_irqctl_writereg() argument
33 irq_reg_writel(gc, val, reg); in ab_irqctl_writereg()
36 static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg) in ab_irqctl_readreg() argument
38 return irq_reg_readl(gc, reg); in ab_irqctl_readreg()
43 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); in tb10x_irq_set_type() local
48 irq_gc_lock(gc); in tb10x_irq_set_type()
50 mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im; in tb10x_irq_set_type()
51 pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im; in tb10x_irq_set_type()
70 irq_gc_unlock(gc); in tb10x_irq_set_type()
79 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod); in tb10x_irq_set_type()
[all …]
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| D | irq-sunxi-nmi.c | 75 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off, in sunxi_sc_nmi_write() argument
78 irq_reg_writel(gc, val, off); in sunxi_sc_nmi_write()
81 static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off) in sunxi_sc_nmi_read() argument
83 return irq_reg_readl(gc, off); in sunxi_sc_nmi_read()
98 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); in sunxi_sc_nmi_set_type() local
99 struct irq_chip_type *ct = gc->chip_types; in sunxi_sc_nmi_set_type()
105 irq_gc_lock(gc); in sunxi_sc_nmi_set_type()
122 irq_gc_unlock(gc); in sunxi_sc_nmi_set_type()
131 for (i = 0; i < gc->num_ct; i++, ct++) in sunxi_sc_nmi_set_type()
135 src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off); in sunxi_sc_nmi_set_type()
[all …]
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-atmel-aic.c | 63 struct irq_domain_chip_generic *dgc = aic_domain->gc; in aic_handle()
64 struct irq_chip_generic *gc = dgc->gc[0]; in aic_handle() local
68 irqnr = irq_reg_readl(gc, AT91_AIC_IVR); in aic_handle()
69 irqstat = irq_reg_readl(gc, AT91_AIC_ISR); in aic_handle()
72 irq_reg_writel(gc, 0, AT91_AIC_EOICR); in aic_handle()
79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in aic_retrigger() local
82 irq_gc_lock(gc); in aic_retrigger()
83 irq_reg_writel(gc, d->mask, AT91_AIC_ISCR); in aic_retrigger()
84 irq_gc_unlock(gc); in aic_retrigger()
91 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in aic_set_type() local
[all …]
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| D | irq-tb10x.c | 31 static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg, in ab_irqctl_writereg() argument
34 irq_reg_writel(gc, val, reg); in ab_irqctl_writereg()
37 static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg) in ab_irqctl_readreg() argument
39 return irq_reg_readl(gc, reg); in ab_irqctl_readreg()
44 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); in tb10x_irq_set_type() local
49 irq_gc_lock(gc); in tb10x_irq_set_type()
51 mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im; in tb10x_irq_set_type()
52 pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im; in tb10x_irq_set_type()
70 irq_gc_unlock(gc); in tb10x_irq_set_type()
79 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod); in tb10x_irq_set_type()
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| /kernel/linux/linux-6.6/drivers/net/ethernet/microsoft/mana/ |
| D | gdma_main.c | 23 struct gdma_context *gc = pci_get_drvdata(pdev); in mana_gd_init_pf_regs() local
27 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF; in mana_gd_init_pf_regs()
28 gc->db_page_base = gc->bar0_va + in mana_gd_init_pf_regs()
29 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF); in mana_gd_init_pf_regs()
31 sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF); in mana_gd_init_pf_regs()
33 sriov_base_va = gc->bar0_va + sriov_base_off; in mana_gd_init_pf_regs()
34 gc->shm_base = sriov_base_va + in mana_gd_init_pf_regs()
35 mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF); in mana_gd_init_pf_regs()
40 struct gdma_context *gc = pci_get_drvdata(pdev); in mana_gd_init_vf_regs() local
42 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; in mana_gd_init_vf_regs()
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| /kernel/linux/linux-5.10/drivers/input/joystick/ |
| D | gamecon.c | 73 struct gc { struct
87 static struct gc *gc_base[3]; argument
133 static void gc_n64_send_command(struct gc *gc, unsigned long cmd, in gc_n64_send_command() argument
136 struct parport *port = gc->pd->port; in gc_n64_send_command()
147 static void gc_n64_send_stop_bit(struct gc *gc, unsigned char target) in gc_n64_send_stop_bit() argument
149 struct parport *port = gc->pd->port; in gc_n64_send_stop_bit()
165 static void gc_n64_read_packet(struct gc *gc, unsigned char *data) in gc_n64_read_packet() argument
175 gc_n64_send_command(gc, GC_N64_REQUEST_DATA, GC_N64_OUT); in gc_n64_read_packet()
176 gc_n64_send_stop_bit(gc, GC_N64_OUT); in gc_n64_read_packet()
191 parport_write_data(gc->pd->port, GC_N64_POWER_R); in gc_n64_read_packet()
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