1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Rockchip Electronics Co.Ltd
4 * Author: Andy Yan <andy.yan@rock-chips.com>
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/component.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <dt-bindings/display/rockchip_vop.h>
12
13 #include <drm/drm_fourcc.h>
14 #include <drm/drm_print.h>
15 #include "rockchip_drm_vop.h"
16 #include "rockchip_vop_reg.h"
17 #include "rockchip_drm_drv.h"
18
19 #define _VOP_REG(off, _mask, _shift, _write_mask) \
20 { \
21 .offset = off, \
22 .mask = _mask, \
23 .shift = _shift, \
24 .write_mask = _write_mask, \
25 }
26
27 #define VOP_REG(off, _mask, _shift) \
28 _VOP_REG(off, _mask, _shift, false)
29
30 #define VOP_REG_MASK(off, _mask, s) \
31 _VOP_REG(off, _mask, s, true)
32
33 static const uint32_t formats_for_cluster[] = {
34 DRM_FORMAT_XRGB2101010,
35 DRM_FORMAT_ARGB2101010,
36 DRM_FORMAT_XBGR2101010,
37 DRM_FORMAT_ABGR2101010,
38 DRM_FORMAT_XRGB8888,
39 DRM_FORMAT_ARGB8888,
40 DRM_FORMAT_XBGR8888,
41 DRM_FORMAT_ABGR8888,
42 DRM_FORMAT_RGB888,
43 DRM_FORMAT_BGR888,
44 DRM_FORMAT_RGB565,
45 DRM_FORMAT_BGR565,
46 DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
47 DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
48 DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
49 DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
50 #ifdef CONFIG_NO_GKI
51 DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
52 DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
53 #endif
54 DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
55 DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
56 DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
57 DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
58 };
59
60 static const uint32_t formats_for_esmart[] = {
61 DRM_FORMAT_XRGB8888,
62 DRM_FORMAT_ARGB8888,
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_RGB888,
66 DRM_FORMAT_BGR888,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_BGR565,
69 DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
70 DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */
71 DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
72 DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */
73 DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
74 DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */
75 DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
76 #ifdef CONFIG_NO_GKI
77 DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
78 DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
79 #endif
80 DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode */
81 DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */
82 DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */
83 DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */
84 };
85
86 /* RK356x can't support uv swap for YUYV and UYVY */
87 static const uint32_t formats_for_rk356x_esmart[] = {
88 DRM_FORMAT_XRGB8888,
89 DRM_FORMAT_ARGB8888,
90 DRM_FORMAT_XBGR8888,
91 DRM_FORMAT_ABGR8888,
92 DRM_FORMAT_RGB888,
93 DRM_FORMAT_BGR888,
94 DRM_FORMAT_RGB565,
95 DRM_FORMAT_BGR565,
96 DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
97 DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
98 DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
99 DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
100 #ifdef CONFIG_NO_GKI
101 DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
102 DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
103 #endif
104 DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */
105 DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */
106 };
107
108 static const uint32_t formats_for_smart[] = {
109 DRM_FORMAT_XRGB8888,
110 DRM_FORMAT_ARGB8888,
111 DRM_FORMAT_XBGR8888,
112 DRM_FORMAT_ABGR8888,
113 DRM_FORMAT_RGB888,
114 DRM_FORMAT_BGR888,
115 DRM_FORMAT_RGB565,
116 DRM_FORMAT_BGR565,
117 };
118
119 static const u32 formats_wb[] = {
120 DRM_FORMAT_BGR888,
121 DRM_FORMAT_ARGB8888,
122 DRM_FORMAT_RGB565,
123 DRM_FORMAT_NV12,
124 };
125
126 static const uint64_t format_modifiers[] = {
127 DRM_FORMAT_MOD_LINEAR,
128 DRM_FORMAT_MOD_INVALID,
129 };
130
131 static const uint64_t format_modifiers_afbc[] = {
132 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16),
133
134 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
135 AFBC_FORMAT_MOD_SPARSE),
136
137 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
138 AFBC_FORMAT_MOD_YTR),
139
140 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
141 AFBC_FORMAT_MOD_CBR),
142
143 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
144 AFBC_FORMAT_MOD_YTR |
145 AFBC_FORMAT_MOD_SPARSE),
146
147 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
148 AFBC_FORMAT_MOD_CBR |
149 AFBC_FORMAT_MOD_SPARSE),
150
151 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
152 AFBC_FORMAT_MOD_YTR |
153 AFBC_FORMAT_MOD_CBR),
154
155 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
156 AFBC_FORMAT_MOD_YTR |
157 AFBC_FORMAT_MOD_CBR |
158 AFBC_FORMAT_MOD_SPARSE),
159
160 /* SPLIT mandates SPARSE, RGB modes mandates YTR */
161 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
162 AFBC_FORMAT_MOD_YTR |
163 AFBC_FORMAT_MOD_SPARSE |
164 AFBC_FORMAT_MOD_SPLIT),
165
166 DRM_FORMAT_MOD_LINEAR,
167 DRM_FORMAT_MOD_INVALID,
168 };
169
170 static const u32 sdr2hdr_bt1886eotf_yn_for_hlg_hdr[65] = {
171 0,
172 1, 7, 17, 35,
173 60, 92, 134, 184,
174 244, 315, 396, 487,
175 591, 706, 833, 915,
176 1129, 1392, 1717, 2118,
177 2352, 2612, 2900, 3221,
178 3577, 3972, 4411, 4899,
179 5441, 6042, 6710, 7452,
180 7853, 8276, 8721, 9191,
181 9685, 10207, 10756, 11335,
182 11945, 12588, 13266, 13980,
183 14732, 15525, 16361, 17241,
184 17699, 18169, 18652, 19147,
185 19656, 20178, 20714, 21264,
186 21829, 22408, 23004, 23615,
187 24242, 24886, 25547, 26214,
188 };
189
190 static const u32 sdr2hdr_bt1886eotf_yn_for_bt2020[65] = {
191 0,
192 1820, 3640, 5498, 7674,
193 10256, 13253, 16678, 20539,
194 24847, 29609, 34833, 40527,
195 46699, 53354, 60499, 68141,
196 76285, 84937, 94103, 103787,
197 108825, 113995, 119296, 124731,
198 130299, 136001, 141837, 147808,
199 153915, 160158, 166538, 173055,
200 176365, 179709, 183089, 186502,
201 189951, 193434, 196952, 200505,
202 204093, 207715, 211373, 215066,
203 218795, 222558, 226357, 230191,
204 232121, 234060, 236008, 237965,
205 239931, 241906, 243889, 245882,
206 247883, 249894, 251913, 253941,
207 255978, 258024, 260079, 262143,
208 };
209
210 static u32 sdr2hdr_bt1886eotf_yn_for_hdr[65] = {
211 /* dst_range 425int */
212 0,
213 5, 21, 49, 91,
214 150, 225, 320, 434,
215 569, 726, 905, 1108,
216 1336, 1588, 1866, 2171,
217 2502, 2862, 3250, 3667,
218 3887, 4114, 4349, 4591,
219 4841, 5099, 5364, 5638,
220 5920, 6209, 6507, 6812,
221 6968, 7126, 7287, 7449,
222 7613, 7779, 7948, 8118,
223 8291, 8466, 8643, 8822,
224 9003, 9187, 9372, 9560,
225 9655, 9750, 9846, 9942,
226 10039, 10136, 10234, 10333,
227 10432, 10531, 10631, 10732,
228 10833, 10935, 11038, 11141,
229 };
230
231 static const u32 sdr2hdr_st2084oetf_yn_for_hlg_hdr[65] = {
232 0,
233 668, 910, 1217, 1600,
234 2068, 2384, 2627, 3282,
235 3710, 4033, 4879, 5416,
236 5815, 6135, 6401, 6631,
237 6833, 7176, 7462, 7707,
238 7921, 8113, 8285, 8442,
239 8586, 8843, 9068, 9268,
240 9447, 9760, 10027, 10259,
241 10465, 10650, 10817, 10971,
242 11243, 11480, 11689, 11877,
243 12047, 12202, 12345, 12477,
244 12601, 12716, 12926, 13115,
245 13285, 13441, 13583, 13716,
246 13839, 13953, 14163, 14350,
247 14519, 14673, 14945, 15180,
248 15570, 15887, 16153, 16383,
249 };
250
251 static const u32 sdr2hdr_st2084oetf_yn_for_bt2020[65] = {
252 0,
253 0, 0, 1, 2,
254 4, 6, 9, 18,
255 27, 36, 72, 108,
256 144, 180, 216, 252,
257 288, 360, 432, 504,
258 576, 648, 720, 792,
259 864, 1008, 1152, 1296,
260 1444, 1706, 1945, 2166,
261 2372, 2566, 2750, 2924,
262 3251, 3553, 3834, 4099,
263 4350, 4588, 4816, 5035,
264 5245, 5447, 5832, 6194,
265 6536, 6862, 7173, 7471,
266 7758, 8035, 8560, 9055,
267 9523, 9968, 10800, 11569,
268 12963, 14210, 15347, 16383,
269 };
270
271 static u32 sdr2hdr_st2084oetf_yn_for_hdr[65] = {
272 0,
273 281, 418, 610, 871,
274 1217, 1464, 1662, 2218,
275 2599, 2896, 3699, 4228,
276 4628, 4953, 5227, 5466,
277 5676, 6038, 6341, 6602,
278 6833, 7039, 7226, 7396,
279 7554, 7835, 8082, 8302,
280 8501, 8848, 9145, 9405,
281 9635, 9842, 10031, 10204,
282 10512, 10779, 11017, 11230,
283 11423, 11599, 11762, 11913,
284 12054, 12185, 12426, 12641,
285 12835, 13013, 13177, 13328,
286 13469, 13600, 13840, 14055,
287 14248, 14425, 14737, 15006,
288 15453, 15816, 16121, 16383,
289 };
290
291 static const u32 sdr2hdr_st2084oetf_dxn_pow2[64] = {
292 0, 0, 1, 2,
293 3, 3, 3, 5,
294 5, 5, 7, 7,
295 7, 7, 7, 7,
296 7, 8, 8, 8,
297 8, 8, 8, 8,
298 8, 9, 9, 9,
299 9, 10, 10, 10,
300 10, 10, 10, 10,
301 11, 11, 11, 11,
302 11, 11, 11, 11,
303 11, 11, 12, 12,
304 12, 12, 12, 12,
305 12, 12, 13, 13,
306 13, 13, 14, 14,
307 15, 15, 15, 15,
308 };
309
310 static const u32 sdr2hdr_st2084oetf_dxn[64] = {
311 1, 1, 2, 4,
312 8, 8, 8, 32,
313 32, 32, 128, 128,
314 128, 128, 128, 128,
315 128, 256, 256, 256,
316 256, 256, 256, 256,
317 256, 512, 512, 512,
318 512, 1024, 1024, 1024,
319 1024, 1024, 1024, 1024,
320 2048, 2048, 2048, 2048,
321 2048, 2048, 2048, 2048,
322 2048, 2048, 4096, 4096,
323 4096, 4096, 4096, 4096,
324 4096, 4096, 8192, 8192,
325 8192, 8192, 16384, 16384,
326 32768, 32768, 32768, 32768,
327 };
328
329 static const u32 sdr2hdr_st2084oetf_xn[63] = {
330 1, 2, 4, 8,
331 16, 24, 32, 64,
332 96, 128, 256, 384,
333 512, 640, 768, 896,
334 1024, 1280, 1536, 1792,
335 2048, 2304, 2560, 2816,
336 3072, 3584, 4096, 4608,
337 5120, 6144, 7168, 8192,
338 9216, 10240, 11264, 12288,
339 14336, 16384, 18432, 20480,
340 22528, 24576, 26624, 28672,
341 30720, 32768, 36864, 40960,
342 45056, 49152, 53248, 57344,
343 61440, 65536, 73728, 81920,
344 90112, 98304, 114688, 131072,
345 163840, 196608, 229376,
346 };
347
348 static u32 hdr2sdr_eetf_yn[33] = {
349 1716,
350 1880, 2067, 2277, 2508,
351 2758, 3026, 3310, 3609,
352 3921, 4246, 4581, 4925,
353 5279, 5640, 6007, 6380,
354 6758, 7140, 7526, 7914,
355 8304, 8694, 9074, 9438,
356 9779, 10093, 10373, 10615,
357 10812, 10960, 11053, 11084,
358 };
359
360 static u32 hdr2sdr_bt1886oetf_yn[33] = {
361 0,
362 0, 0, 0, 0,
363 0, 0, 0, 314,
364 746, 1323, 2093, 2657,
365 3120, 3519, 3874, 4196,
366 4492, 5024, 5498, 5928,
367 6323, 7034, 7666, 8239,
368 8766, 9716, 10560, 11325,
369 12029, 13296, 14422, 16383,
370 };
371
372 static const u32 hdr2sdr_sat_yn[9] = {
373 0,
374 1792, 3584, 3472, 2778,
375 2083, 1389, 694, 0,
376 };
377
378 static const struct vop_hdr_table rk3568_vop_hdr_table = {
379 .hdr2sdr_eetf_yn = hdr2sdr_eetf_yn,
380 .hdr2sdr_bt1886oetf_yn = hdr2sdr_bt1886oetf_yn,
381 .hdr2sdr_sat_yn = hdr2sdr_sat_yn,
382
383 .hdr2sdr_src_range_min = 494,
384 .hdr2sdr_src_range_max = 12642,
385 .hdr2sdr_normfaceetf = 1327,
386 .hdr2sdr_dst_range_min = 4,
387 .hdr2sdr_dst_range_max = 3276,
388 .hdr2sdr_normfacgamma = 5120,
389
390 .sdr2hdr_bt1886eotf_yn_for_hlg_hdr = sdr2hdr_bt1886eotf_yn_for_hlg_hdr,
391 .sdr2hdr_bt1886eotf_yn_for_bt2020 = sdr2hdr_bt1886eotf_yn_for_bt2020,
392 .sdr2hdr_bt1886eotf_yn_for_hdr = sdr2hdr_bt1886eotf_yn_for_hdr,
393 .sdr2hdr_st2084oetf_yn_for_hlg_hdr = sdr2hdr_st2084oetf_yn_for_hlg_hdr,
394 .sdr2hdr_st2084oetf_yn_for_bt2020 = sdr2hdr_st2084oetf_yn_for_bt2020,
395 .sdr2hdr_st2084oetf_yn_for_hdr = sdr2hdr_st2084oetf_yn_for_hdr,
396 .sdr2hdr_st2084oetf_dxn_pow2 = sdr2hdr_st2084oetf_dxn_pow2,
397 .sdr2hdr_st2084oetf_dxn = sdr2hdr_st2084oetf_dxn,
398 .sdr2hdr_st2084oetf_xn = sdr2hdr_st2084oetf_xn,
399 };
400
401 static const int rk3568_vop_axi_intrs[] = {
402 0,
403 BUS_ERROR_INTR,
404 0,
405 WB_UV_FIFO_FULL_INTR,
406 WB_YRGB_FIFO_FULL_INTR,
407 WB_COMPLETE_INTR,
408
409 };
410
411 static const struct vop_intr rk3568_vop_axi_intr[] = {
412 {
413 .intrs = rk3568_vop_axi_intrs,
414 .nintrs = ARRAY_SIZE(rk3568_vop_axi_intrs),
415 .status = VOP_REG(RK3568_SYS0_INT_STATUS, 0xfe, 0),
416 .enable = VOP_REG_MASK(RK3568_SYS0_INT_EN, 0xfe, 0),
417 .clear = VOP_REG_MASK(RK3568_SYS0_INT_CLR, 0xfe, 0),
418 },
419
420 {
421 .intrs = rk3568_vop_axi_intrs,
422 .nintrs = ARRAY_SIZE(rk3568_vop_axi_intrs),
423 .status = VOP_REG(RK3568_SYS1_INT_STATUS, 0xfe, 0),
424 .enable = VOP_REG_MASK(RK3568_SYS1_INT_EN, 0xfe, 0),
425 .clear = VOP_REG_MASK(RK3568_SYS1_INT_CLR, 0xfe, 0),
426 },
427 };
428
429 static const int rk3568_vop_intrs[] = {
430 FS_INTR,
431 FS_NEW_INTR,
432 LINE_FLAG_INTR,
433 LINE_FLAG1_INTR,
434 POST_BUF_EMPTY_INTR,
435 FS_FIELD_INTR,
436 DSP_HOLD_VALID_INTR,
437 };
438
439 static const struct vop_intr rk3568_vp0_intr = {
440 .intrs = rk3568_vop_intrs,
441 .nintrs = ARRAY_SIZE(rk3568_vop_intrs),
442 .line_flag_num[0] = VOP_REG(RK3568_VP0_LINE_FLAG, 0x1fff, 0),
443 .line_flag_num[1] = VOP_REG(RK3568_VP0_LINE_FLAG, 0x1fff, 16),
444 .status = VOP_REG(RK3568_VP0_INT_STATUS, 0xffff, 0),
445 .enable = VOP_REG_MASK(RK3568_VP0_INT_EN, 0xffff, 0),
446 .clear = VOP_REG_MASK(RK3568_VP0_INT_CLR, 0xffff, 0),
447 };
448
449 static const struct vop_intr rk3568_vp1_intr = {
450 .intrs = rk3568_vop_intrs,
451 .nintrs = ARRAY_SIZE(rk3568_vop_intrs),
452 .line_flag_num[0] = VOP_REG(RK3568_VP1_LINE_FLAG, 0x1fff, 0),
453 .line_flag_num[1] = VOP_REG(RK3568_VP1_LINE_FLAG, 0x1fff, 16),
454 .status = VOP_REG(RK3568_VP1_INT_STATUS, 0xffff, 0),
455 .enable = VOP_REG_MASK(RK3568_VP1_INT_EN, 0xffff, 0),
456 .clear = VOP_REG_MASK(RK3568_VP1_INT_CLR, 0xffff, 0),
457 };
458
459 static const struct vop_intr rk3568_vp2_intr = {
460 .intrs = rk3568_vop_intrs,
461 .nintrs = ARRAY_SIZE(rk3568_vop_intrs),
462 .line_flag_num[0] = VOP_REG(RK3568_VP2_LINE_FLAG, 0x1fff, 0),
463 .line_flag_num[1] = VOP_REG(RK3568_VP2_LINE_FLAG, 0x1fff, 16),
464 .status = VOP_REG(RK3568_VP2_INT_STATUS, 0xffff, 0),
465 .enable = VOP_REG_MASK(RK3568_VP2_INT_EN, 0xffff, 0),
466 .clear = VOP_REG_MASK(RK3568_VP2_INT_CLR, 0xffff, 0),
467 };
468
469 static const struct vop_intr rk3588_vp3_intr = {
470 .intrs = rk3568_vop_intrs,
471 .nintrs = ARRAY_SIZE(rk3568_vop_intrs),
472 .line_flag_num[0] = VOP_REG(RK3588_VP3_LINE_FLAG, 0x1fff, 0),
473 .line_flag_num[1] = VOP_REG(RK3588_VP3_LINE_FLAG, 0x1fff, 16),
474 .status = VOP_REG(RK3588_VP3_INT_STATUS, 0xffff, 0),
475 .enable = VOP_REG_MASK(RK3588_VP3_INT_EN, 0xffff, 0),
476 .clear = VOP_REG_MASK(RK3588_VP3_INT_CLR, 0xffff, 0),
477 };
478
479 static const struct vop2_dsc_regs rk3588_vop_dsc_8k_regs = {
480 /* DSC SYS CTRL */
481 .dsc_port_sel = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 0),
482 .dsc_man_mode = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 2),
483 .dsc_interface_mode = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 4),
484 .dsc_pixel_num = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 6),
485 .dsc_pxl_clk_div = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 8),
486 .dsc_cds_clk_div = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 12),
487 .dsc_txp_clk_div = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 14),
488 .dsc_init_dly_mode = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 16),
489 .dsc_scan_en = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 17),
490 .dsc_halt_en = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 18),
491 .rst_deassert = VOP_REG(RK3588_DSC_8K_RST, 0x1, 0),
492 .dsc_flush = VOP_REG(RK3588_DSC_8K_RST, 0x1, 16),
493 .dsc_cfg_done = VOP_REG(RK3588_DSC_8K_CFG_DONE, 0x1, 0),
494 .dsc_init_dly_num = VOP_REG(RK3588_DSC_8K_INIT_DLY, 0xffff, 0),
495 .scan_timing_para_imd_en = VOP_REG(RK3588_DSC_8K_INIT_DLY, 0x1, 16),
496 .dsc_htotal_pw = VOP_REG(RK3588_DSC_8K_HTOTAL_HS_END, 0xffffffff, 0),
497 .dsc_hact_st_end = VOP_REG(RK3588_DSC_8K_HACT_ST_END, 0xffffffff, 0),
498 .dsc_vtotal_pw = VOP_REG(RK3588_DSC_8K_VTOTAL_VS_END, 0xffffffff, 0),
499 .dsc_vact_st_end = VOP_REG(RK3588_DSC_8K_VACT_ST_END, 0xffffffff, 0),
500 .dsc_error_status = VOP_REG(RK3588_DSC_8K_STATUS, 0x1, 0),
501
502 /* DSC encoder */
503 .dsc_pps0_3 = VOP_REG(RK3588_DSC_8K_PPS0_3, 0xffffffff, 0),
504 .dsc_en = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 0),
505 .dsc_rbit = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 2),
506 .dsc_rbyt = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 3),
507 .dsc_flal = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 4),
508 .dsc_mer = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 5),
509 .dsc_epb = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 6),
510 .dsc_epl = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 7),
511 .dsc_nslc = VOP_REG(RK3588_DSC_8K_CTRL0, 0x7, 16),
512 .dsc_sbo = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 28),
513 .dsc_ifep = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 29),
514 .dsc_pps_upd = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 31),
515 .dsc_status = VOP_REG(RK3588_DSC_8K_STS0, 0xffffffff, 0),
516 .dsc_ecw = VOP_REG(RK3588_DSC_8K_ERS, 0xffffffff, 0),
517 };
518
519 static const struct vop2_dsc_regs rk3588_vop_dsc_4k_regs = {
520 /* DSC SYS CTRL */
521 .dsc_port_sel = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 0),
522 .dsc_man_mode = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 2),
523 .dsc_interface_mode = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 4),
524 .dsc_pixel_num = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 6),
525 .dsc_pxl_clk_div = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 8),
526 .dsc_cds_clk_div = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 12),
527 .dsc_txp_clk_div = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 14),
528 .dsc_init_dly_mode = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 16),
529 .dsc_scan_en = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 17),
530 .dsc_halt_en = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 18),
531 .rst_deassert = VOP_REG(RK3588_DSC_4K_RST, 0x1, 0),
532 .dsc_flush = VOP_REG(RK3588_DSC_4K_RST, 0x1, 16),
533 .dsc_cfg_done = VOP_REG(RK3588_DSC_4K_CFG_DONE, 0x1, 0),
534 .dsc_init_dly_num = VOP_REG(RK3588_DSC_4K_INIT_DLY, 0xffff, 0),
535 .scan_timing_para_imd_en = VOP_REG(RK3588_DSC_4K_INIT_DLY, 0x1, 16),
536 .dsc_htotal_pw = VOP_REG(RK3588_DSC_4K_HTOTAL_HS_END, 0xffffffff, 0),
537 .dsc_hact_st_end = VOP_REG(RK3588_DSC_4K_HACT_ST_END, 0xffffffff, 0),
538 .dsc_vtotal_pw = VOP_REG(RK3588_DSC_4K_VTOTAL_VS_END, 0xffffffff, 0),
539 .dsc_vact_st_end = VOP_REG(RK3588_DSC_4K_VACT_ST_END, 0xffffffff, 0),
540 .dsc_error_status = VOP_REG(RK3588_DSC_4K_STATUS, 0x1, 0),
541
542 /* DSC encoder */
543 .dsc_pps0_3 = VOP_REG(RK3588_DSC_4K_PPS0_3, 0xffffffff, 0),
544 .dsc_en = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 0),
545 .dsc_rbit = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 2),
546 .dsc_rbyt = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 3),
547 .dsc_flal = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 4),
548 .dsc_mer = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 5),
549 .dsc_epb = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 6),
550 .dsc_epl = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 7),
551 .dsc_nslc = VOP_REG(RK3588_DSC_4K_CTRL0, 0x7, 16),
552 .dsc_sbo = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 28),
553 .dsc_ifep = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 29),
554 .dsc_pps_upd = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 31),
555 .dsc_status = VOP_REG(RK3588_DSC_4K_STS0, 0xffffffff, 0),
556 .dsc_ecw = VOP_REG(RK3588_DSC_4K_ERS, 0xffffffff, 0),
557 };
558
559 static const struct dsc_error_info dsc_ecw[] = {
560 {0x00000000, "no error detected by DSC encoder"},
561 {0x0030ffff, "bits per component error"},
562 {0x0040ffff, "multiple mode error"},
563 {0x0050ffff, "line buffer depth error"},
564 {0x0060ffff, "minor version error"},
565 {0x0070ffff, "picture height error"},
566 {0x0080ffff, "picture width error"},
567 {0x0090ffff, "number of slices error"},
568 {0x00c0ffff, "slice height Error "},
569 {0x00d0ffff, "slice width error"},
570 {0x00e0ffff, "second line BPG offset error"},
571 {0x00f0ffff, "non second line BPG offset error"},
572 {0x0100ffff, "PPS ID error"},
573 {0x0110ffff, "bits per pixel (BPP) Error"},
574 {0x0120ffff, "buffer flow error"}, /* dsc_buffer_flow */
575
576 {0x01510001, "slice 0 RC buffer model overflow error"},
577 {0x01510002, "slice 1 RC buffer model overflow error"},
578 {0x01510004, "slice 2 RC buffer model overflow error"},
579 {0x01510008, "slice 3 RC buffer model overflow error"},
580 {0x01510010, "slice 4 RC buffer model overflow error"},
581 {0x01510020, "slice 5 RC buffer model overflow error"},
582 {0x01510040, "slice 6 RC buffer model overflow error"},
583 {0x01510080, "slice 7 RC buffer model overflow error"},
584
585 {0x01610001, "slice 0 RC buffer model underflow error"},
586 {0x01610002, "slice 1 RC buffer model underflow error"},
587 {0x01610004, "slice 2 RC buffer model underflow error"},
588 {0x01610008, "slice 3 RC buffer model underflow error"},
589 {0x01610010, "slice 4 RC buffer model underflow error"},
590 {0x01610020, "slice 5 RC buffer model underflow error"},
591 {0x01610040, "slice 6 RC buffer model underflow error"},
592 {0x01610080, "slice 7 RC buffer model underflow error"},
593
594 {0xffffffff, "unsuccessful RESET cycle status"},
595 {0x00a0ffff, "ICH full error precision settings error"},
596 {0x0020ffff, "native mode"},
597 };
598
599 static const struct dsc_error_info dsc_buffer_flow[] = {
600 {0x00000000, "rate buffer status"},
601 {0x00000001, "line buffer status"},
602 {0x00000002, "decoder model status"},
603 {0x00000003, "pixel buffer status"},
604 {0x00000004, "balance fifo buffer status"},
605 {0x00000005, "syntax element fifo status"},
606 };
607
608 static const struct vop2_dsc_data rk3588_vop_dsc_data[] = {
609 {
610 .id = 0,
611 .pd_id = VOP2_PD_DSC_8K,
612 .max_slice_num = 8,
613 .max_linebuf_depth = 11,
614 .min_bits_per_pixel = 9,
615 .dsc_txp_clk_src_name = "dsc_8k_txp_clk_src",
616 .dsc_txp_clk_name = "dsc_8k_txp_clk",
617 .dsc_pxl_clk_name = "dsc_8k_pxl_clk",
618 .dsc_cds_clk_name = "dsc_8k_cds_clk",
619 .regs = &rk3588_vop_dsc_8k_regs,
620 },
621
622 {
623 .id = 1,
624 .pd_id = VOP2_PD_DSC_4K,
625 .max_slice_num = 2,
626 .max_linebuf_depth = 11,
627 .min_bits_per_pixel = 9,
628 .dsc_txp_clk_src_name = "dsc_4k_txp_clk_src",
629 .dsc_txp_clk_name = "dsc_4k_txp_clk",
630 .dsc_pxl_clk_name = "dsc_4k_pxl_clk",
631 .dsc_cds_clk_name = "dsc_4k_cds_clk",
632 .regs = &rk3588_vop_dsc_4k_regs,
633 },
634 };
635
636 static const struct vop2_wb_regs rk3568_vop_wb_regs = {
637 .enable = VOP_REG(RK3568_WB_CTRL, 0x1, 0),
638 .format = VOP_REG(RK3568_WB_CTRL, 0x7, 1),
639 .dither_en = VOP_REG(RK3568_WB_CTRL, 0x1, 4),
640 .r2y_en = VOP_REG(RK3568_WB_CTRL, 0x1, 5),
641 .scale_x_en = VOP_REG(RK3568_WB_CTRL, 0x1, 7),
642 .scale_y_en = VOP_REG(RK3568_WB_CTRL, 0x1, 8),
643 .axi_yrgb_id = VOP_REG(RK3568_WB_CTRL, 0xff, 19),
644 .axi_uv_id = VOP_REG(RK3568_WB_CTRL, 0x1f, 27),
645 .scale_x_factor = VOP_REG(RK3568_WB_XSCAL_FACTOR, 0x3fff, 16),
646 .yrgb_mst = VOP_REG(RK3568_WB_YRGB_MST, 0xffffffff, 0),
647 .uv_mst = VOP_REG(RK3568_WB_CBR_MST, 0xffffffff, 0),
648 .vp_id = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 8),
649 .fifo_throd = VOP_REG(RK3568_WB_XSCAL_FACTOR, 0x3ff, 0),
650 };
651
652 static const struct vop2_wb_data rk3568_vop_wb_data = {
653 .formats = formats_wb,
654 .nformats = ARRAY_SIZE(formats_wb),
655 .max_output = { 1920, 1080 },
656 .fifo_depth = 1920 * 4 / 16,
657 .regs = &rk3568_vop_wb_regs,
658 };
659
660 static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
661 .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
662 .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
663 .dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0x3fffffff, 0),
664 .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0),
665 .out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
666 .standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
667 .core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
668 .dclk_div2 = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 4),
669 .dclk_div2_phase_lock = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 5),
670 .p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
671 .dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
672 .dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
673 .dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
674 .post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
675 .pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
676 .bg_dly = VOP_REG(RK3568_VP0_BG_MIX_CTRL, 0xff, 24),
677 .hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
678 .vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
679 .htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
680 .post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
681 .post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
682 .hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0x1fff1fff, 0),
683 .vtotal_pw = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
684 .vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
685 .vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
686 .vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
687 .vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
688 .pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
689 .dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
690 .dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
691 .dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
692 .dual_channel_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 20),
693 .dual_channel_swap = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 21),
694 .dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
695 .hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4),
696 .hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
697 .hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
698 .hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
699 .sdr2hdr_eotf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 0),
700 .sdr2hdr_r2r_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 1),
701 .sdr2hdr_r2r_mode = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 2),
702 .sdr2hdr_oetf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 3),
703 .sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 8),
704 .sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 9),
705 .sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 5),
706 .hdr2sdr_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 0),
707 .hdr2sdr_bypass_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 8),
708 .hdr2sdr_auto_gating_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 9),
709 .hdr2sdr_src_min = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 0),
710 .hdr2sdr_src_max = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 16),
711 .hdr2sdr_normfaceetf = VOP_REG(RK3568_HDR2SDR_NORMFACEETF, 0x7ff, 0),
712 .hdr2sdr_dst_min = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 0),
713 .hdr2sdr_dst_max = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 16),
714 .hdr2sdr_normfacgamma = VOP_REG(RK3568_HDR2SDR_NORMFACCGAMMA, 0xffff, 0),
715 .hdr2sdr_eetf_oetf_y0_offset = RK3568_HDR_EETF_OETF_Y0,
716 .hdr2sdr_sat_y0_offset = RK3568_HDR_SAT_Y0,
717 .sdr2hdr_eotf_oetf_y0_offset = RK3568_HDR_EOTF_OETF_Y0,
718 .sdr2hdr_oetf_dx_pow1_offset = RK3568_HDR_OETF_DX_POW1,
719 .sdr2hdr_oetf_xn1_offset = RK3568_HDR_OETF_XN1,
720 .hdr_src_color_ctrl = VOP_REG(RK3568_HDR0_SRC_COLOR_CTRL, 0xffffffff, 0),
721 .hdr_dst_color_ctrl = VOP_REG(RK3568_HDR0_DST_COLOR_CTRL, 0xffffffff, 0),
722 .hdr_src_alpha_ctrl = VOP_REG(RK3568_HDR0_SRC_ALPHA_CTRL, 0xffffffff, 0),
723 .hdr_dst_alpha_ctrl = VOP_REG(RK3568_HDR0_DST_ALPHA_CTRL, 0xffffffff, 0),
724
725 .bcsh_brightness = VOP_REG(RK3568_VP0_BCSH_BCS, 0xff, 0),
726 .bcsh_contrast = VOP_REG(RK3568_VP0_BCSH_BCS, 0x1ff, 8),
727 .bcsh_sat_con = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3ff, 20),
728 .bcsh_out_mode = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3, 30),
729 .bcsh_sin_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 0),
730 .bcsh_cos_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 16),
731 .bcsh_r2y_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 6),
732 .bcsh_r2y_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 4),
733 .bcsh_y2r_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 2),
734 .bcsh_y2r_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 0),
735 .bcsh_en = VOP_REG(RK3568_VP0_BCSH_COLOR_BAR, 0x1, 31),
736
737 .cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0),
738 .cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2),
739 .cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0),
740 };
741
742 static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
743 .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
744 .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1),
745 .dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0x3fffffff, 0),
746 .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4),
747 .out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
748 .standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
749 .core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
750 .dclk_div2 = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 4),
751 .dclk_div2_phase_lock = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 5),
752 .p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
753 .dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
754 .dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
755 .dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
756 .post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
757 .pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
758 .bg_dly = VOP_REG(RK3568_VP1_BG_MIX_CTRL, 0xff, 24),
759 .hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
760 .vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
761 .htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
762 .post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
763 .post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
764 .hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0x1fff1fff, 0),
765 .vtotal_pw = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
766 .vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
767 .vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
768 .vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
769 .vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
770 .pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
771 .dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
772 .dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
773 .dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
774 .dual_channel_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 20),
775 .dual_channel_swap = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 21),
776
777 .bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0),
778 .bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8),
779 .bcsh_sat_con = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3ff, 20),
780 .bcsh_out_mode = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3, 30),
781 .bcsh_sin_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 0),
782 .bcsh_cos_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 16),
783 .bcsh_r2y_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 6),
784 .bcsh_r2y_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 4),
785 .bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2),
786 .bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
787 .bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
788 .dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
789 };
790
791 static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
792 .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
793 .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2),
794 .dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0x3fffffff, 0),
795 .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8),
796 .out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
797 .standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
798 .core_dclk_div = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 4),
799 .dclk_div2 = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 4),
800 .dclk_div2_phase_lock = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 5),
801 .p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5),
802 .dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6),
803 .dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),
804 .dsp_data_swap = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1f, 8),
805 .post_dsp_out_r2y = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 15),
806 .pre_scan_htiming = VOP_REG(RK3568_VP2_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
807 .bg_dly = VOP_REG(RK3568_VP2_BG_MIX_CTRL, 0xff, 24),
808 .hpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
809 .vpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
810 .post_scl_factor = VOP_REG(RK3568_VP2_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
811 .post_scl_ctrl = VOP_REG(RK3568_VP2_POST_SCL_CTRL, 0x3, 0),
812 .htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
813 .hact_st_end = VOP_REG(RK3568_VP2_DSP_HACT_ST_END, 0x1fff1fff, 0),
814 .vtotal_pw = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
815 .vact_st_end = VOP_REG(RK3568_VP2_DSP_VACT_ST_END, 0x1fff1fff, 0),
816 .vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
817 .vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
818 .vpost_st_end_f1 = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
819 .pre_dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 16),
820 .dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 17),
821 .dither_down_sel = VOP_REG(RK3568_VP2_DSP_CTRL, 0x3, 18),
822 .dither_down_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 20),
823 .dual_channel_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 20),
824 .dual_channel_swap = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 21),
825
826 .bcsh_brightness = VOP_REG(RK3568_VP2_BCSH_BCS, 0xff, 0),
827 .bcsh_contrast = VOP_REG(RK3568_VP2_BCSH_BCS, 0x1ff, 8),
828 .bcsh_sat_con = VOP_REG(RK3568_VP2_BCSH_BCS, 0x3ff, 20),
829 .bcsh_out_mode = VOP_REG(RK3568_VP2_BCSH_BCS, 0x3, 30),
830 .bcsh_sin_hue = VOP_REG(RK3568_VP2_BCSH_H, 0x1ff, 0),
831 .bcsh_cos_hue = VOP_REG(RK3568_VP2_BCSH_H, 0x1ff, 16),
832 .bcsh_r2y_csc_mode = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x3, 6),
833 .bcsh_r2y_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 4),
834 .bcsh_y2r_csc_mode = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x3, 2),
835 .bcsh_y2r_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 0),
836 .bcsh_en = VOP_REG(RK3568_VP2_BCSH_COLOR_BAR, 0x1, 31),
837 .dsp_lut_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 28),
838 };
839
840 static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
841 {
842 .id = 0,
843 .soc_id = { 0x3568, 0x3566 },
844 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE |
845 VOP_FEATURE_HDR10 | VOP_FEATURE_OVERSCAN,
846 .gamma_lut_len = 1024,
847 .cubic_lut_len = 729, /* 9x9x9 */
848 .max_output = { 4096, 2304 },
849 .pre_scan_max_dly = { 69, 53, 53, 42 },
850 .intr = &rk3568_vp0_intr,
851 .hdr_table = &rk3568_vop_hdr_table,
852 .regs = &rk3568_vop_vp0_regs,
853 },
854 {
855 .id = 1,
856 .soc_id = { 0x3568, 0x3566 },
857 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
858 .gamma_lut_len = 1024,
859 .max_output = { 2048, 1536 },
860 .pre_scan_max_dly = { 40, 40, 40, 40 },
861 .intr = &rk3568_vp1_intr,
862 .regs = &rk3568_vop_vp1_regs,
863 },
864 {
865 .id = 2,
866 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
867 .soc_id = { 0x3568, 0x3566 },
868 .gamma_lut_len = 1024,
869 .max_output = { 1920, 1080 },
870 .pre_scan_max_dly = { 40, 40, 40, 40 },
871 .intr = &rk3568_vp2_intr,
872 .regs = &rk3568_vop_vp2_regs,
873 },
874 };
875
876 static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
877 .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
878 .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
879 .dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
880 .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0),
881 .out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
882 .p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
883 .dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
884 .dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
885 .dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
886 .post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
887 .pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
888 .dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
889 .dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
890 .dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
891 .gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
892 .dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
893 .standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
894 .dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
895 .splice_en = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 16),
896 .dclk_core_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 0),
897 .dclk_out_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 2),
898 .pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
899 .bg_dly = VOP_REG(RK3568_VP0_BG_MIX_CTRL, 0xff, 24),
900 .hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
901 .vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
902 .post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
903 .post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
904 .htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
905 .hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
906 .vtotal_pw = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
907 .vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
908 .vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
909 .vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
910 .vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
911 .dual_channel_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 20),
912 .dual_channel_swap = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 21),
913 .hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4),
914 .hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
915 .hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
916 .hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
917 .sdr2hdr_eotf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 0),
918 .sdr2hdr_r2r_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 1),
919 .sdr2hdr_r2r_mode = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 2),
920 .sdr2hdr_oetf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 3),
921 .sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 8),
922 .sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 9),
923 .sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 5),
924 .hdr2sdr_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 0),
925 .hdr2sdr_bypass_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 8),
926 .hdr2sdr_auto_gating_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 9),
927 .hdr2sdr_src_min = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 0),
928 .hdr2sdr_src_max = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 16),
929 .hdr2sdr_normfaceetf = VOP_REG(RK3568_HDR2SDR_NORMFACEETF, 0x7ff, 0),
930 .hdr2sdr_dst_min = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 0),
931 .hdr2sdr_dst_max = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 16),
932 .hdr2sdr_normfacgamma = VOP_REG(RK3568_HDR2SDR_NORMFACCGAMMA, 0xffff, 0),
933 .hdr2sdr_eetf_oetf_y0_offset = RK3568_HDR_EETF_OETF_Y0,
934 .hdr2sdr_sat_y0_offset = RK3568_HDR_SAT_Y0,
935 .sdr2hdr_eotf_oetf_y0_offset = RK3568_HDR_EOTF_OETF_Y0,
936 .sdr2hdr_oetf_dx_pow1_offset = RK3568_HDR_OETF_DX_POW1,
937 .sdr2hdr_oetf_xn1_offset = RK3568_HDR_OETF_XN1,
938 .hdr_src_color_ctrl = VOP_REG(RK3568_HDR0_SRC_COLOR_CTRL, 0xffffffff, 0),
939 .hdr_dst_color_ctrl = VOP_REG(RK3568_HDR0_DST_COLOR_CTRL, 0xffffffff, 0),
940 .hdr_src_alpha_ctrl = VOP_REG(RK3568_HDR0_SRC_ALPHA_CTRL, 0xffffffff, 0),
941 .hdr_dst_alpha_ctrl = VOP_REG(RK3568_HDR0_DST_ALPHA_CTRL, 0xffffffff, 0),
942
943 .bcsh_brightness = VOP_REG(RK3568_VP0_BCSH_BCS, 0xff, 0),
944 .bcsh_contrast = VOP_REG(RK3568_VP0_BCSH_BCS, 0x1ff, 8),
945 .bcsh_sat_con = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3ff, 20),
946 .bcsh_out_mode = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3, 30),
947 .bcsh_sin_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 0),
948 .bcsh_cos_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 16),
949 .bcsh_r2y_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 6),
950 .bcsh_r2y_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 4),
951 .bcsh_y2r_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 2),
952 .bcsh_y2r_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 0),
953 .bcsh_en = VOP_REG(RK3568_VP0_BCSH_COLOR_BAR, 0x1, 31),
954 .edpi_te_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 28),
955 .edpi_wms_hold_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 30),
956 .edpi_wms_fs = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 31),
957
958 .lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
959 .cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0),
960 .cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2),
961 .cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0),
962 };
963
964 /*
965 * VP1 can splice with VP0 to output hdisplay > 4096,
966 * VP1 has a another HDR10 controller, but share the
967 * same eotf curve with VP1.
968 */
969 static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
970 .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
971 .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1),
972 .dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0),
973 .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4),
974 .out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
975 .p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
976 .dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
977 .dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
978 .dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
979 .post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
980 .pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
981 .dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
982 .dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
983 .dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
984 .gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22),
985 .dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
986 .standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
987 .dclk_core_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 0),
988 .dclk_out_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 2),
989 .pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
990 .bg_dly = VOP_REG(RK3568_VP1_BG_MIX_CTRL, 0xff, 24),
991 .hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
992 .vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
993 .post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
994 .post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
995 .htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
996 .hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0x1fff1fff, 0),
997 .vtotal_pw = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
998 .vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
999 .vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1000 .vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1001 .vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1002 .dual_channel_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 20),
1003 .dual_channel_swap = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 21),
1004 .hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 24),
1005 .hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
1006 .hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
1007 .hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
1008 .sdr2hdr_eotf_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 0),
1009 .sdr2hdr_r2r_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 1),
1010 .sdr2hdr_r2r_mode = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 2),
1011 .sdr2hdr_oetf_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 3),
1012 .sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 8),
1013 .sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 9),
1014 .sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 25),
1015 .hdr2sdr_en = VOP_REG(RK3568_HDR2SDR_CTRL1, 0x1, 0),
1016 .hdr2sdr_bypass_en = VOP_REG(RK3568_HDR2SDR_CTRL1, 0x1, 8),
1017 .hdr2sdr_auto_gating_en = VOP_REG(RK3568_HDR2SDR_CTRL1, 0x1, 9),
1018 .hdr2sdr_src_min = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 0),
1019 .hdr2sdr_src_max = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 16),
1020 .hdr2sdr_normfaceetf = VOP_REG(RK3568_HDR2SDR_NORMFACEETF, 0x7ff, 0),
1021 .hdr2sdr_dst_min = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 0),
1022 .hdr2sdr_dst_max = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 16),
1023 .hdr2sdr_normfacgamma = VOP_REG(RK3568_HDR2SDR_NORMFACCGAMMA, 0xffff, 0),
1024 .hdr2sdr_eetf_oetf_y0_offset = RK3568_HDR_EETF_OETF_Y0,
1025 .hdr2sdr_sat_y0_offset = RK3568_HDR_SAT_Y0,
1026 .sdr2hdr_eotf_oetf_y0_offset = RK3568_HDR_EOTF_OETF_Y0,
1027 .sdr2hdr_oetf_dx_pow1_offset = RK3568_HDR_OETF_DX_POW1,
1028 .sdr2hdr_oetf_xn1_offset = RK3568_HDR_OETF_XN1,
1029 .hdr_src_color_ctrl = VOP_REG(RK3568_HDR1_SRC_COLOR_CTRL, 0xffffffff, 0),
1030 .hdr_dst_color_ctrl = VOP_REG(RK3568_HDR1_DST_COLOR_CTRL, 0xffffffff, 0),
1031 .hdr_src_alpha_ctrl = VOP_REG(RK3568_HDR1_SRC_ALPHA_CTRL, 0xffffffff, 0),
1032 .hdr_dst_alpha_ctrl = VOP_REG(RK3568_HDR1_DST_ALPHA_CTRL, 0xffffffff, 0),
1033
1034 .bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0),
1035 .bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8),
1036 .bcsh_sat_con = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3ff, 20),
1037 .bcsh_out_mode = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3, 30),
1038 .bcsh_sin_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 0),
1039 .bcsh_cos_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 16),
1040 .bcsh_r2y_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 6),
1041 .bcsh_r2y_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 4),
1042 .bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2),
1043 .bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
1044 .bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
1045 .edpi_te_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 28),
1046 .edpi_wms_hold_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 30),
1047 .edpi_wms_fs = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 31),
1048
1049 .lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1050 .cubic_lut_en = VOP_REG(RK3588_VP1_3D_LUT_CTRL, 0x1, 0),
1051 .cubic_lut_update_en = VOP_REG(RK3588_VP1_3D_LUT_CTRL, 0x1, 2),
1052 .cubic_lut_mst = VOP_REG(RK3588_VP1_3D_LUT_MST, 0xffffffff, 0),
1053 };
1054
1055 static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
1056 .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
1057 .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2),
1058 .dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0xffffffff, 0),
1059 .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8),
1060 .out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
1061 .p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5),
1062 .dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6),
1063 .dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),
1064 .dsp_data_swap = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1f, 8),
1065 .post_dsp_out_r2y = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 15),
1066 .pre_dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 16),
1067 .dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 17),
1068 .dither_down_sel = VOP_REG(RK3568_VP2_DSP_CTRL, 0x3, 18),
1069 .dither_down_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 20),
1070 .gamma_update_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 22),
1071 .dsp_lut_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 28),
1072 .standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
1073 .dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 31),
1074 .dclk_core_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 0),
1075 .dclk_out_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 2),
1076 .pre_scan_htiming = VOP_REG(RK3568_VP2_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1077 .bg_dly = VOP_REG(RK3568_VP2_BG_MIX_CTRL, 0xff, 24),
1078 .hpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1079 .vpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1080 .post_scl_factor = VOP_REG(RK3568_VP2_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1081 .post_scl_ctrl = VOP_REG(RK3568_VP2_POST_SCL_CTRL, 0x3, 0),
1082 .htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1083 .hact_st_end = VOP_REG(RK3568_VP2_DSP_HACT_ST_END, 0x1fff1fff, 0),
1084 .vtotal_pw = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1085 .vact_st_end = VOP_REG(RK3568_VP2_DSP_VACT_ST_END, 0x1fff1fff, 0),
1086 .vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1087 .vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1088 .vpost_st_end_f1 = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1089 .dual_channel_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 20),
1090 .dual_channel_swap = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 21),
1091 .bcsh_brightness = VOP_REG(RK3568_VP2_BCSH_BCS, 0xff, 0),
1092 .bcsh_contrast = VOP_REG(RK3568_VP2_BCSH_BCS, 0x1ff, 8),
1093 .bcsh_sat_con = VOP_REG(RK3568_VP2_BCSH_BCS, 0x3ff, 20),
1094 .bcsh_out_mode = VOP_REG(RK3568_VP2_BCSH_BCS, 0x3, 30),
1095 .bcsh_sin_hue = VOP_REG(RK3568_VP2_BCSH_H, 0x1ff, 0),
1096 .bcsh_cos_hue = VOP_REG(RK3568_VP2_BCSH_H, 0x1ff, 16),
1097 .bcsh_r2y_csc_mode = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x3, 6),
1098 .bcsh_r2y_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 4),
1099 .bcsh_y2r_csc_mode = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x3, 2),
1100 .bcsh_y2r_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 0),
1101 .bcsh_en = VOP_REG(RK3568_VP2_BCSH_COLOR_BAR, 0x1, 31),
1102 .edpi_te_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 28),
1103 .edpi_wms_hold_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 30),
1104 .edpi_wms_fs = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 31),
1105
1106 .lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1107 .cubic_lut_en = VOP_REG(RK3588_VP2_3D_LUT_CTRL, 0x1, 0),
1108 .cubic_lut_update_en = VOP_REG(RK3588_VP2_3D_LUT_CTRL, 0x1, 2),
1109 .cubic_lut_mst = VOP_REG(RK3588_VP2_3D_LUT_MST, 0xffffffff, 0),
1110 };
1111
1112 static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
1113 .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 3),
1114 .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 3),
1115 .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 12),
1116 .dsp_background = VOP_REG(RK3588_VP3_DSP_BG, 0xffffffff, 0),
1117 .out_mode = VOP_REG(RK3588_VP3_DSP_CTRL, 0xf, 0),
1118 .p2i_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 5),
1119 .dsp_filed_pol = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 6),
1120 .dsp_interlace = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 7),
1121 .dsp_data_swap = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1f, 8),
1122 .post_dsp_out_r2y = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 15),
1123 .pre_dither_down_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 16),
1124 .dither_down_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 17),
1125 .dither_down_sel = VOP_REG(RK3588_VP3_DSP_CTRL, 0x3, 18),
1126 .dither_down_mode = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 20),
1127 .gamma_update_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 22),
1128 .dsp_lut_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 28),
1129 .standby = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 31),
1130 .dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
1131 .dclk_core_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 0),
1132 .dclk_out_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 2),
1133 .pre_scan_htiming = VOP_REG(RK3588_VP3_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1134 .bg_dly = VOP_REG(RK3588_VP3_BG_MIX_CTRL, 0xff, 24),
1135 .hpost_st_end = VOP_REG(RK3588_VP3_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1136 .vpost_st_end = VOP_REG(RK3588_VP3_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1137 .post_scl_factor = VOP_REG(RK3588_VP3_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1138 .post_scl_ctrl = VOP_REG(RK3588_VP3_POST_SCL_CTRL, 0x3, 0),
1139 .htotal_pw = VOP_REG(RK3588_VP3_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1140 .hact_st_end = VOP_REG(RK3588_VP3_DSP_HACT_ST_END, 0x1fff1fff, 0),
1141 .vtotal_pw = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1142 .vact_st_end = VOP_REG(RK3588_VP3_DSP_VACT_ST_END, 0x1fff1fff, 0),
1143 .vact_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1144 .vs_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1145 .vpost_st_end_f1 = VOP_REG(RK3588_VP3_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1146 .dual_channel_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 20),
1147 .dual_channel_swap = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 21),
1148 .bcsh_brightness = VOP_REG(RK3588_VP3_BCSH_BCS, 0xff, 0),
1149 .bcsh_contrast = VOP_REG(RK3588_VP3_BCSH_BCS, 0x1ff, 8),
1150 .bcsh_sat_con = VOP_REG(RK3588_VP3_BCSH_BCS, 0x3ff, 20),
1151 .bcsh_out_mode = VOP_REG(RK3588_VP3_BCSH_BCS, 0x3, 30),
1152 .bcsh_sin_hue = VOP_REG(RK3588_VP3_BCSH_H, 0x1ff, 0),
1153 .bcsh_cos_hue = VOP_REG(RK3588_VP3_BCSH_H, 0x1ff, 16),
1154 .bcsh_r2y_csc_mode = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x3, 6),
1155 .bcsh_r2y_en = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x1, 4),
1156 .bcsh_y2r_csc_mode = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x3, 2),
1157 .bcsh_y2r_en = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x1, 0),
1158 .bcsh_en = VOP_REG(RK3588_VP3_BCSH_COLOR_BAR, 0x1, 31),
1159 .edpi_te_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 28),
1160 .edpi_wms_hold_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 30),
1161 .edpi_wms_fs = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 31),
1162 };
1163
1164 static const struct vop2_video_port_data rk3588_vop_video_ports[] = {
1165 {
1166 .id = 0,
1167 .splice_vp_id = 1,
1168 .lut_dma_rid = 1,
1169 .soc_id = { 0x3588, 0x3588 },
1170 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE |
1171 VOP_FEATURE_HDR10 | VOP_FEATURE_NEXT_HDR,
1172 .gamma_lut_len = 1024,
1173 .cubic_lut_len = 729, /* 9x9x9 */
1174 .dclk_max = 600000000,
1175 .max_output = { 7680, 4320 },
1176 /* hdr2sdr sdr2hdr hdr2hdr sdr2sdr */
1177 .pre_scan_max_dly = { 76, 65, 65, 54 },
1178 .intr = &rk3568_vp0_intr,
1179 .hdr_table = &rk3568_vop_hdr_table,
1180 .regs = &rk3588_vop_vp0_regs,
1181 },
1182 {
1183 .id = 1,
1184 .lut_dma_rid = 14,
1185 .soc_id = { 0x3588, 0x3588 },
1186 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE,
1187 .gamma_lut_len = 1024,
1188 .cubic_lut_len = 729, /* 9x9x9 */
1189 .dclk_max = 600000000,
1190 .max_output = { 4096, 2304 },
1191 .pre_scan_max_dly = { 76, 65, 65, 54 },
1192 .intr = &rk3568_vp1_intr,
1193 /* vp1 share the same hdr curve with vp0 */
1194 .hdr_table = &rk3568_vop_hdr_table,
1195 .regs = &rk3588_vop_vp1_regs,
1196 },
1197 {
1198 .id = 2,
1199 .lut_dma_rid = 14,
1200 .soc_id = { 0x3588, 0x3588 },
1201 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE,
1202 .gamma_lut_len = 1024,
1203 .cubic_lut_len = 4913, /* 17x17x17 */
1204 .dclk_max = 600000000,
1205 .max_output = { 4096, 2304 },
1206 .pre_scan_max_dly = { 52, 52, 52, 52 },
1207 .intr = &rk3568_vp2_intr,
1208 .regs = &rk3588_vop_vp2_regs,
1209 },
1210 {
1211 .id = 3,
1212 .soc_id = { 0x3588, 0x3588 },
1213 .feature = VOP_FEATURE_ALPHA_SCALE,
1214 .gamma_lut_len = 1024,
1215 .dclk_max = 200000000,
1216 .max_output = { 2048, 1536 },
1217 .pre_scan_max_dly = { 52, 52, 52, 52 },
1218 .intr = &rk3588_vp3_intr,
1219 .regs = &rk3588_vop_vp3_regs,
1220 },
1221 };
1222
1223 /*
1224 * HDMI/eDP infterface pixclk and dclk are independent of each other.
1225 * MIPI and DP interface pixclk and dclk are the same in itself.
1226 */
1227 static const struct vop2_connector_if_data rk3588_conn_if_data[] = {
1228 {
1229 .id = VOP_OUTPUT_IF_HDMI0,
1230 .clk_src_name = "hdmi_edp0_clk_src",
1231 .clk_parent_name = "dclk",
1232 .pixclk_name = "hdmi_edp0_pixclk",
1233 .dclk_name = "hdmi_edp0_dclk",
1234 .post_proc_div_shift = 2,
1235 .if_div_shift = 4,
1236 .if_div_yuv420_shift = 1,
1237 .bus_div_shift = 2,
1238 .pixel_clk_div_shift = 2,
1239 },
1240
1241 {
1242 .id = VOP_OUTPUT_IF_HDMI1,
1243 .clk_src_name = "hdmi_edp1_clk_src",
1244 .clk_parent_name = "dclk",
1245 .pixclk_name = "hdmi_edp1_pixclk",
1246 .dclk_name = "hdmi_edp1_dclk",
1247 .post_proc_div_shift = 2,
1248 .if_div_shift = 4,
1249 .if_div_yuv420_shift = 1,
1250 .bus_div_shift = 2,
1251 .pixel_clk_div_shift = 2,
1252 },
1253
1254 {
1255 .id = VOP_OUTPUT_IF_eDP0,
1256 .clk_src_name = "hdmi_edp0_clk_src",
1257 .clk_parent_name = "dclk",
1258 .pixclk_name = "hdmi_edp0_pixclk",
1259 .dclk_name = "hdmi_edp0_dclk",
1260 .post_proc_div_shift = 2,
1261 .if_div_shift = 4,
1262 .if_div_yuv420_shift = 1,
1263 .bus_div_shift = 1,
1264 .pixel_clk_div_shift = 1,
1265 },
1266
1267 {
1268 .id = VOP_OUTPUT_IF_eDP1,
1269 .clk_src_name = "hdmi_edp1_clk_src",
1270 .clk_parent_name = "dclk",
1271 .pixclk_name = "hdmi_edp1_pixclk",
1272 .dclk_name = "hdmi_edp1_dclk",
1273 .post_proc_div_shift = 2,
1274 .if_div_shift = 4,
1275 .if_div_yuv420_shift = 1,
1276 .bus_div_shift = 1,
1277 .pixel_clk_div_shift = 1,
1278 },
1279
1280 {
1281 .id = VOP_OUTPUT_IF_DP0,
1282 .clk_src_name = "dp0_pixclk",
1283 .clk_parent_name = "dclk_out",
1284 .pixclk_name = "dp0_pixclk",
1285 .post_proc_div_shift = 2,
1286 .if_div_shift = 1,
1287 .if_div_yuv420_shift = 2,
1288 .bus_div_shift = 1,
1289 .pixel_clk_div_shift = 1,
1290
1291 },
1292
1293 {
1294 .id = VOP_OUTPUT_IF_DP1,
1295 .clk_src_name = "dp1_pixclk",
1296 .clk_parent_name = "dclk_out",
1297 .pixclk_name = "dp1_pixclk",
1298 .post_proc_div_shift = 2,
1299 .if_div_shift = 1,
1300 .if_div_yuv420_shift = 2,
1301 .bus_div_shift = 1,
1302 .pixel_clk_div_shift = 1,
1303
1304 },
1305
1306 {
1307 .id = VOP_OUTPUT_IF_MIPI0,
1308 .clk_src_name = "mipi0_clk_src",
1309 .clk_parent_name = "dclk_out",
1310 .pixclk_name = "mipi0_pixclk",
1311 .post_proc_div_shift = 2,
1312 .if_div_shift = 1,
1313 .if_div_yuv420_shift = 1,
1314 .bus_div_shift = 1,
1315 .pixel_clk_div_shift = 1,
1316 },
1317
1318 {
1319 .id = VOP_OUTPUT_IF_MIPI1,
1320 .clk_src_name = "mipi1_clk_src",
1321 .clk_parent_name = "dclk_out",
1322 .pixclk_name = "mipi1_pixclk",
1323 .post_proc_div_shift = 2,
1324 .if_div_shift = 1,
1325 .if_div_yuv420_shift = 1,
1326 .bus_div_shift = 1,
1327 .pixel_clk_div_shift = 1,
1328 },
1329
1330 {
1331 .id = VOP_OUTPUT_IF_RGB,
1332 .clk_src_name = "port3_dclk_src",
1333 .clk_parent_name = "dclk",
1334 .pixclk_name = "rgb_pixclk",
1335 .post_proc_div_shift = 2,
1336 .if_div_shift = 0,
1337 .if_div_yuv420_shift = 0,
1338 .bus_div_shift = 0,
1339 .pixel_clk_div_shift = 0,
1340 },
1341 };
1342
1343
1344 const struct vop2_layer_regs rk3568_vop_layer0_regs = {
1345 .layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 0)
1346 };
1347
1348 const struct vop2_layer_regs rk3568_vop_layer1_regs = {
1349 .layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 4)
1350 };
1351
1352 const struct vop2_layer_regs rk3568_vop_layer2_regs = {
1353 .layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 8)
1354 };
1355
1356 const struct vop2_layer_regs rk3568_vop_layer3_regs = {
1357 .layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 12)
1358 };
1359
1360 const struct vop2_layer_regs rk3568_vop_layer4_regs = {
1361 .layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 16)
1362 };
1363
1364 const struct vop2_layer_regs rk3568_vop_layer5_regs = {
1365 .layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 20)
1366 };
1367
1368 const struct vop2_layer_regs rk3568_vop_layer6_regs = {
1369 .layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 24)
1370 };
1371
1372 const struct vop2_layer_regs rk3568_vop_layer7_regs = {
1373 .layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 28)
1374 };
1375
1376 static const struct vop2_layer_data rk3568_vop_layers[] = {
1377 {
1378 .id = 0,
1379 .regs = &rk3568_vop_layer0_regs,
1380 },
1381
1382 {
1383 .id = 1,
1384 .regs = &rk3568_vop_layer1_regs,
1385 },
1386
1387 {
1388 .id = 2,
1389 .regs = &rk3568_vop_layer2_regs,
1390 },
1391
1392 {
1393 .id = 3,
1394 .regs = &rk3568_vop_layer3_regs,
1395 },
1396
1397 {
1398 .id = 4,
1399 .regs = &rk3568_vop_layer4_regs,
1400 },
1401
1402 {
1403 .id = 5,
1404 .regs = &rk3568_vop_layer5_regs,
1405 },
1406
1407 {
1408 .id = 6,
1409 .regs = &rk3568_vop_layer6_regs,
1410 },
1411
1412 {
1413 .id = 7,
1414 .regs = &rk3568_vop_layer7_regs,
1415 },
1416
1417 };
1418
1419 static const struct vop2_cluster_regs rk3568_vop_cluster0 = {
1420 .afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
1421 .enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
1422 .lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
1423 };
1424
1425 static const struct vop2_cluster_regs rk3568_vop_cluster1 = {
1426 .afbc_enable = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 1),
1427 .enable = VOP_REG(RK3568_CLUSTER1_CTRL, 1, 0),
1428 .lb_mode = VOP_REG(RK3568_CLUSTER1_CTRL, 0xf, 4),
1429 };
1430
1431 static const struct vop2_cluster_regs rk3588_vop_cluster2 = {
1432 .afbc_enable = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 1),
1433 .enable = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 0),
1434 .lb_mode = VOP_REG(RK3588_CLUSTER2_CTRL, 0xf, 4),
1435 };
1436
1437 static const struct vop2_cluster_regs rk3588_vop_cluster3 = {
1438 .afbc_enable = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 1),
1439 .enable = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 0),
1440 .lb_mode = VOP_REG(RK3588_CLUSTER3_CTRL, 0xf, 4),
1441 };
1442
1443 static const struct vop_afbc rk3568_cluster0_afbc = {
1444 .format = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1f, 2),
1445 .rb_swap = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1, 9),
1446 .uv_swap = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1, 10),
1447 .auto_gating_en = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_OUTPUT_CTRL, 0x1, 4),
1448 .half_block_en = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1, 7),
1449 .block_split_en = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1, 8),
1450 .hdr_ptr = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR, 0xffffffff, 0),
1451 .pic_size = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE, 0xffffffff, 0),
1452 .pic_vir_width = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH, 0xffff, 0),
1453 .tile_num = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH, 0xffff, 16),
1454 .pic_offset = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET, 0xffffffff, 0),
1455 .dsp_offset = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET, 0xffffffff, 0),
1456 .transform_offset = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_TRANSFORM_OFFSET, 0xffffffff, 0),
1457 .rotate_90 = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 0),
1458 .rotate_270 = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
1459 .xmirror = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
1460 .ymirror = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
1461 };
1462
1463 static const struct vop2_scl_regs rk3568_cluster0_win_scl = {
1464 .scale_yrgb_x = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1465 .scale_yrgb_y = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
1466 .yrgb_ver_scl_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 14),
1467 .yrgb_hor_scl_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 12),
1468 .bic_coe_sel = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 2),
1469 .vsd_yrgb_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 28),
1470 .vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 29),
1471 };
1472
1473 static const struct vop_afbc rk3568_cluster1_afbc = {
1474 .format = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_CTRL, 0x1f, 2),
1475 .rb_swap = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_CTRL, 0x1, 9),
1476 .uv_swap = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_CTRL, 0x1, 10),
1477 .auto_gating_en = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_OUTPUT_CTRL, 0x1, 4),
1478 .half_block_en = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_CTRL, 0x1, 7),
1479 .block_split_en = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_CTRL, 0x1, 8),
1480 .hdr_ptr = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR, 0xffffffff, 0),
1481 .pic_size = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE, 0xffffffff, 0),
1482 .pic_vir_width = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH, 0xffff, 0),
1483 .tile_num = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH, 0xffff, 16),
1484 .pic_offset = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET, 0xffffffff, 0),
1485 .dsp_offset = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET, 0xffffffff, 0),
1486 .transform_offset = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_TRANSFORM_OFFSET, 0xffffffff, 0),
1487 .rotate_90 = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE, 0x1, 0),
1488 .rotate_270 = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
1489 .xmirror = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
1490 .ymirror = VOP_REG(RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
1491 };
1492
1493 static const struct vop2_scl_regs rk3568_cluster1_win_scl = {
1494 .scale_yrgb_x = VOP_REG(RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1495 .scale_yrgb_y = VOP_REG(RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
1496 .yrgb_ver_scl_mode = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL1, 0x3, 14),
1497 .yrgb_hor_scl_mode = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL1, 0x3, 12),
1498 .bic_coe_sel = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL1, 0x3, 2),
1499 .vsd_yrgb_gt2 = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL1, 0x1, 28),
1500 .vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL1, 0x1, 29),
1501 };
1502
1503 static const struct vop_afbc rk3588_cluster2_afbc = {
1504 .format = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1f, 2),
1505 .rb_swap = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 9),
1506 .uv_swap = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 10),
1507 .auto_gating_en = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_OUTPUT_CTRL, 0x1, 4),
1508 .half_block_en = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 7),
1509 .block_split_en = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 8),
1510 .hdr_ptr = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_HDR_PTR, 0xffffffff, 0),
1511 .pic_size = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_PIC_SIZE, 0xffffffff, 0),
1512 .pic_vir_width = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH, 0xffff, 0),
1513 .tile_num = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH, 0xffff, 16),
1514 .pic_offset = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_PIC_OFFSET, 0xffffffff, 0),
1515 .dsp_offset = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_DSP_OFFSET, 0xffffffff, 0),
1516 .transform_offset = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_TRANSFORM_OFFSET, 0xffffffff, 0),
1517 .rotate_90 = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 0),
1518 .rotate_270 = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
1519 .xmirror = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
1520 .ymirror = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
1521 };
1522
1523 static const struct vop2_scl_regs rk3588_cluster2_win_scl = {
1524 .scale_yrgb_x = VOP_REG(RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1525 .scale_yrgb_y = VOP_REG(RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
1526 .yrgb_ver_scl_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x3, 14),
1527 .yrgb_hor_scl_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x3, 12),
1528 .bic_coe_sel = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x3, 2),
1529 .vsd_yrgb_gt2 = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x1, 28),
1530 .vsd_yrgb_gt4 = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x1, 29),
1531 };
1532
1533 static const struct vop_afbc rk3588_cluster3_afbc = {
1534 .format = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1f, 2),
1535 .rb_swap = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 9),
1536 .uv_swap = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 10),
1537 .auto_gating_en = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_OUTPUT_CTRL, 0x1, 4),
1538 .half_block_en = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 7),
1539 .block_split_en = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 8),
1540 .hdr_ptr = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_HDR_PTR, 0xffffffff, 0),
1541 .pic_size = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_PIC_SIZE, 0xffffffff, 0),
1542 .pic_vir_width = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH, 0xffff, 0),
1543 .tile_num = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH, 0xffff, 16),
1544 .pic_offset = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_PIC_OFFSET, 0xffffffff, 0),
1545 .dsp_offset = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_DSP_OFFSET, 0xffffffff, 0),
1546 .transform_offset = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_TRANSFORM_OFFSET, 0xffffffff, 0),
1547 .rotate_90 = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 0),
1548 .rotate_270 = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
1549 .xmirror = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
1550 .ymirror = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
1551 };
1552
1553 static const struct vop2_scl_regs rk3588_cluster3_win_scl = {
1554 .scale_yrgb_x = VOP_REG(RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1555 .scale_yrgb_y = VOP_REG(RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
1556 .yrgb_ver_scl_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x3, 14),
1557 .yrgb_hor_scl_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x3, 12),
1558 .bic_coe_sel = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x3, 2),
1559 .vsd_yrgb_gt2 = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x1, 28),
1560 .vsd_yrgb_gt4 = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x1, 29),
1561 };
1562
1563 static const struct vop2_scl_regs rk3568_esmart_win_scl = {
1564 .scale_yrgb_x = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1565 .scale_yrgb_y = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB, 0xffff, 16),
1566 .scale_cbcr_x = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_CBR, 0xffff, 0x0),
1567 .scale_cbcr_y = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_CBR, 0xffff, 16),
1568 .yrgb_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 0),
1569 .yrgb_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 2),
1570 .yrgb_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 4),
1571 .yrgb_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 6),
1572 .cbcr_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 8),
1573 .cbcr_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 10),
1574 .cbcr_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 12),
1575 .cbcr_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 14),
1576 .bic_coe_sel = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 16),
1577 .vsd_yrgb_gt2 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 8),
1578 .vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 9),
1579 .vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 10),
1580 .vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 11),
1581 };
1582
1583 static const struct vop2_scl_regs rk3568_area1_scl = {
1584 .scale_yrgb_x = VOP_REG(RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB, 0xffff, 0x0),
1585 .scale_yrgb_y = VOP_REG(RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB, 0xffff, 16),
1586 .scale_cbcr_x = VOP_REG(RK3568_ESMART0_REGION1_SCL_FACTOR_CBR, 0xffff, 0x0),
1587 .scale_cbcr_y = VOP_REG(RK3568_ESMART0_REGION1_SCL_FACTOR_CBR, 0xffff, 16),
1588 .yrgb_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION1_SCL_CTRL, 0x3, 0),
1589 .yrgb_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION1_SCL_CTRL, 0x3, 2),
1590 .yrgb_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION1_SCL_CTRL, 0x3, 4),
1591 .yrgb_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION1_SCL_CTRL, 0x3, 6),
1592 .cbcr_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION1_SCL_CTRL, 0x3, 8),
1593 .cbcr_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION1_SCL_CTRL, 0x3, 10),
1594 .cbcr_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION1_SCL_CTRL, 0x3, 12),
1595 .cbcr_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION1_SCL_CTRL, 0x3, 14),
1596 .bic_coe_sel = VOP_REG(RK3568_ESMART0_REGION1_SCL_CTRL, 0x3, 16),
1597 .vsd_yrgb_gt2 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 8),
1598 .vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 9),
1599 .vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 10),
1600 .vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 11),
1601 };
1602
1603 static const struct vop2_scl_regs rk3568_area2_scl = {
1604 .scale_yrgb_x = VOP_REG(RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB, 0xffff, 0x0),
1605 .scale_yrgb_y = VOP_REG(RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB, 0xffff, 16),
1606 .scale_cbcr_x = VOP_REG(RK3568_ESMART0_REGION2_SCL_FACTOR_CBR, 0xffff, 0x0),
1607 .scale_cbcr_y = VOP_REG(RK3568_ESMART0_REGION2_SCL_FACTOR_CBR, 0xffff, 16),
1608 .yrgb_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION2_SCL_CTRL, 0x3, 0),
1609 .yrgb_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION2_SCL_CTRL, 0x3, 2),
1610 .yrgb_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION2_SCL_CTRL, 0x3, 4),
1611 .yrgb_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION2_SCL_CTRL, 0x3, 6),
1612 .cbcr_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION2_SCL_CTRL, 0x3, 8),
1613 .cbcr_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION2_SCL_CTRL, 0x3, 10),
1614 .cbcr_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION2_SCL_CTRL, 0x3, 12),
1615 .cbcr_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION2_SCL_CTRL, 0x3, 14),
1616 .bic_coe_sel = VOP_REG(RK3568_ESMART0_REGION2_SCL_CTRL, 0x3, 16),
1617 .vsd_yrgb_gt2 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 8),
1618 .vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 9),
1619 .vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 10),
1620 .vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 11),
1621 };
1622
1623 static const struct vop2_scl_regs rk3568_area3_scl = {
1624 .scale_yrgb_x = VOP_REG(RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB, 0xffff, 0x0),
1625 .scale_yrgb_y = VOP_REG(RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB, 0xffff, 16),
1626 .scale_cbcr_x = VOP_REG(RK3568_ESMART0_REGION3_SCL_FACTOR_CBR, 0xffff, 0x0),
1627 .scale_cbcr_y = VOP_REG(RK3568_ESMART0_REGION3_SCL_FACTOR_CBR, 0xffff, 16),
1628 .yrgb_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION3_SCL_CTRL, 0x3, 0),
1629 .yrgb_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION3_SCL_CTRL, 0x3, 2),
1630 .yrgb_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION3_SCL_CTRL, 0x3, 4),
1631 .yrgb_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION3_SCL_CTRL, 0x3, 6),
1632 .cbcr_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION3_SCL_CTRL, 0x3, 8),
1633 .cbcr_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION3_SCL_CTRL, 0x3, 10),
1634 .cbcr_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION3_SCL_CTRL, 0x3, 12),
1635 .cbcr_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION3_SCL_CTRL, 0x3, 14),
1636 .bic_coe_sel = VOP_REG(RK3568_ESMART0_REGION3_SCL_CTRL, 0x3, 16),
1637 .vsd_yrgb_gt2 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 8),
1638 .vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 9),
1639 .vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 10),
1640 .vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 11),
1641 };
1642
1643 static const struct vop2_win_regs rk3568_area1_data = {
1644 .scl = &rk3568_area1_scl,
1645 .enable = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 0),
1646 .format = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1f, 1),
1647 .rb_swap = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 14),
1648 .uv_swap = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 16),
1649 .act_info = VOP_REG(RK3568_ESMART0_REGION1_ACT_INFO, 0x1fff1fff, 0),
1650 .dsp_info = VOP_REG(RK3568_ESMART0_REGION1_DSP_INFO, 0x1fff1fff, 0),
1651 .dsp_st = VOP_REG(RK3568_ESMART0_REGION1_DSP_ST, 0x1fff1fff, 0),
1652 .yrgb_mst = VOP_REG(RK3568_ESMART0_REGION1_YRGB_MST, 0xffffffff, 0),
1653 .uv_mst = VOP_REG(RK3568_ESMART0_REGION1_CBR_MST, 0xffffffff, 0),
1654 .yrgb_vir = VOP_REG(RK3568_ESMART0_REGION1_VIR, 0xffff, 0),
1655 .uv_vir = VOP_REG(RK3568_ESMART0_REGION1_VIR, 0xffff, 16),
1656 };
1657
1658 static const struct vop2_win_regs rk3568_area2_data = {
1659 .scl = &rk3568_area2_scl,
1660 .enable = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 0),
1661 .format = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1f, 1),
1662 .rb_swap = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 14),
1663 .uv_swap = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 16),
1664 .act_info = VOP_REG(RK3568_ESMART0_REGION2_ACT_INFO, 0x1fff1fff, 0),
1665 .dsp_info = VOP_REG(RK3568_ESMART0_REGION2_DSP_INFO, 0x0fff0fff, 0),
1666 .dsp_st = VOP_REG(RK3568_ESMART0_REGION2_DSP_ST, 0x1fff1fff, 0),
1667 .yrgb_mst = VOP_REG(RK3568_ESMART0_REGION2_YRGB_MST, 0xffffffff, 0),
1668 .uv_mst = VOP_REG(RK3568_ESMART0_REGION2_CBR_MST, 0xffffffff, 0),
1669 .yrgb_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 0),
1670 .uv_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 16),
1671 };
1672
1673 static const struct vop2_win_regs rk3568_area3_data = {
1674 .scl = &rk3568_area3_scl,
1675 .enable = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 0),
1676 .format = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1f, 1),
1677 .rb_swap = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 14),
1678 .uv_swap = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 16),
1679 .act_info = VOP_REG(RK3568_ESMART0_REGION3_ACT_INFO, 0x1fff1fff, 0),
1680 .dsp_info = VOP_REG(RK3568_ESMART0_REGION3_DSP_INFO, 0x0fff0fff, 0),
1681 .dsp_st = VOP_REG(RK3568_ESMART0_REGION3_DSP_ST, 0x1fff1fff, 0),
1682 .yrgb_mst = VOP_REG(RK3568_ESMART0_REGION3_YRGB_MST, 0xffffffff, 0),
1683 .uv_mst = VOP_REG(RK3568_ESMART0_REGION3_CBR_MST, 0xffffffff, 0),
1684 .yrgb_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 0),
1685 .uv_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 16),
1686 };
1687
1688 static const struct vop2_win_regs *rk3568_area_data[] = {
1689 &rk3568_area1_data,
1690 &rk3568_area2_data,
1691 &rk3568_area3_data
1692 };
1693
1694 static const struct vop2_win_regs rk3568_cluster0_win_data = {
1695 .scl = &rk3568_cluster0_win_scl,
1696 .afbc = &rk3568_cluster0_afbc,
1697 .cluster = &rk3568_vop_cluster0,
1698 .enable = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0),
1699 .format = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1f, 1),
1700 .rb_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 14),
1701 .dither_up = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 18),
1702 .act_info = VOP_REG(RK3568_CLUSTER0_WIN0_ACT_INFO, 0x1fff1fff, 0),
1703 .dsp_info = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_INFO, 0x1fff1fff, 0),
1704 .dsp_st = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_ST, 0x1fff1fff, 0),
1705 .yrgb_mst = VOP_REG(RK3568_CLUSTER0_WIN0_YRGB_MST, 0xffffffff, 0),
1706 .uv_mst = VOP_REG(RK3568_CLUSTER0_WIN0_CBR_MST, 0xffffffff, 0),
1707 .yrgb_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 0),
1708 .uv_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 16),
1709 .y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8),
1710 .r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9),
1711 .csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x3, 10),
1712 .axi_yrgb_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 0),
1713 .axi_uv_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 5),
1714 .axi_id = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 13),
1715 };
1716
1717 static const struct vop2_win_regs rk3568_cluster1_win_data = {
1718 .scl = &rk3568_cluster1_win_scl,
1719 .afbc = &rk3568_cluster1_afbc,
1720 .cluster = &rk3568_vop_cluster1,
1721 .enable = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0),
1722 .format = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1f, 1),
1723 .rb_swap = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 14),
1724 .dither_up = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 18),
1725 .act_info = VOP_REG(RK3568_CLUSTER1_WIN0_ACT_INFO, 0x1fff1fff, 0),
1726 .dsp_info = VOP_REG(RK3568_CLUSTER1_WIN0_DSP_INFO, 0x1fff1fff, 0),
1727 .dsp_st = VOP_REG(RK3568_CLUSTER1_WIN0_DSP_ST, 0x1fff1fff, 0),
1728 .yrgb_mst = VOP_REG(RK3568_CLUSTER1_WIN0_YRGB_MST, 0xffffffff, 0),
1729 .uv_mst = VOP_REG(RK3568_CLUSTER1_WIN0_CBR_MST, 0xffffffff, 0),
1730 .yrgb_vir = VOP_REG(RK3568_CLUSTER1_WIN0_VIR, 0xffff, 0),
1731 .uv_vir = VOP_REG(RK3568_CLUSTER1_WIN0_VIR, 0xffff, 16),
1732 .y2r_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 8),
1733 .r2y_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 9),
1734 .csc_mode = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x3, 10),
1735 .axi_yrgb_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 0),
1736 .axi_uv_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 5),
1737 .axi_id = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 13),
1738 };
1739
1740 static const struct vop2_win_regs rk3588_cluster2_win_data = {
1741 .scl = &rk3588_cluster2_win_scl,
1742 .afbc = &rk3588_cluster2_afbc,
1743 .cluster = &rk3588_vop_cluster2,
1744 .enable = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 0),
1745 .format = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1f, 1),
1746 .rb_swap = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 14),
1747 .act_info = VOP_REG(RK3588_CLUSTER2_WIN0_ACT_INFO, 0x1fff1fff, 0),
1748 .dsp_info = VOP_REG(RK3588_CLUSTER2_WIN0_DSP_INFO, 0x1fff1fff, 0),
1749 .dsp_st = VOP_REG(RK3588_CLUSTER2_WIN0_DSP_ST, 0x1fff1fff, 0),
1750 .yrgb_mst = VOP_REG(RK3588_CLUSTER2_WIN0_YRGB_MST, 0xffffffff, 0),
1751 .uv_mst = VOP_REG(RK3588_CLUSTER2_WIN0_CBR_MST, 0xffffffff, 0),
1752 .yrgb_vir = VOP_REG(RK3588_CLUSTER2_WIN0_VIR, 0xffff, 0),
1753 .uv_vir = VOP_REG(RK3588_CLUSTER2_WIN0_VIR, 0xffff, 16),
1754 .y2r_en = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 8),
1755 .r2y_en = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 9),
1756 .csc_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x3, 10),
1757 .axi_yrgb_id = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL2, 0x1f, 0),
1758 .axi_uv_id = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL2, 0x1f, 5),
1759 .axi_id = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 13),
1760 };
1761
1762 static const struct vop2_win_regs rk3588_cluster3_win_data = {
1763 .scl = &rk3588_cluster3_win_scl,
1764 .afbc = &rk3588_cluster3_afbc,
1765 .cluster = &rk3588_vop_cluster3,
1766 .enable = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 0),
1767 .format = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1f, 1),
1768 .rb_swap = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 14),
1769 .act_info = VOP_REG(RK3588_CLUSTER3_WIN0_ACT_INFO, 0x1fff1fff, 0),
1770 .dsp_info = VOP_REG(RK3588_CLUSTER3_WIN0_DSP_INFO, 0x1fff1fff, 0),
1771 .dsp_st = VOP_REG(RK3588_CLUSTER3_WIN0_DSP_ST, 0x1fff1fff, 0),
1772 .yrgb_mst = VOP_REG(RK3588_CLUSTER3_WIN0_YRGB_MST, 0xffffffff, 0),
1773 .uv_mst = VOP_REG(RK3588_CLUSTER3_WIN0_CBR_MST, 0xffffffff, 0),
1774 .yrgb_vir = VOP_REG(RK3588_CLUSTER3_WIN0_VIR, 0xffff, 0),
1775 .uv_vir = VOP_REG(RK3588_CLUSTER3_WIN0_VIR, 0xffff, 16),
1776 .y2r_en = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 8),
1777 .r2y_en = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 9),
1778 .csc_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x3, 10),
1779 .axi_yrgb_id = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL2, 0x1f, 0),
1780 .axi_uv_id = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL2, 0x1f, 5),
1781 .axi_id = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 13),
1782 };
1783
1784 static const struct vop2_win_regs rk3568_esmart_win_data = {
1785 .scl = &rk3568_esmart_win_scl,
1786 .axi_yrgb_id = VOP_REG(RK3568_ESMART0_CTRL1, 0x1f, 4),
1787 .axi_uv_id = VOP_REG(RK3568_ESMART0_CTRL1, 0x1f, 12),
1788 .axi_id = VOP_REG(RK3568_ESMART0_AXI_CTRL, 0x1, 1),
1789 .enable = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0),
1790 .format = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1f, 1),
1791 .dither_up = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 12),
1792 .rb_swap = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 14),
1793 .uv_swap = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 16),
1794 .act_info = VOP_REG(RK3568_ESMART0_REGION0_ACT_INFO, 0x1fff1fff, 0),
1795 .dsp_info = VOP_REG(RK3568_ESMART0_REGION0_DSP_INFO, 0x1fff1fff, 0),
1796 .dsp_st = VOP_REG(RK3568_ESMART0_REGION0_DSP_ST, 0x1fff1fff, 0),
1797 .yrgb_mst = VOP_REG(RK3568_ESMART0_REGION0_YRGB_MST, 0xffffffff, 0),
1798 .uv_mst = VOP_REG(RK3568_ESMART0_REGION0_CBR_MST, 0xffffffff, 0),
1799 .yrgb_vir = VOP_REG(RK3568_ESMART0_REGION0_VIR, 0xffff, 0),
1800 .uv_vir = VOP_REG(RK3568_ESMART0_REGION0_VIR, 0xffff, 16),
1801 .y2r_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 0),
1802 .r2y_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 1),
1803 .csc_mode = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 2),
1804 .ymirror = VOP_REG(RK3568_ESMART0_CTRL1, 0x1, 31),
1805 .color_key = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x3fffffff, 0),
1806 .color_key_en = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x1, 31),
1807 };
1808
1809 /*
1810 * rk3568 vop with 2 cluster, 2 esmart win, 2 smart win.
1811 * Every cluster can work as 4K win or split into two win.
1812 * All win in cluster support AFBCD.
1813 *
1814 * Every esmart win and smart win support 4 Multi-region.
1815 *
1816 * Scale filter mode:
1817 *
1818 * * Cluster: bicubic for horizontal scale up, others use bilinear
1819 * * ESmart:
1820 * * nearest-neighbor/bilinear/bicubic for scale up
1821 * * nearest-neighbor/bilinear/average for scale down
1822 *
1823 *
1824 * @TODO describe the wind like cpu-map dt nodes;
1825 */
1826 static const struct vop2_win_data rk3568_vop_win_data[] = {
1827 {
1828 .name = "Smart0-win0",
1829 .phys_id = ROCKCHIP_VOP2_SMART0,
1830 .base = 0x400,
1831 .formats = formats_for_smart,
1832 .nformats = ARRAY_SIZE(formats_for_smart),
1833 .format_modifiers = format_modifiers,
1834 .layer_sel_id = 3,
1835 .supported_rotations = DRM_MODE_REFLECT_Y,
1836 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1837 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1838 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1839 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1840 .regs = &rk3568_esmart_win_data,
1841 .area = rk3568_area_data,
1842 .area_size = ARRAY_SIZE(rk3568_area_data),
1843 .type = DRM_PLANE_TYPE_PRIMARY,
1844 .max_upscale_factor = 8,
1845 .max_downscale_factor = 8,
1846 .dly = { 20, 47, 41 },
1847 .feature = WIN_FEATURE_MULTI_AREA,
1848 },
1849
1850 {
1851 .name = "Smart1-win0",
1852 .phys_id = ROCKCHIP_VOP2_SMART1,
1853 .formats = formats_for_smart,
1854 .nformats = ARRAY_SIZE(formats_for_smart),
1855 .format_modifiers = format_modifiers,
1856 .base = 0x600,
1857 .layer_sel_id = 7,
1858 .supported_rotations = DRM_MODE_REFLECT_Y,
1859 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1860 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1861 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1862 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1863 .regs = &rk3568_esmart_win_data,
1864 .area = rk3568_area_data,
1865 .area_size = ARRAY_SIZE(rk3568_area_data),
1866 .type = DRM_PLANE_TYPE_PRIMARY,
1867 .max_upscale_factor = 8,
1868 .max_downscale_factor = 8,
1869 .dly = { 20, 47, 41 },
1870 .feature = WIN_FEATURE_MIRROR | WIN_FEATURE_MULTI_AREA,
1871 },
1872
1873 {
1874 .name = "Esmart1-win0",
1875 .phys_id = ROCKCHIP_VOP2_ESMART1,
1876 .formats = formats_for_rk356x_esmart,
1877 .nformats = ARRAY_SIZE(formats_for_rk356x_esmart),
1878 .format_modifiers = format_modifiers,
1879 .base = 0x200,
1880 .layer_sel_id = 6,
1881 .supported_rotations = DRM_MODE_REFLECT_Y,
1882 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1883 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1884 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1885 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1886 .regs = &rk3568_esmart_win_data,
1887 .area = rk3568_area_data,
1888 .area_size = ARRAY_SIZE(rk3568_area_data),
1889 .type = DRM_PLANE_TYPE_PRIMARY,
1890 .max_upscale_factor = 8,
1891 .max_downscale_factor = 8,
1892 .dly = { 20, 47, 41 },
1893 .feature = WIN_FEATURE_MIRROR | WIN_FEATURE_MULTI_AREA,
1894 },
1895
1896 {
1897 .name = "Esmart0-win0",
1898 .phys_id = ROCKCHIP_VOP2_ESMART0,
1899 .formats = formats_for_rk356x_esmart,
1900 .nformats = ARRAY_SIZE(formats_for_rk356x_esmart),
1901 .format_modifiers = format_modifiers,
1902 .base = 0x0,
1903 .layer_sel_id = 2,
1904 .supported_rotations = DRM_MODE_REFLECT_Y,
1905 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1906 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1907 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1908 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1909 .regs = &rk3568_esmart_win_data,
1910 .area = rk3568_area_data,
1911 .area_size = ARRAY_SIZE(rk3568_area_data),
1912 .type = DRM_PLANE_TYPE_OVERLAY,
1913 .max_upscale_factor = 8,
1914 .max_downscale_factor = 8,
1915 .dly = { 20, 47, 41 },
1916 .feature = WIN_FEATURE_MULTI_AREA,
1917 },
1918
1919 {
1920 .name = "Cluster0-win0",
1921 .phys_id = ROCKCHIP_VOP2_CLUSTER0,
1922 .base = 0x00,
1923 .formats = formats_for_cluster,
1924 .nformats = ARRAY_SIZE(formats_for_cluster),
1925 .format_modifiers = format_modifiers_afbc,
1926 .layer_sel_id = 0,
1927 .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
1928 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
1929 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1930 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1931 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1932 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1933 .regs = &rk3568_cluster0_win_data,
1934 .max_upscale_factor = 4,
1935 .max_downscale_factor = 4,
1936 .dly = { 0, 27, 21 },
1937 .type = DRM_PLANE_TYPE_OVERLAY,
1938 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
1939 },
1940
1941 {
1942 .name = "Cluster0-win1",
1943 .phys_id = ROCKCHIP_VOP2_CLUSTER0,
1944 .base = 0x80,
1945 .layer_sel_id = -1,
1946 .formats = formats_for_cluster,
1947 .nformats = ARRAY_SIZE(formats_for_cluster),
1948 .format_modifiers = format_modifiers_afbc,
1949 .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
1950 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1951 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1952 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1953 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1954 .regs = &rk3568_cluster0_win_data,
1955 .max_upscale_factor = 4,
1956 .max_downscale_factor = 4,
1957 .type = DRM_PLANE_TYPE_OVERLAY,
1958 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
1959 },
1960
1961 {
1962 .name = "Cluster1-win0",
1963 .phys_id = ROCKCHIP_VOP2_CLUSTER1,
1964 .base = 0x00,
1965 .formats = formats_for_cluster,
1966 .nformats = ARRAY_SIZE(formats_for_cluster),
1967 .format_modifiers = format_modifiers_afbc,
1968 .layer_sel_id = 1,
1969 .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
1970 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
1971 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1972 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1973 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1974 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1975 .regs = &rk3568_cluster1_win_data,
1976 .type = DRM_PLANE_TYPE_OVERLAY,
1977 .max_upscale_factor = 4,
1978 .max_downscale_factor = 4,
1979 .dly = { 0, 27, 21 },
1980 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_MIRROR,
1981 },
1982
1983 {
1984 .name = "Cluster1-win1",
1985 .phys_id = ROCKCHIP_VOP2_CLUSTER1,
1986 .layer_sel_id = -1,
1987 .formats = formats_for_cluster,
1988 .nformats = ARRAY_SIZE(formats_for_cluster),
1989 .format_modifiers = format_modifiers_afbc,
1990 .base = 0x80,
1991 .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
1992 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1993 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1994 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1995 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1996 .regs = &rk3568_cluster1_win_data,
1997 .type = DRM_PLANE_TYPE_OVERLAY,
1998 .max_upscale_factor = 4,
1999 .max_downscale_factor = 4,
2000 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB | WIN_FEATURE_MIRROR,
2001 },
2002 };
2003
2004 const struct vop2_power_domain_regs rk3588_cluster0_pd_regs = {
2005 .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 0),
2006 .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 8),
2007 .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 9),
2008 .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 9),
2009 };
2010
2011 const struct vop2_power_domain_regs rk3588_cluster1_pd_regs = {
2012 .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 1),
2013 .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 9),
2014 .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 10),
2015 .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 10),
2016 };
2017
2018 const struct vop2_power_domain_regs rk3588_cluster2_pd_regs = {
2019 .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 2),
2020 .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 10),
2021 .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 11),
2022 .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 11),
2023 };
2024
2025 const struct vop2_power_domain_regs rk3588_cluster3_pd_regs = {
2026 .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 3),
2027 .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 11),
2028 .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 12),
2029 .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 12),
2030 };
2031
2032 const struct vop2_power_domain_regs rk3588_esmart_pd_regs = {
2033 .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 7),
2034 .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 15),
2035 .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 15),
2036 .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 15),
2037 };
2038
2039 const struct vop2_power_domain_regs rk3588_dsc_8k_pd_regs = {
2040 .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 5),
2041 .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 13),
2042 .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 13),
2043 .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 13),
2044 };
2045
2046 const struct vop2_power_domain_regs rk3588_dsc_4k_pd_regs = {
2047 .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 6),
2048 .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 14),
2049 .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 14),
2050 .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 14),
2051 };
2052
2053 /*
2054 * There are 7 internal power domains on rk3588 vop,
2055 * Cluster0/1/2/3 each have on pd, and PD_CLUSTER0 as parent,
2056 * that means PD_CLUSTER0 should turn on first before
2057 * PD_CLUSTER1/2/3 turn on.
2058 *
2059 * Esmart0/1/2/3 share one pd PD_ESMART0.
2060 * DSC_8K/DSC_4K each have on pd.
2061 */
2062 static const struct vop2_power_domain_data rk3588_vop_pd_data[] = {
2063 {
2064 .id = VOP2_PD_CLUSTER0,
2065 .regs = &rk3588_cluster0_pd_regs,
2066 },
2067
2068 {
2069 .id = VOP2_PD_CLUSTER1,
2070 .parent_id = VOP2_PD_CLUSTER0,
2071 .regs = &rk3588_cluster1_pd_regs,
2072 },
2073
2074 {
2075 .id = VOP2_PD_CLUSTER2,
2076 .parent_id = VOP2_PD_CLUSTER0,
2077 .regs = &rk3588_cluster2_pd_regs,
2078 },
2079
2080 {
2081 .id = VOP2_PD_CLUSTER3,
2082 .parent_id = VOP2_PD_CLUSTER0,
2083 .regs = &rk3588_cluster3_pd_regs,
2084 },
2085
2086 {
2087 .id = VOP2_PD_ESMART0,
2088 .regs = &rk3588_esmart_pd_regs,
2089 },
2090
2091 {
2092 .id = VOP2_PD_DSC_8K,
2093 .regs = &rk3588_dsc_8k_pd_regs,
2094 },
2095
2096 {
2097 .id = VOP2_PD_DSC_4K,
2098 .regs = &rk3588_dsc_4k_pd_regs,
2099 },
2100 };
2101
2102 const struct vop2_power_domain_regs rk3588_mem_pg_vp0_regs = {
2103 .pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON1, 0x1, 15),
2104 .status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 19),
2105 };
2106
2107 const struct vop2_power_domain_regs rk3588_mem_pg_vp1_regs = {
2108 .pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 0),
2109 .status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 20),
2110 };
2111
2112 const struct vop2_power_domain_regs rk3588_mem_pg_vp2_regs = {
2113 .pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 1),
2114 .status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 21),
2115 };
2116
2117 const struct vop2_power_domain_regs rk3588_mem_pg_vp3_regs = {
2118 .pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 2),
2119 .status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 22),
2120 };
2121
2122 const struct vop2_power_domain_regs rk3588_mem_pg_db0_regs = {
2123 .pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 3),
2124 .status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 23),
2125 };
2126
2127 const struct vop2_power_domain_regs rk3588_mem_pg_db1_regs = {
2128 .pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 4),
2129 .status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 24),
2130 };
2131
2132 const struct vop2_power_domain_regs rk3588_mem_pg_db2_regs = {
2133 .pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 5),
2134 .status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 25),
2135 };
2136
2137 const struct vop2_power_domain_regs rk3588_mem_pg_wb_regs = {
2138 .pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 6),
2139 .status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 26),
2140 };
2141
2142 /*
2143 * All power gates will power on when PD_VOP is turn on.
2144 * Corresponding mem_pwr_ack_bypass bit should be enabled
2145 * if power gate powe down before PD_VOP.
2146 * power gates take effect immediately, this means there
2147 * is no synchronization between vop frame scanout, so
2148 * we can only enable a power gate before we enable
2149 * a module, and turn off power gate after the module
2150 * is actually disabled.
2151 */
2152 static const struct vop2_power_domain_data rk3588_vop_mem_pg_data[] = {
2153 {
2154 .id = VOP2_MEM_PG_VP0,
2155 .regs = &rk3588_mem_pg_vp0_regs,
2156 },
2157
2158 {
2159 .id = VOP2_MEM_PG_VP1,
2160 .regs = &rk3588_mem_pg_vp1_regs,
2161 },
2162
2163 {
2164 .id = VOP2_MEM_PG_VP2,
2165 .regs = &rk3588_mem_pg_vp2_regs,
2166 },
2167
2168 {
2169 .id = VOP2_MEM_PG_VP3,
2170 .regs = &rk3588_mem_pg_vp3_regs,
2171 },
2172
2173 {
2174 .id = VOP2_MEM_PG_DB0,
2175 .regs = &rk3588_mem_pg_db0_regs,
2176 },
2177
2178 {
2179 .id = VOP2_MEM_PG_DB1,
2180 .regs = &rk3588_mem_pg_db1_regs,
2181 },
2182
2183 {
2184 .id = VOP2_MEM_PG_DB2,
2185 .regs = &rk3588_mem_pg_db2_regs,
2186 },
2187
2188 {
2189 .id = VOP2_MEM_PG_WB,
2190 .regs = &rk3588_mem_pg_wb_regs,
2191 },
2192 };
2193
2194 /*
2195 * rk3588 vop with 4 cluster, 4 esmart win.
2196 * Every cluster can work as 4K win or split into two win.
2197 * All win in cluster support AFBCD.
2198 *
2199 * Every esmart win and smart win support 4 Multi-region.
2200 *
2201 * Scale filter mode:
2202 *
2203 * * Cluster: bicubic for horizontal scale up, others use bilinear
2204 * * ESmart:
2205 * * nearest-neighbor/bilinear/bicubic for scale up
2206 * * nearest-neighbor/bilinear/average for scale down
2207 *
2208 * AXI Read ID assignment:
2209 * Two AXI bus:
2210 * AXI0 is a read/write bus with a higher performance.
2211 * AXI1 is a read only bus.
2212 *
2213 * Every window on a AXI bus must assigned two unique
2214 * read id(yrgb_id/uv_id, valid id are 0x1~0xe).
2215 *
2216 * AXI0:
2217 * Cluster0/1, Esmart0/1, WriteBack
2218 *
2219 * AXI 1:
2220 * Cluster2/3, Esmart2/3
2221 *
2222 * @TODO describe the wind like cpu-map dt nodes;
2223 */
2224 static const struct vop2_win_data rk3588_vop_win_data[] = {
2225 {
2226 .name = "Cluster0-win0",
2227 .phys_id = ROCKCHIP_VOP2_CLUSTER0,
2228 .splice_win_id = ROCKCHIP_VOP2_CLUSTER1,
2229 .base = 0x00,
2230 .formats = formats_for_cluster,
2231 .nformats = ARRAY_SIZE(formats_for_cluster),
2232 .format_modifiers = format_modifiers_afbc,
2233 .layer_sel_id = 0,
2234 .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
2235 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2236 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2237 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2238 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2239 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2240 .regs = &rk3568_cluster0_win_data,
2241 .pd_id = VOP2_PD_CLUSTER0,
2242 .axi_id = 0,
2243 .axi_yrgb_id = 2,
2244 .axi_uv_id = 3,
2245 .max_upscale_factor = 4,
2246 .max_downscale_factor = 4,
2247 .dly = { 4, 26, 29 },
2248 .type = DRM_PLANE_TYPE_OVERLAY,
2249 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_SPLICE_LEFT,
2250 },
2251
2252 {
2253 .name = "Cluster0-win1",
2254 .phys_id = ROCKCHIP_VOP2_CLUSTER0,
2255 .base = 0x80,
2256 .layer_sel_id = -1,
2257 .formats = formats_for_cluster,
2258 .nformats = ARRAY_SIZE(formats_for_cluster),
2259 .format_modifiers = format_modifiers_afbc,
2260 .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2261 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2262 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2263 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2264 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2265 .regs = &rk3568_cluster0_win_data,
2266 .axi_id = 0,
2267 .axi_yrgb_id = 4,
2268 .axi_uv_id = 5,
2269 .max_upscale_factor = 4,
2270 .max_downscale_factor = 4,
2271 .type = DRM_PLANE_TYPE_OVERLAY,
2272 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
2273 },
2274
2275 {
2276 .name = "Cluster1-win0",
2277 .phys_id = ROCKCHIP_VOP2_CLUSTER1,
2278 .base = 0x00,
2279 .formats = formats_for_cluster,
2280 .nformats = ARRAY_SIZE(formats_for_cluster),
2281 .format_modifiers = format_modifiers_afbc,
2282 .layer_sel_id = 1,
2283 .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
2284 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2285 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2286 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2287 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2288 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2289 .regs = &rk3568_cluster1_win_data,
2290 .pd_id = VOP2_PD_CLUSTER1,
2291 .axi_id = 0,
2292 .axi_yrgb_id = 6,
2293 .axi_uv_id = 7,
2294 .type = DRM_PLANE_TYPE_OVERLAY,
2295 .max_upscale_factor = 4,
2296 .max_downscale_factor = 4,
2297 .dly = { 4, 26, 29 },
2298 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
2299 },
2300
2301 {
2302 .name = "Cluster1-win1",
2303 .phys_id = ROCKCHIP_VOP2_CLUSTER1,
2304 .layer_sel_id = -1,
2305 .formats = formats_for_cluster,
2306 .nformats = ARRAY_SIZE(formats_for_cluster),
2307 .format_modifiers = format_modifiers_afbc,
2308 .base = 0x80,
2309 .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2310 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2311 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2312 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2313 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2314 .regs = &rk3568_cluster1_win_data,
2315 .type = DRM_PLANE_TYPE_OVERLAY,
2316 .axi_id = 0,
2317 .axi_yrgb_id = 8,
2318 .axi_uv_id = 9,
2319 .max_upscale_factor = 4,
2320 .max_downscale_factor = 4,
2321 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
2322 },
2323
2324 {
2325 .name = "Cluster2-win0",
2326 .phys_id = ROCKCHIP_VOP2_CLUSTER2,
2327 .pd_id = VOP2_PD_CLUSTER2,
2328 .splice_win_id = ROCKCHIP_VOP2_CLUSTER3,
2329 .base = 0x00,
2330 .formats = formats_for_cluster,
2331 .nformats = ARRAY_SIZE(formats_for_cluster),
2332 .format_modifiers = format_modifiers_afbc,
2333 .layer_sel_id = 4,
2334 .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
2335 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2336 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2337 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2338 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2339 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2340 .regs = &rk3588_cluster2_win_data,
2341 .type = DRM_PLANE_TYPE_OVERLAY,
2342 .axi_id = 1,
2343 .axi_yrgb_id = 2,
2344 .axi_uv_id = 3,
2345 .max_upscale_factor = 4,
2346 .max_downscale_factor = 4,
2347 .dly = { 4, 26, 29 },
2348 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_SPLICE_LEFT,
2349 },
2350
2351 {
2352 .name = "Cluster2-win1",
2353 .phys_id = ROCKCHIP_VOP2_CLUSTER2,
2354 .layer_sel_id = -1,
2355 .formats = formats_for_cluster,
2356 .nformats = ARRAY_SIZE(formats_for_cluster),
2357 .format_modifiers = format_modifiers_afbc,
2358 .base = 0x80,
2359 .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2360 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2361 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2362 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2363 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2364 .regs = &rk3588_cluster2_win_data,
2365 .type = DRM_PLANE_TYPE_OVERLAY,
2366 .axi_id = 1,
2367 .axi_yrgb_id = 4,
2368 .axi_uv_id = 5,
2369 .max_upscale_factor = 4,
2370 .max_downscale_factor = 4,
2371 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
2372 },
2373
2374 {
2375 .name = "Cluster3-win0",
2376 .phys_id = ROCKCHIP_VOP2_CLUSTER3,
2377 .pd_id = VOP2_PD_CLUSTER3,
2378 .base = 0x00,
2379 .formats = formats_for_cluster,
2380 .nformats = ARRAY_SIZE(formats_for_cluster),
2381 .format_modifiers = format_modifiers_afbc,
2382 .layer_sel_id = 5,
2383 .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
2384 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2385 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2386 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2387 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2388 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2389 .regs = &rk3588_cluster3_win_data,
2390 .type = DRM_PLANE_TYPE_OVERLAY,
2391 .axi_id = 1,
2392 .axi_yrgb_id = 6,
2393 .axi_uv_id = 7,
2394 .max_upscale_factor = 4,
2395 .max_downscale_factor = 4,
2396 .dly = { 4, 26, 29 },
2397 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
2398 },
2399
2400 {
2401 .name = "Cluster3-win1",
2402 .phys_id = ROCKCHIP_VOP2_CLUSTER3,
2403 .layer_sel_id = -1,
2404 .formats = formats_for_cluster,
2405 .nformats = ARRAY_SIZE(formats_for_cluster),
2406 .format_modifiers = format_modifiers_afbc,
2407 .base = 0x80,
2408 .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2409 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2410 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2411 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2412 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2413 .regs = &rk3588_cluster3_win_data,
2414 .type = DRM_PLANE_TYPE_OVERLAY,
2415 .axi_id = 1,
2416 .axi_yrgb_id = 8,
2417 .axi_uv_id = 9,
2418 .max_upscale_factor = 4,
2419 .max_downscale_factor = 4,
2420 .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
2421 },
2422
2423 {
2424 .name = "Esmart0-win0",
2425 .phys_id = ROCKCHIP_VOP2_ESMART0,
2426 .pd_id = VOP2_PD_ESMART0,
2427 .splice_win_id = ROCKCHIP_VOP2_ESMART1,
2428 .formats = formats_for_esmart,
2429 .nformats = ARRAY_SIZE(formats_for_esmart),
2430 .format_modifiers = format_modifiers,
2431 .base = 0x0,
2432 .layer_sel_id = 2,
2433 .supported_rotations = DRM_MODE_REFLECT_Y,
2434 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2435 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2436 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2437 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2438 .regs = &rk3568_esmart_win_data,
2439 .area = rk3568_area_data,
2440 .area_size = ARRAY_SIZE(rk3568_area_data),
2441 .type = DRM_PLANE_TYPE_PRIMARY,
2442 .axi_id = 0,
2443 .axi_yrgb_id = 0x0a,
2444 .axi_uv_id = 0x0b,
2445 .max_upscale_factor = 8,
2446 .max_downscale_factor = 8,
2447 .dly = { 23, 45, 48 },
2448 .feature = WIN_FEATURE_SPLICE_LEFT | WIN_FEATURE_MULTI_AREA,
2449 },
2450
2451 {
2452 .name = "Esmart2-win0",
2453 .phys_id = ROCKCHIP_VOP2_ESMART2,
2454 .pd_id = VOP2_PD_ESMART0,
2455 .splice_win_id = ROCKCHIP_VOP2_ESMART3,
2456 .base = 0x400,
2457 .formats = formats_for_esmart,
2458 .nformats = ARRAY_SIZE(formats_for_esmart),
2459 .format_modifiers = format_modifiers,
2460 .layer_sel_id = 6,
2461 .supported_rotations = DRM_MODE_REFLECT_Y,
2462 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2463 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2464 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2465 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2466 .regs = &rk3568_esmart_win_data,
2467 .area = rk3568_area_data,
2468 .area_size = ARRAY_SIZE(rk3568_area_data),
2469 .type = DRM_PLANE_TYPE_PRIMARY,
2470 .axi_id = 1,
2471 .axi_yrgb_id = 0x0a,
2472 .axi_uv_id = 0x0b,
2473 .max_upscale_factor = 8,
2474 .max_downscale_factor = 8,
2475 .dly = { 23, 45, 48 },
2476 .feature = WIN_FEATURE_SPLICE_LEFT | WIN_FEATURE_MULTI_AREA,
2477 },
2478
2479 {
2480 .name = "Esmart1-win0",
2481 .phys_id = ROCKCHIP_VOP2_ESMART1,
2482 .pd_id = VOP2_PD_ESMART0,
2483 .formats = formats_for_esmart,
2484 .nformats = ARRAY_SIZE(formats_for_esmart),
2485 .format_modifiers = format_modifiers,
2486 .base = 0x200,
2487 .layer_sel_id = 3,
2488 .supported_rotations = DRM_MODE_REFLECT_Y,
2489 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2490 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2491 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2492 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2493 .regs = &rk3568_esmart_win_data,
2494 .area = rk3568_area_data,
2495 .area_size = ARRAY_SIZE(rk3568_area_data),
2496 .type = DRM_PLANE_TYPE_PRIMARY,
2497 .axi_id = 0,
2498 .axi_yrgb_id = 0x0c,
2499 .axi_uv_id = 0x0d,
2500 .max_upscale_factor = 8,
2501 .max_downscale_factor = 8,
2502 .dly = { 23, 45, 48 },
2503 .feature = WIN_FEATURE_MULTI_AREA,
2504 },
2505
2506 {
2507 .name = "Esmart3-win0",
2508 .phys_id = ROCKCHIP_VOP2_ESMART3,
2509 .pd_id = VOP2_PD_ESMART0,
2510 .formats = formats_for_esmart,
2511 .nformats = ARRAY_SIZE(formats_for_esmart),
2512 .format_modifiers = format_modifiers,
2513 .base = 0x600,
2514 .layer_sel_id = 7,
2515 .supported_rotations = DRM_MODE_REFLECT_Y,
2516 .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2517 .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2518 .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2519 .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2520 .regs = &rk3568_esmart_win_data,
2521 .area = rk3568_area_data,
2522 .area_size = ARRAY_SIZE(rk3568_area_data),
2523 .type = DRM_PLANE_TYPE_PRIMARY,
2524 .axi_id = 1,
2525 .axi_yrgb_id = 0x0c,
2526 .axi_uv_id = 0x0d,
2527 .max_upscale_factor = 8,
2528 .max_downscale_factor = 8,
2529 .dly = { 23, 45, 48 },
2530 .feature = WIN_FEATURE_MULTI_AREA,
2531 },
2532 };
2533
2534 static const struct vop_grf_ctrl rk3568_sys_grf_ctrl = {
2535 .grf_bt656_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 1),
2536 .grf_bt1120_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 2),
2537 .grf_dclk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 3),
2538 };
2539
2540 static const struct vop2_ctrl rk3568_vop_ctrl = {
2541 .cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
2542 .wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
2543 .auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
2544 .ovl_cfg_done_port = VOP_REG(RK3568_OVL_CTRL, 0x3, 30),
2545 .ovl_port_mux_cfg_done_imd = VOP_REG(RK3568_OVL_CTRL, 0x1, 28),
2546 .ovl_port_mux_cfg = VOP_REG(RK3568_OVL_PORT_SEL, 0xffff, 0),
2547 .if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
2548 .version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
2549 .lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
2550 .cluster0_src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
2551 .cluster0_dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
2552 .cluster0_src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
2553 .cluster0_dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
2554 .src_color_ctrl = VOP_REG(RK3568_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
2555 .dst_color_ctrl = VOP_REG(RK3568_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
2556 .src_alpha_ctrl = VOP_REG(RK3568_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
2557 .dst_alpha_ctrl = VOP_REG(RK3568_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
2558 .rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
2559 .hdmi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 1),
2560 .edp0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 3),
2561 .mipi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 4),
2562 .mipi1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 20),
2563 .lvds0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 5),
2564 .lvds1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 24),
2565 .bt1120_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 6),
2566 .bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
2567 .rgb_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
2568 .hdmi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 10),
2569 .edp0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 14),
2570 .mipi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
2571 .mipi1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 21),
2572 .lvds0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
2573 .lvds1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 25),
2574 .lvds_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 0),
2575 .lvds_dual_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 1),
2576 .lvds_dual_channel_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 2),
2577 .bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
2578 .bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9),
2579 .gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 0),
2580 .lvds_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
2581 .lvds_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
2582 .hdmi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 4),
2583 .hdmi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 7),
2584 .edp_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x3, 12),
2585 .edp_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 15),
2586 .mipi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 16),
2587 .mipi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 19),
2588 .win_vp_id[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 16),
2589 .win_vp_id[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 18),
2590 .win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 24),
2591 .win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 26),
2592 .win_vp_id[ROCKCHIP_VOP2_SMART0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 28),
2593 .win_vp_id[ROCKCHIP_VOP2_SMART1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 30),
2594 .win_dly[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 0),
2595 .win_dly[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 16),
2596 .win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 0),
2597 .win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 8),
2598 .win_dly[ROCKCHIP_VOP2_SMART0] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 16),
2599 .win_dly[ROCKCHIP_VOP2_SMART1] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
2600 .otp_en = VOP_REG(RK3568_OTP_WIN_EN, 0x1, 0),
2601 };
2602
2603 static const struct vop_grf_ctrl rk3588_sys_grf_ctrl = {
2604 .grf_bt656_clk_inv = VOP_REG(RK3588_GRF_SOC_CON1, 0x1, 14),
2605 .grf_bt1120_clk_inv = VOP_REG(RK3588_GRF_SOC_CON1, 0x1, 14),
2606 .grf_dclk_inv = VOP_REG(RK3588_GRF_SOC_CON1, 0x1, 14),
2607 };
2608
2609 static const struct vop_grf_ctrl rk3588_vop_grf_ctrl = {
2610 .grf_edp0_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 0),
2611 .grf_hdmi0_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 1),
2612 .grf_hdmi0_dsc_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 2),
2613 .grf_edp1_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 3),
2614 .grf_hdmi1_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 4),
2615 .grf_hdmi1_dsc_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 4),
2616 };
2617
2618 static const struct vop_grf_ctrl rk3588_vo1_grf_ctrl = {
2619 .grf_hdmi0_pin_pol = VOP_REG(RK3588_GRF_VO1_CON0, 0x3, 5),
2620 .grf_hdmi1_pin_pol = VOP_REG(RK3588_GRF_VO1_CON0, 0x3, 7),
2621 };
2622
2623 static const struct vop2_ctrl rk3588_vop_ctrl = {
2624 .cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
2625 .wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
2626 .auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
2627 .ovl_cfg_done_port = VOP_REG(RK3568_OVL_CTRL, 0x3, 30),
2628 .ovl_port_mux_cfg_done_imd = VOP_REG(RK3568_OVL_CTRL, 0x1, 28),
2629 .ovl_port_mux_cfg = VOP_REG(RK3568_OVL_PORT_SEL, 0xffff, 0),
2630 .if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
2631 .version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
2632 .lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
2633 .cluster0_src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
2634 .cluster0_dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
2635 .cluster0_src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
2636 .cluster0_dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
2637 .src_color_ctrl = VOP_REG(RK3568_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
2638 .dst_color_ctrl = VOP_REG(RK3568_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
2639 .src_alpha_ctrl = VOP_REG(RK3568_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
2640 .dst_alpha_ctrl = VOP_REG(RK3568_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
2641 .dp0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
2642 .dp1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 1),
2643 .edp0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 2),
2644 .hdmi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 3),
2645 .edp1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 4),
2646 .hdmi1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 5),
2647 .mipi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 6),
2648 .mipi1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
2649 .bt1120_en = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
2650 .bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 9),
2651 .rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 10),
2652 .dp0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 12),
2653 .dp1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 14),
2654 .hdmi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
2655 .edp0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
2656 .hdmi1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
2657 .edp1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
2658 .mipi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x1, 20),
2659 .mipi1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 21),
2660 .bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 1),
2661 .bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
2662 .hdmi_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 8),
2663 .edp_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 8),
2664 .dp_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9),
2665 .mipi_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 10),
2666 .mipi0_ds_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 11),
2667 .mipi1_ds_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 12),
2668 .hdmi0_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 16),
2669 .hdmi0_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 18),
2670 .hdmi1_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 20),
2671 .hdmi1_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 22),
2672 .edp0_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 16),
2673 .edp0_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 18),
2674 .edp1_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 20),
2675 .edp1_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 22),
2676
2677 .mipi0_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 24),
2678 .mipi1_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 26),
2679 /* HDMI pol control by GRF_VO1_CON0
2680 * DP0/1 clk pol is fixed
2681 * MIPI/eDP pol is fixed
2682 */
2683 .rgb_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
2684 .rgb_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
2685 .dp0_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 8),
2686 .dp1_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 12),
2687 .gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 12),
2688 .pd_off_imd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 31),
2689 .win_vp_id[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 16),
2690 .win_vp_id[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 18),
2691 .win_vp_id[ROCKCHIP_VOP2_CLUSTER2] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 20),
2692 .win_vp_id[ROCKCHIP_VOP2_CLUSTER3] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 22),
2693 .win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 24),
2694 .win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 26),
2695 .win_vp_id[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 28),
2696 .win_vp_id[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 30),
2697 .win_dly[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 0),
2698 .win_dly[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 16),
2699 .win_dly[ROCKCHIP_VOP2_CLUSTER2] = VOP_REG(RK3568_CLUSTER_DLY_NUM1, 0xffff, 0),
2700 .win_dly[ROCKCHIP_VOP2_CLUSTER3] = VOP_REG(RK3568_CLUSTER_DLY_NUM1, 0xffff, 16),
2701 .win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 0),
2702 .win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 8),
2703 .win_dly[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 16),
2704 .win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
2705 };
2706
2707 static const struct vop2_data rk3568_vop = {
2708 .version = VOP_VERSION_RK3568,
2709 .nr_vps = 3,
2710 .nr_mixers = 5,
2711 .nr_layers = 6,
2712 .nr_gammas = 1,
2713 .max_input = { 4096, 2304 },
2714 .max_output = { 4096, 2304 },
2715 .ctrl = &rk3568_vop_ctrl,
2716 .sys_grf = &rk3568_sys_grf_ctrl,
2717 .axi_intr = rk3568_vop_axi_intr,
2718 .nr_axi_intr = ARRAY_SIZE(rk3568_vop_axi_intr),
2719 .vp = rk3568_vop_video_ports,
2720 .wb = &rk3568_vop_wb_data,
2721 .layer = rk3568_vop_layers,
2722 .win = rk3568_vop_win_data,
2723 .win_size = ARRAY_SIZE(rk3568_vop_win_data),
2724 };
2725
2726 static const struct vop2_data rk3588_vop = {
2727 .version = VOP_VERSION_RK3588,
2728 .feature = VOP_FEATURE_SPLICE,
2729 .nr_dscs = 2,
2730 .nr_dsc_ecw = ARRAY_SIZE(dsc_ecw),
2731 .nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow),
2732 .nr_vps = 4,
2733 .nr_mixers = 7,
2734 .nr_layers = 8,
2735 .nr_gammas = 4,
2736 .nr_pds = 7,
2737 .max_input = { 4096, 4320 },
2738 .max_output = { 4096, 4320 },
2739 .ctrl = &rk3588_vop_ctrl,
2740 .grf = &rk3588_vop_grf_ctrl,
2741 .sys_grf = &rk3588_sys_grf_ctrl,
2742 .vo1_grf = &rk3588_vo1_grf_ctrl,
2743 .axi_intr = rk3568_vop_axi_intr,
2744 .nr_axi_intr = ARRAY_SIZE(rk3568_vop_axi_intr),
2745 .dsc = rk3588_vop_dsc_data,
2746 .dsc_error_ecw = dsc_ecw,
2747 .dsc_error_buffer_flow = dsc_buffer_flow,
2748 .vp = rk3588_vop_video_ports,
2749 .conn = rk3588_conn_if_data,
2750 .nr_conns = ARRAY_SIZE(rk3588_conn_if_data),
2751 .wb = &rk3568_vop_wb_data,
2752 .layer = rk3568_vop_layers,
2753 .win = rk3588_vop_win_data,
2754 .win_size = ARRAY_SIZE(rk3588_vop_win_data),
2755 .pd = rk3588_vop_pd_data,
2756 .nr_pds = ARRAY_SIZE(rk3588_vop_pd_data),
2757 .mem_pg = rk3588_vop_mem_pg_data,
2758 .nr_mem_pgs = ARRAY_SIZE(rk3588_vop_mem_pg_data),
2759 };
2760
2761 static const struct of_device_id vop2_dt_match[] = {
2762 { .compatible = "rockchip,rk3568-vop",
2763 .data = &rk3568_vop },
2764 { .compatible = "rockchip,rk3588-vop",
2765 .data = &rk3588_vop },
2766
2767 {},
2768 };
2769 MODULE_DEVICE_TABLE(of, vop2_dt_match);
2770
vop2_probe(struct platform_device * pdev)2771 static int vop2_probe(struct platform_device *pdev)
2772 {
2773 struct device *dev = &pdev->dev;
2774
2775 if (!dev->of_node) {
2776 DRM_DEV_ERROR(dev, "can't find vop2 devices\n");
2777 return -ENODEV;
2778 }
2779 return component_add(dev, &vop2_component_ops);
2780 }
2781
vop2_remove(struct platform_device * pdev)2782 static int vop2_remove(struct platform_device *pdev)
2783 {
2784 component_del(&pdev->dev, &vop2_component_ops);
2785
2786 return 0;
2787 }
2788
2789 struct platform_driver vop2_platform_driver = {
2790 .probe = vop2_probe,
2791 .remove = vop2_remove,
2792 .driver = {
2793 .name = "rockchip-vop2",
2794 .of_match_table = of_match_ptr(vop2_dt_match),
2795 },
2796 };
2797