1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
6 *
7 * The Si5341 has 10 outputs and 5 synthesizers.
8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
11 * The Si5342 and Si5344 are smaller versions of the Si5345.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/gcd.h>
18 #include <linux/math64.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <asm/unaligned.h>
25
26 #define SI5341_NUM_INPUTS 4
27
28 #define SI5340_MAX_NUM_OUTPUTS 4
29 #define SI5341_MAX_NUM_OUTPUTS 10
30 #define SI5342_MAX_NUM_OUTPUTS 2
31 #define SI5344_MAX_NUM_OUTPUTS 4
32 #define SI5345_MAX_NUM_OUTPUTS 10
33
34 #define SI5340_NUM_SYNTH 4
35 #define SI5341_NUM_SYNTH 5
36 #define SI5342_NUM_SYNTH 2
37 #define SI5344_NUM_SYNTH 4
38 #define SI5345_NUM_SYNTH 5
39
40 /* Range of the synthesizer fractional divider */
41 #define SI5341_SYNTH_N_MIN 10
42 #define SI5341_SYNTH_N_MAX 4095
43
44 /* The chip can get its input clock from 3 input pins or an XTAL */
45
46 /* There is one PLL running at 13500–14256 MHz */
47 #define SI5341_PLL_VCO_MIN 13500000000ull
48 #define SI5341_PLL_VCO_MAX 14256000000ull
49
50 /* The 5 frequency synthesizers obtain their input from the PLL */
51 struct clk_si5341_synth {
52 struct clk_hw hw;
53 struct clk_si5341 *data;
54 u8 index;
55 };
56 #define to_clk_si5341_synth(_hw) \
57 container_of(_hw, struct clk_si5341_synth, hw)
58
59 /* The output stages can be connected to any synth (full mux) */
60 struct clk_si5341_output {
61 struct clk_hw hw;
62 struct clk_si5341 *data;
63 struct regulator *vddo_reg;
64 u8 index;
65 };
66 #define to_clk_si5341_output(_hw) \
67 container_of(_hw, struct clk_si5341_output, hw)
68
69 struct clk_si5341 {
70 struct clk_hw hw;
71 struct regmap *regmap;
72 struct i2c_client *i2c_client;
73 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
74 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
75 struct clk *input_clk[SI5341_NUM_INPUTS];
76 const char *input_clk_name[SI5341_NUM_INPUTS];
77 const u16 *reg_output_offset;
78 const u16 *reg_rdiv_offset;
79 u64 freq_vco; /* 13500–14256 MHz */
80 u8 num_outputs;
81 u8 num_synth;
82 u16 chip_id;
83 };
84 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
85
86 struct clk_si5341_output_config {
87 u8 out_format_drv_bits;
88 u8 out_cm_ampl_bits;
89 u8 vdd_sel_bits;
90 bool synth_master;
91 bool always_on;
92 };
93
94 #define SI5341_PAGE 0x0001
95 #define SI5341_PN_BASE 0x0002
96 #define SI5341_DEVICE_REV 0x0005
97 #define SI5341_STATUS 0x000C
98 #define SI5341_LOS 0x000D
99 #define SI5341_STATUS_STICKY 0x0011
100 #define SI5341_LOS_STICKY 0x0012
101 #define SI5341_SOFT_RST 0x001C
102 #define SI5341_IN_SEL 0x0021
103 #define SI5341_DEVICE_READY 0x00FE
104 #define SI5341_XAXB_CFG 0x090E
105 #define SI5341_IN_EN 0x0949
106 #define SI5341_INX_TO_PFD_EN 0x094A
107
108 /* Status bits */
109 #define SI5341_STATUS_SYSINCAL BIT(0)
110 #define SI5341_STATUS_LOSXAXB BIT(1)
111 #define SI5341_STATUS_LOSREF BIT(2)
112 #define SI5341_STATUS_LOL BIT(3)
113
114 /* Input selection */
115 #define SI5341_IN_SEL_MASK 0x06
116 #define SI5341_IN_SEL_SHIFT 1
117 #define SI5341_IN_SEL_REGCTRL 0x01
118 #define SI5341_INX_TO_PFD_SHIFT 4
119
120 /* XTAL config bits */
121 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
122 #define SI5341_XAXB_CFG_PDNB BIT(1)
123
124 /* Input dividers (48-bit) */
125 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
126 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
127 #define SI5341_PX_UPD 0x0230
128
129 /* PLL configuration */
130 #define SI5341_PLL_M_NUM 0x0235
131 #define SI5341_PLL_M_DEN 0x023B
132
133 /* Output configuration */
134 #define SI5341_OUT_CONFIG(output) \
135 ((output)->data->reg_output_offset[(output)->index])
136 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
137 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
138 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
139 #define SI5341_OUT_R_REG(output) \
140 ((output)->data->reg_rdiv_offset[(output)->index])
141
142 #define SI5341_OUT_MUX_VDD_SEL_MASK 0x38
143
144 /* Synthesize N divider */
145 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
146 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
147 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
148
149 /* Synthesizer output enable, phase bypass, power mode */
150 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
151 #define SI5341_SYNTH_N_PIBYP 0x0A04
152 #define SI5341_SYNTH_N_PDNB 0x0A05
153 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
154
155 #define SI5341_REGISTER_MAX 0xBFF
156
157 /* SI5341_OUT_CONFIG bits */
158 #define SI5341_OUT_CFG_PDN BIT(0)
159 #define SI5341_OUT_CFG_OE BIT(1)
160 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
161
162 /* Static configuration (to be moved to firmware) */
163 struct si5341_reg_default {
164 u16 address;
165 u8 value;
166 };
167
168 static const char * const si5341_input_clock_names[] = {
169 "in0", "in1", "in2", "xtal"
170 };
171
172 /* Output configuration registers 0..9 are not quite logically organized */
173 /* Also for si5345 */
174 static const u16 si5341_reg_output_offset[] = {
175 0x0108,
176 0x010D,
177 0x0112,
178 0x0117,
179 0x011C,
180 0x0121,
181 0x0126,
182 0x012B,
183 0x0130,
184 0x013A,
185 };
186
187 /* for si5340, si5342 and si5344 */
188 static const u16 si5340_reg_output_offset[] = {
189 0x0112,
190 0x0117,
191 0x0126,
192 0x012B,
193 };
194
195 /* The location of the R divider registers */
196 static const u16 si5341_reg_rdiv_offset[] = {
197 0x024A,
198 0x024D,
199 0x0250,
200 0x0253,
201 0x0256,
202 0x0259,
203 0x025C,
204 0x025F,
205 0x0262,
206 0x0268,
207 };
208 static const u16 si5340_reg_rdiv_offset[] = {
209 0x0250,
210 0x0253,
211 0x025C,
212 0x025F,
213 };
214
215 /*
216 * Programming sequence from ClockBuilder, settings to initialize the system
217 * using only the XTAL input, without pre-divider.
218 * This also contains settings that aren't mentioned anywhere in the datasheet.
219 * The "known" settings like synth and output configuration are done later.
220 */
221 static const struct si5341_reg_default si5341_reg_defaults[] = {
222 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
223 { 0x0018, 0xFF }, /* INT mask */
224 { 0x0021, 0x0F }, /* Select XTAL as input */
225 { 0x0022, 0x00 }, /* Not in datasheet */
226 { 0x002B, 0x02 }, /* SPI config */
227 { 0x002C, 0x20 }, /* LOS enable for XTAL */
228 { 0x002D, 0x00 }, /* LOS timing */
229 { 0x002E, 0x00 },
230 { 0x002F, 0x00 },
231 { 0x0030, 0x00 },
232 { 0x0031, 0x00 },
233 { 0x0032, 0x00 },
234 { 0x0033, 0x00 },
235 { 0x0034, 0x00 },
236 { 0x0035, 0x00 },
237 { 0x0036, 0x00 },
238 { 0x0037, 0x00 },
239 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
240 { 0x0039, 0x00 },
241 { 0x003A, 0x00 },
242 { 0x003B, 0x00 },
243 { 0x003C, 0x00 },
244 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
245 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
246 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
247 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
248 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
249 { 0x009E, 0x00 }, /* Not in datasheet */
250 { 0x0102, 0x01 }, /* Enable outputs */
251 { 0x013F, 0x00 }, /* Not in datasheet */
252 { 0x0140, 0x00 }, /* Not in datasheet */
253 { 0x0141, 0x40 }, /* OUT LOS */
254 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
255 { 0x0203, 0x00 },
256 { 0x0204, 0x00 },
257 { 0x0205, 0x00 },
258 { 0x0206, 0x00 }, /* PXAXB (2^x) */
259 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
260 { 0x0209, 0x00 },
261 { 0x020A, 0x00 },
262 { 0x020B, 0x00 },
263 { 0x020C, 0x00 },
264 { 0x020D, 0x00 },
265 { 0x020E, 0x00 },
266 { 0x020F, 0x00 },
267 { 0x0210, 0x00 },
268 { 0x0211, 0x00 },
269 { 0x0212, 0x00 },
270 { 0x0213, 0x00 },
271 { 0x0214, 0x00 },
272 { 0x0215, 0x00 },
273 { 0x0216, 0x00 },
274 { 0x0217, 0x00 },
275 { 0x0218, 0x00 },
276 { 0x0219, 0x00 },
277 { 0x021A, 0x00 },
278 { 0x021B, 0x00 },
279 { 0x021C, 0x00 },
280 { 0x021D, 0x00 },
281 { 0x021E, 0x00 },
282 { 0x021F, 0x00 },
283 { 0x0220, 0x00 },
284 { 0x0221, 0x00 },
285 { 0x0222, 0x00 },
286 { 0x0223, 0x00 },
287 { 0x0224, 0x00 },
288 { 0x0225, 0x00 },
289 { 0x0226, 0x00 },
290 { 0x0227, 0x00 },
291 { 0x0228, 0x00 },
292 { 0x0229, 0x00 },
293 { 0x022A, 0x00 },
294 { 0x022B, 0x00 },
295 { 0x022C, 0x00 },
296 { 0x022D, 0x00 },
297 { 0x022E, 0x00 },
298 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
299 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
300 { 0x026C, 0x00 },
301 { 0x026D, 0x00 },
302 { 0x026E, 0x00 },
303 { 0x026F, 0x00 },
304 { 0x0270, 0x00 },
305 { 0x0271, 0x00 },
306 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
307 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
308 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
309 { 0x033C, 0x00 },
310 { 0x033D, 0x00 },
311 { 0x033E, 0x00 },
312 { 0x033F, 0x00 },
313 { 0x0340, 0x00 },
314 { 0x0341, 0x00 },
315 { 0x0342, 0x00 },
316 { 0x0343, 0x00 },
317 { 0x0344, 0x00 },
318 { 0x0345, 0x00 },
319 { 0x0346, 0x00 },
320 { 0x0347, 0x00 },
321 { 0x0348, 0x00 },
322 { 0x0349, 0x00 },
323 { 0x034A, 0x00 },
324 { 0x034B, 0x00 },
325 { 0x034C, 0x00 },
326 { 0x034D, 0x00 },
327 { 0x034E, 0x00 },
328 { 0x034F, 0x00 },
329 { 0x0350, 0x00 },
330 { 0x0351, 0x00 },
331 { 0x0352, 0x00 },
332 { 0x0353, 0x00 },
333 { 0x0354, 0x00 },
334 { 0x0355, 0x00 },
335 { 0x0356, 0x00 },
336 { 0x0357, 0x00 },
337 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
338 { 0x0359, 0x00 }, /* Nx_DELAY */
339 { 0x035A, 0x00 },
340 { 0x035B, 0x00 },
341 { 0x035C, 0x00 },
342 { 0x035D, 0x00 },
343 { 0x035E, 0x00 },
344 { 0x035F, 0x00 },
345 { 0x0360, 0x00 },
346 { 0x0361, 0x00 },
347 { 0x0362, 0x00 }, /* Nx_DELAY end */
348 { 0x0802, 0x00 }, /* Not in datasheet */
349 { 0x0803, 0x00 }, /* Not in datasheet */
350 { 0x0804, 0x00 }, /* Not in datasheet */
351 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
352 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
353 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
354 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
355 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
356 { 0x0A02, 0x00 }, /* Not in datasheet */
357 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
358 { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
359 { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
360 };
361
362 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
si5341_decode_44_32(struct regmap * regmap,unsigned int reg,u64 * val1,u32 * val2)363 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
364 u64 *val1, u32 *val2)
365 {
366 int err;
367 u8 r[10];
368
369 err = regmap_bulk_read(regmap, reg, r, 10);
370 if (err < 0)
371 return err;
372
373 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
374 (get_unaligned_le32(r));
375 *val2 = get_unaligned_le32(&r[6]);
376
377 return 0;
378 }
379
si5341_encode_44_32(struct regmap * regmap,unsigned int reg,u64 n_num,u32 n_den)380 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
381 u64 n_num, u32 n_den)
382 {
383 u8 r[10];
384
385 /* Shift left as far as possible without overflowing */
386 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
387 n_num <<= 1;
388 n_den <<= 1;
389 }
390
391 /* 44 bits (6 bytes) numerator */
392 put_unaligned_le32(n_num, r);
393 r[4] = (n_num >> 32) & 0xff;
394 r[5] = (n_num >> 40) & 0x0f;
395 /* 32 bits denominator */
396 put_unaligned_le32(n_den, &r[6]);
397
398 /* Program the fraction */
399 return regmap_bulk_write(regmap, reg, r, sizeof(r));
400 }
401
402 /* VCO, we assume it runs at a constant frequency */
si5341_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)403 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
404 unsigned long parent_rate)
405 {
406 struct clk_si5341 *data = to_clk_si5341(hw);
407 int err;
408 u64 res;
409 u64 m_num;
410 u32 m_den;
411 unsigned int shift;
412
413 /* Assume that PDIV is not being used, just read the PLL setting */
414 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
415 &m_num, &m_den);
416 if (err < 0)
417 return 0;
418
419 if (!m_num || !m_den)
420 return 0;
421
422 /*
423 * Though m_num is 64-bit, only the upper bits are actually used. While
424 * calculating m_num and m_den, they are shifted as far as possible to
425 * the left. To avoid 96-bit division here, we just shift them back so
426 * we can do with just 64 bits.
427 */
428 shift = 0;
429 res = m_num;
430 while (res & 0xffff00000000ULL) {
431 ++shift;
432 res >>= 1;
433 }
434 res *= parent_rate;
435 do_div(res, (m_den >> shift));
436
437 /* We cannot return the actual frequency in 32 bit, store it locally */
438 data->freq_vco = res;
439
440 /* Report kHz since the value is out of range */
441 do_div(res, 1000);
442
443 return (unsigned long)res;
444 }
445
si5341_clk_get_selected_input(struct clk_si5341 * data)446 static int si5341_clk_get_selected_input(struct clk_si5341 *data)
447 {
448 int err;
449 u32 val;
450
451 err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
452 if (err < 0)
453 return err;
454
455 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
456 }
457
si5341_clk_get_parent(struct clk_hw * hw)458 static u8 si5341_clk_get_parent(struct clk_hw *hw)
459 {
460 struct clk_si5341 *data = to_clk_si5341(hw);
461 int res = si5341_clk_get_selected_input(data);
462
463 if (res < 0)
464 return 0; /* Apparently we cannot report errors */
465
466 return res;
467 }
468
si5341_clk_reparent(struct clk_si5341 * data,u8 index)469 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
470 {
471 int err;
472 u8 val;
473
474 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
475 /* Enable register-based input selection */
476 val |= SI5341_IN_SEL_REGCTRL;
477
478 err = regmap_update_bits(data->regmap,
479 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
480 if (err < 0)
481 return err;
482
483 if (index < 3) {
484 /* Enable input buffer for selected input */
485 err = regmap_update_bits(data->regmap,
486 SI5341_IN_EN, 0x07, BIT(index));
487 if (err < 0)
488 return err;
489
490 /* Enables the input to phase detector */
491 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
492 0x7 << SI5341_INX_TO_PFD_SHIFT,
493 BIT(index + SI5341_INX_TO_PFD_SHIFT));
494 if (err < 0)
495 return err;
496
497 /* Power down XTAL oscillator and buffer */
498 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
499 SI5341_XAXB_CFG_PDNB, 0);
500 if (err < 0)
501 return err;
502
503 /*
504 * Set the P divider to "1". There's no explanation in the
505 * datasheet of these registers, but the clockbuilder software
506 * programs a "1" when the input is being used.
507 */
508 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
509 if (err < 0)
510 return err;
511
512 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
513 if (err < 0)
514 return err;
515
516 /* Set update PDIV bit */
517 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
518 if (err < 0)
519 return err;
520 } else {
521 /* Disable all input buffers */
522 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
523 if (err < 0)
524 return err;
525
526 /* Disable input to phase detector */
527 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
528 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
529 if (err < 0)
530 return err;
531
532 /* Power up XTAL oscillator and buffer */
533 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
534 SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
535 if (err < 0)
536 return err;
537 }
538
539 return 0;
540 }
541
si5341_clk_set_parent(struct clk_hw * hw,u8 index)542 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
543 {
544 struct clk_si5341 *data = to_clk_si5341(hw);
545
546 return si5341_clk_reparent(data, index);
547 }
548
549 static const struct clk_ops si5341_clk_ops = {
550 .set_parent = si5341_clk_set_parent,
551 .get_parent = si5341_clk_get_parent,
552 .recalc_rate = si5341_clk_recalc_rate,
553 };
554
555 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
556
557 /* The synthesizer is on if all power and enable bits are set */
si5341_synth_clk_is_on(struct clk_hw * hw)558 static int si5341_synth_clk_is_on(struct clk_hw *hw)
559 {
560 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
561 int err;
562 u32 val;
563 u8 index = synth->index;
564
565 err = regmap_read(synth->data->regmap,
566 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
567 if (err < 0)
568 return 0;
569
570 if (!(val & BIT(index)))
571 return 0;
572
573 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
574 if (err < 0)
575 return 0;
576
577 if (!(val & BIT(index)))
578 return 0;
579
580 /* This bit must be 0 for the synthesizer to receive clock input */
581 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
582 if (err < 0)
583 return 0;
584
585 return !(val & BIT(index));
586 }
587
si5341_synth_clk_unprepare(struct clk_hw * hw)588 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
589 {
590 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
591 u8 index = synth->index; /* In range 0..5 */
592 u8 mask = BIT(index);
593
594 /* Disable output */
595 regmap_update_bits(synth->data->regmap,
596 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
597 /* Power down */
598 regmap_update_bits(synth->data->regmap,
599 SI5341_SYNTH_N_PDNB, mask, 0);
600 /* Disable clock input to synth (set to 1 to disable) */
601 regmap_update_bits(synth->data->regmap,
602 SI5341_SYNTH_N_CLK_DIS, mask, mask);
603 }
604
si5341_synth_clk_prepare(struct clk_hw * hw)605 static int si5341_synth_clk_prepare(struct clk_hw *hw)
606 {
607 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
608 int err;
609 u8 index = synth->index;
610 u8 mask = BIT(index);
611
612 /* Power up */
613 err = regmap_update_bits(synth->data->regmap,
614 SI5341_SYNTH_N_PDNB, mask, mask);
615 if (err < 0)
616 return err;
617
618 /* Enable clock input to synth (set bit to 0 to enable) */
619 err = regmap_update_bits(synth->data->regmap,
620 SI5341_SYNTH_N_CLK_DIS, mask, 0);
621 if (err < 0)
622 return err;
623
624 /* Enable output */
625 return regmap_update_bits(synth->data->regmap,
626 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
627 }
628
629 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
si5341_synth_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)630 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
631 unsigned long parent_rate)
632 {
633 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
634 u64 f;
635 u64 n_num;
636 u32 n_den;
637 int err;
638
639 err = si5341_decode_44_32(synth->data->regmap,
640 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
641 if (err < 0)
642 return err;
643 /* Check for bogus/uninitialized settings */
644 if (!n_num || !n_den)
645 return 0;
646
647 /*
648 * n_num and n_den are shifted left as much as possible, so to prevent
649 * overflow in 64-bit math, we shift n_den 4 bits to the right
650 */
651 f = synth->data->freq_vco;
652 f *= n_den >> 4;
653
654 /* Now we need to to 64-bit division: f/n_num */
655 /* And compensate for the 4 bits we dropped */
656 f = div64_u64(f, (n_num >> 4));
657
658 return f;
659 }
660
si5341_synth_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)661 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
662 unsigned long *parent_rate)
663 {
664 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
665 u64 f;
666
667 /* The synthesizer accuracy is such that anything in range will work */
668 f = synth->data->freq_vco;
669 do_div(f, SI5341_SYNTH_N_MAX);
670 if (rate < f)
671 return f;
672
673 f = synth->data->freq_vco;
674 do_div(f, SI5341_SYNTH_N_MIN);
675 if (rate > f)
676 return f;
677
678 return rate;
679 }
680
si5341_synth_program(struct clk_si5341_synth * synth,u64 n_num,u32 n_den,bool is_integer)681 static int si5341_synth_program(struct clk_si5341_synth *synth,
682 u64 n_num, u32 n_den, bool is_integer)
683 {
684 int err;
685 u8 index = synth->index;
686
687 err = si5341_encode_44_32(synth->data->regmap,
688 SI5341_SYNTH_N_NUM(index), n_num, n_den);
689
690 err = regmap_update_bits(synth->data->regmap,
691 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
692 if (err < 0)
693 return err;
694
695 return regmap_write(synth->data->regmap,
696 SI5341_SYNTH_N_UPD(index), 0x01);
697 }
698
699
si5341_synth_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)700 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
701 unsigned long parent_rate)
702 {
703 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
704 u64 n_num;
705 u32 n_den;
706 u32 r;
707 u32 g;
708 bool is_integer;
709
710 n_num = synth->data->freq_vco;
711
712 /* see if there's an integer solution */
713 r = do_div(n_num, rate);
714 is_integer = (r == 0);
715 if (is_integer) {
716 /* Integer divider equal to n_num */
717 n_den = 1;
718 } else {
719 /* Calculate a fractional solution */
720 g = gcd(r, rate);
721 n_den = rate / g;
722 n_num *= n_den;
723 n_num += r / g;
724 }
725
726 dev_dbg(&synth->data->i2c_client->dev,
727 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
728 synth->index, n_num, n_den,
729 is_integer ? "int" : "frac");
730
731 return si5341_synth_program(synth, n_num, n_den, is_integer);
732 }
733
734 static const struct clk_ops si5341_synth_clk_ops = {
735 .is_prepared = si5341_synth_clk_is_on,
736 .prepare = si5341_synth_clk_prepare,
737 .unprepare = si5341_synth_clk_unprepare,
738 .recalc_rate = si5341_synth_clk_recalc_rate,
739 .round_rate = si5341_synth_clk_round_rate,
740 .set_rate = si5341_synth_clk_set_rate,
741 };
742
si5341_output_clk_is_on(struct clk_hw * hw)743 static int si5341_output_clk_is_on(struct clk_hw *hw)
744 {
745 struct clk_si5341_output *output = to_clk_si5341_output(hw);
746 int err;
747 u32 val;
748
749 err = regmap_read(output->data->regmap,
750 SI5341_OUT_CONFIG(output), &val);
751 if (err < 0)
752 return err;
753
754 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
755 return (val & 0x03) == SI5341_OUT_CFG_OE;
756 }
757
758 /* Disables and then powers down the output */
si5341_output_clk_unprepare(struct clk_hw * hw)759 static void si5341_output_clk_unprepare(struct clk_hw *hw)
760 {
761 struct clk_si5341_output *output = to_clk_si5341_output(hw);
762
763 regmap_update_bits(output->data->regmap,
764 SI5341_OUT_CONFIG(output),
765 SI5341_OUT_CFG_OE, 0);
766 regmap_update_bits(output->data->regmap,
767 SI5341_OUT_CONFIG(output),
768 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
769 }
770
771 /* Powers up and then enables the output */
si5341_output_clk_prepare(struct clk_hw * hw)772 static int si5341_output_clk_prepare(struct clk_hw *hw)
773 {
774 struct clk_si5341_output *output = to_clk_si5341_output(hw);
775 int err;
776
777 err = regmap_update_bits(output->data->regmap,
778 SI5341_OUT_CONFIG(output),
779 SI5341_OUT_CFG_PDN, 0);
780 if (err < 0)
781 return err;
782
783 return regmap_update_bits(output->data->regmap,
784 SI5341_OUT_CONFIG(output),
785 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
786 }
787
si5341_output_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)788 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
789 unsigned long parent_rate)
790 {
791 struct clk_si5341_output *output = to_clk_si5341_output(hw);
792 int err;
793 u32 val;
794 u32 r_divider;
795 u8 r[3];
796
797 err = regmap_read(output->data->regmap,
798 SI5341_OUT_CONFIG(output), &val);
799 if (err < 0)
800 return err;
801
802 /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
803 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
804 return parent_rate / 2;
805
806 err = regmap_bulk_read(output->data->regmap,
807 SI5341_OUT_R_REG(output), r, 3);
808 if (err < 0)
809 return err;
810
811 /* Calculate value as 24-bit integer*/
812 r_divider = r[2] << 16 | r[1] << 8 | r[0];
813
814 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
815 if (!r_divider)
816 return 0;
817
818 /* Divider is 2*(Rx_REG+1) */
819 r_divider += 1;
820 r_divider <<= 1;
821
822
823 return parent_rate / r_divider;
824 }
825
si5341_output_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)826 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
827 unsigned long *parent_rate)
828 {
829 unsigned long r;
830
831 if (!rate)
832 return 0;
833
834 r = *parent_rate >> 1;
835
836 /* If rate is an even divisor, no changes to parent required */
837 if (r && !(r % rate))
838 return (long)rate;
839
840 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
841 if (rate > 200000000) {
842 /* minimum r-divider is 2 */
843 r = 2;
844 } else {
845 /* Take a parent frequency near 400 MHz */
846 r = (400000000u / rate) & ~1;
847 }
848 *parent_rate = r * rate;
849 } else {
850 /* We cannot change our parent's rate, report what we can do */
851 r /= rate;
852 rate = *parent_rate / (r << 1);
853 }
854
855 return rate;
856 }
857
si5341_output_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)858 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
859 unsigned long parent_rate)
860 {
861 struct clk_si5341_output *output = to_clk_si5341_output(hw);
862 u32 r_div;
863 int err;
864 u8 r[3];
865
866 if (!rate)
867 return -EINVAL;
868
869 /* Frequency divider is (r_div + 1) * 2 */
870 r_div = (parent_rate / rate) >> 1;
871
872 if (r_div <= 1)
873 r_div = 0;
874 else if (r_div >= BIT(24))
875 r_div = BIT(24) - 1;
876 else
877 --r_div;
878
879 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
880 err = regmap_update_bits(output->data->regmap,
881 SI5341_OUT_CONFIG(output),
882 SI5341_OUT_CFG_RDIV_FORCE2,
883 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
884 if (err < 0)
885 return err;
886
887 /* Always write Rx_REG, because a zero value disables the divider */
888 r[0] = r_div ? (r_div & 0xff) : 1;
889 r[1] = (r_div >> 8) & 0xff;
890 r[2] = (r_div >> 16) & 0xff;
891 err = regmap_bulk_write(output->data->regmap,
892 SI5341_OUT_R_REG(output), r, 3);
893
894 return 0;
895 }
896
si5341_output_reparent(struct clk_si5341_output * output,u8 index)897 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
898 {
899 return regmap_update_bits(output->data->regmap,
900 SI5341_OUT_MUX_SEL(output), 0x07, index);
901 }
902
si5341_output_set_parent(struct clk_hw * hw,u8 index)903 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
904 {
905 struct clk_si5341_output *output = to_clk_si5341_output(hw);
906
907 if (index >= output->data->num_synth)
908 return -EINVAL;
909
910 return si5341_output_reparent(output, index);
911 }
912
si5341_output_get_parent(struct clk_hw * hw)913 static u8 si5341_output_get_parent(struct clk_hw *hw)
914 {
915 struct clk_si5341_output *output = to_clk_si5341_output(hw);
916 u32 val;
917
918 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
919
920 return val & 0x7;
921 }
922
923 static const struct clk_ops si5341_output_clk_ops = {
924 .is_prepared = si5341_output_clk_is_on,
925 .prepare = si5341_output_clk_prepare,
926 .unprepare = si5341_output_clk_unprepare,
927 .recalc_rate = si5341_output_clk_recalc_rate,
928 .round_rate = si5341_output_clk_round_rate,
929 .set_rate = si5341_output_clk_set_rate,
930 .set_parent = si5341_output_set_parent,
931 .get_parent = si5341_output_get_parent,
932 };
933
934 /*
935 * The chip can be bought in a pre-programmed version, or one can program the
936 * NVM in the chip to boot up in a preset mode. This routine tries to determine
937 * if that's the case, or if we need to reset and program everything from
938 * scratch. Returns negative error, or true/false.
939 */
si5341_is_programmed_already(struct clk_si5341 * data)940 static int si5341_is_programmed_already(struct clk_si5341 *data)
941 {
942 int err;
943 u8 r[4];
944
945 /* Read the PLL divider value, it must have a non-zero value */
946 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
947 r, ARRAY_SIZE(r));
948 if (err < 0)
949 return err;
950
951 return !!get_unaligned_le32(r);
952 }
953
954 static struct clk_hw *
of_clk_si5341_get(struct of_phandle_args * clkspec,void * _data)955 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
956 {
957 struct clk_si5341 *data = _data;
958 unsigned int idx = clkspec->args[1];
959 unsigned int group = clkspec->args[0];
960
961 switch (group) {
962 case 0:
963 if (idx >= data->num_outputs) {
964 dev_err(&data->i2c_client->dev,
965 "invalid output index %u\n", idx);
966 return ERR_PTR(-EINVAL);
967 }
968 return &data->clk[idx].hw;
969 case 1:
970 if (idx >= data->num_synth) {
971 dev_err(&data->i2c_client->dev,
972 "invalid synthesizer index %u\n", idx);
973 return ERR_PTR(-EINVAL);
974 }
975 return &data->synth[idx].hw;
976 case 2:
977 if (idx > 0) {
978 dev_err(&data->i2c_client->dev,
979 "invalid PLL index %u\n", idx);
980 return ERR_PTR(-EINVAL);
981 }
982 return &data->hw;
983 default:
984 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
985 return ERR_PTR(-EINVAL);
986 }
987 }
988
si5341_probe_chip_id(struct clk_si5341 * data)989 static int si5341_probe_chip_id(struct clk_si5341 *data)
990 {
991 int err;
992 u8 reg[4];
993 u16 model;
994
995 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
996 ARRAY_SIZE(reg));
997 if (err < 0) {
998 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
999 return err;
1000 }
1001
1002 model = get_unaligned_le16(reg);
1003
1004 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
1005 model, reg[2], reg[3]);
1006
1007 switch (model) {
1008 case 0x5340:
1009 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
1010 data->num_synth = SI5340_NUM_SYNTH;
1011 data->reg_output_offset = si5340_reg_output_offset;
1012 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1013 break;
1014 case 0x5341:
1015 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
1016 data->num_synth = SI5341_NUM_SYNTH;
1017 data->reg_output_offset = si5341_reg_output_offset;
1018 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1019 break;
1020 case 0x5342:
1021 data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
1022 data->num_synth = SI5342_NUM_SYNTH;
1023 data->reg_output_offset = si5340_reg_output_offset;
1024 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1025 break;
1026 case 0x5344:
1027 data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
1028 data->num_synth = SI5344_NUM_SYNTH;
1029 data->reg_output_offset = si5340_reg_output_offset;
1030 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1031 break;
1032 case 0x5345:
1033 data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1034 data->num_synth = SI5345_NUM_SYNTH;
1035 data->reg_output_offset = si5341_reg_output_offset;
1036 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1037 break;
1038 default:
1039 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1040 model);
1041 return -EINVAL;
1042 }
1043
1044 data->chip_id = model;
1045
1046 return 0;
1047 }
1048
1049 /* Read active settings into the regmap cache for later reference */
si5341_read_settings(struct clk_si5341 * data)1050 static int si5341_read_settings(struct clk_si5341 *data)
1051 {
1052 int err;
1053 u8 i;
1054 u8 r[10];
1055
1056 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1057 if (err < 0)
1058 return err;
1059
1060 err = regmap_bulk_read(data->regmap,
1061 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1062 if (err < 0)
1063 return err;
1064
1065 err = regmap_bulk_read(data->regmap,
1066 SI5341_SYNTH_N_CLK_DIS, r, 1);
1067 if (err < 0)
1068 return err;
1069
1070 for (i = 0; i < data->num_synth; ++i) {
1071 err = regmap_bulk_read(data->regmap,
1072 SI5341_SYNTH_N_NUM(i), r, 10);
1073 if (err < 0)
1074 return err;
1075 }
1076
1077 for (i = 0; i < data->num_outputs; ++i) {
1078 err = regmap_bulk_read(data->regmap,
1079 data->reg_output_offset[i], r, 4);
1080 if (err < 0)
1081 return err;
1082
1083 err = regmap_bulk_read(data->regmap,
1084 data->reg_rdiv_offset[i], r, 3);
1085 if (err < 0)
1086 return err;
1087 }
1088
1089 return 0;
1090 }
1091
si5341_write_multiple(struct clk_si5341 * data,const struct si5341_reg_default * values,unsigned int num_values)1092 static int si5341_write_multiple(struct clk_si5341 *data,
1093 const struct si5341_reg_default *values, unsigned int num_values)
1094 {
1095 unsigned int i;
1096 int res;
1097
1098 for (i = 0; i < num_values; ++i) {
1099 res = regmap_write(data->regmap,
1100 values[i].address, values[i].value);
1101 if (res < 0) {
1102 dev_err(&data->i2c_client->dev,
1103 "Failed to write %#x:%#x\n",
1104 values[i].address, values[i].value);
1105 return res;
1106 }
1107 }
1108
1109 return 0;
1110 }
1111
1112 static const struct si5341_reg_default si5341_preamble[] = {
1113 { 0x0B25, 0x00 },
1114 { 0x0502, 0x01 },
1115 { 0x0505, 0x03 },
1116 { 0x0957, 0x17 },
1117 { 0x0B4E, 0x1A },
1118 };
1119
1120 static const struct si5341_reg_default si5345_preamble[] = {
1121 { 0x0B25, 0x00 },
1122 { 0x0540, 0x01 },
1123 };
1124
si5341_send_preamble(struct clk_si5341 * data)1125 static int si5341_send_preamble(struct clk_si5341 *data)
1126 {
1127 int res;
1128 u32 revision;
1129
1130 /* For revision 2 and up, the values are slightly different */
1131 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1132 if (res < 0)
1133 return res;
1134
1135 /* Write "preamble" as specified by datasheet */
1136 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1137 if (res < 0)
1138 return res;
1139
1140 /* The si5342..si5345 require a different preamble */
1141 if (data->chip_id > 0x5341)
1142 res = si5341_write_multiple(data,
1143 si5345_preamble, ARRAY_SIZE(si5345_preamble));
1144 else
1145 res = si5341_write_multiple(data,
1146 si5341_preamble, ARRAY_SIZE(si5341_preamble));
1147 if (res < 0)
1148 return res;
1149
1150 /* Datasheet specifies a 300ms wait after sending the preamble */
1151 msleep(300);
1152
1153 return 0;
1154 }
1155
1156 /* Perform a soft reset and write post-amble */
si5341_finalize_defaults(struct clk_si5341 * data)1157 static int si5341_finalize_defaults(struct clk_si5341 *data)
1158 {
1159 int res;
1160 u32 revision;
1161
1162 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1163 if (res < 0)
1164 return res;
1165
1166 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1167
1168 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1169 if (res < 0)
1170 return res;
1171
1172 /* The si5342..si5345 have an additional post-amble */
1173 if (data->chip_id > 0x5341) {
1174 res = regmap_write(data->regmap, 0x540, 0x0);
1175 if (res < 0)
1176 return res;
1177 }
1178
1179 /* Datasheet does not explain these nameless registers */
1180 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1181 if (res < 0)
1182 return res;
1183 res = regmap_write(data->regmap, 0x0B25, 0x02);
1184 if (res < 0)
1185 return res;
1186
1187 return 0;
1188 }
1189
1190
1191 static const struct regmap_range si5341_regmap_volatile_range[] = {
1192 regmap_reg_range(0x000C, 0x0012), /* Status */
1193 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1194 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1195 /* Update bits for P divider and synth config */
1196 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1197 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1198 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1199 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1200 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1201 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1202 };
1203
1204 static const struct regmap_access_table si5341_regmap_volatile = {
1205 .yes_ranges = si5341_regmap_volatile_range,
1206 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1207 };
1208
1209 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1210 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1211 {
1212 .range_min = 0,
1213 .range_max = SI5341_REGISTER_MAX,
1214 .selector_reg = SI5341_PAGE,
1215 .selector_mask = 0xff,
1216 .selector_shift = 0,
1217 .window_start = 0,
1218 .window_len = 256,
1219 },
1220 };
1221
si5341_wait_device_ready(struct i2c_client * client)1222 static int si5341_wait_device_ready(struct i2c_client *client)
1223 {
1224 int count;
1225
1226 /* Datasheet warns: Any attempt to read or write any register other
1227 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1228 * NVM programming and may corrupt the register contents, as they are
1229 * read from NVM. Note that this includes accesses to the PAGE register.
1230 * Also: DEVICE_READY is available on every register page, so no page
1231 * change is needed to read it.
1232 * Do this outside regmap to avoid automatic PAGE register access.
1233 * May take up to 300ms to complete.
1234 */
1235 for (count = 0; count < 15; ++count) {
1236 s32 result = i2c_smbus_read_byte_data(client,
1237 SI5341_DEVICE_READY);
1238 if (result < 0)
1239 return result;
1240 if (result == 0x0F)
1241 return 0;
1242 msleep(20);
1243 }
1244 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1245 return -EIO;
1246 }
1247
1248 static const struct regmap_config si5341_regmap_config = {
1249 .reg_bits = 8,
1250 .val_bits = 8,
1251 .cache_type = REGCACHE_RBTREE,
1252 .ranges = si5341_regmap_ranges,
1253 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1254 .max_register = SI5341_REGISTER_MAX,
1255 .volatile_table = &si5341_regmap_volatile,
1256 };
1257
si5341_dt_parse_dt(struct clk_si5341 * data,struct clk_si5341_output_config * config)1258 static int si5341_dt_parse_dt(struct clk_si5341 *data,
1259 struct clk_si5341_output_config *config)
1260 {
1261 struct device_node *child;
1262 struct device_node *np = data->i2c_client->dev.of_node;
1263 u32 num;
1264 u32 val;
1265
1266 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1267 SI5341_MAX_NUM_OUTPUTS);
1268
1269 for_each_child_of_node(np, child) {
1270 if (of_property_read_u32(child, "reg", &num)) {
1271 dev_err(&data->i2c_client->dev, "missing reg property of %s\n",
1272 child->name);
1273 goto put_child;
1274 }
1275
1276 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1277 dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num);
1278 goto put_child;
1279 }
1280
1281 if (!of_property_read_u32(child, "silabs,format", &val)) {
1282 /* Set cm and ampl conservatively to 3v3 settings */
1283 switch (val) {
1284 case 1: /* normal differential */
1285 config[num].out_cm_ampl_bits = 0x33;
1286 break;
1287 case 2: /* low-power differential */
1288 config[num].out_cm_ampl_bits = 0x13;
1289 break;
1290 case 4: /* LVCMOS */
1291 config[num].out_cm_ampl_bits = 0x33;
1292 /* Set SI recommended impedance for LVCMOS */
1293 config[num].out_format_drv_bits |= 0xc0;
1294 break;
1295 default:
1296 dev_err(&data->i2c_client->dev,
1297 "invalid silabs,format %u for %u\n",
1298 val, num);
1299 goto put_child;
1300 }
1301 config[num].out_format_drv_bits &= ~0x07;
1302 config[num].out_format_drv_bits |= val & 0x07;
1303 /* Always enable the SYNC feature */
1304 config[num].out_format_drv_bits |= 0x08;
1305 }
1306
1307 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1308 if (val > 0xf) {
1309 dev_err(&data->i2c_client->dev,
1310 "invalid silabs,common-mode %u\n",
1311 val);
1312 goto put_child;
1313 }
1314 config[num].out_cm_ampl_bits &= 0xf0;
1315 config[num].out_cm_ampl_bits |= val & 0x0f;
1316 }
1317
1318 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1319 if (val > 0xf) {
1320 dev_err(&data->i2c_client->dev,
1321 "invalid silabs,amplitude %u\n",
1322 val);
1323 goto put_child;
1324 }
1325 config[num].out_cm_ampl_bits &= 0x0f;
1326 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1327 }
1328
1329 if (of_property_read_bool(child, "silabs,disable-high"))
1330 config[num].out_format_drv_bits |= 0x10;
1331
1332 config[num].synth_master =
1333 of_property_read_bool(child, "silabs,synth-master");
1334
1335 config[num].always_on =
1336 of_property_read_bool(child, "always-on");
1337
1338 config[num].vdd_sel_bits = 0x08;
1339 if (data->clk[num].vddo_reg) {
1340 int vdd = regulator_get_voltage(data->clk[num].vddo_reg);
1341
1342 switch (vdd) {
1343 case 3300000:
1344 config[num].vdd_sel_bits |= 0 << 4;
1345 break;
1346 case 1800000:
1347 config[num].vdd_sel_bits |= 1 << 4;
1348 break;
1349 case 2500000:
1350 config[num].vdd_sel_bits |= 2 << 4;
1351 break;
1352 default:
1353 dev_err(&data->i2c_client->dev,
1354 "unsupported vddo voltage %d for %s\n",
1355 vdd, child->name);
1356 goto put_child;
1357 }
1358 } else {
1359 /* chip seems to default to 2.5V when not set */
1360 dev_warn(&data->i2c_client->dev,
1361 "no regulator set, defaulting vdd_sel to 2.5V for %s\n",
1362 child->name);
1363 config[num].vdd_sel_bits |= 2 << 4;
1364 }
1365 }
1366
1367 return 0;
1368
1369 put_child:
1370 of_node_put(child);
1371 return -EINVAL;
1372 }
1373
1374 /*
1375 * If not pre-configured, calculate and set the PLL configuration manually.
1376 * For low-jitter performance, the PLL should be set such that the synthesizers
1377 * only need integer division.
1378 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1379 * the chip to generate any frequency on its outputs, but jitter performance
1380 * may be sub-optimal.
1381 */
si5341_initialize_pll(struct clk_si5341 * data)1382 static int si5341_initialize_pll(struct clk_si5341 *data)
1383 {
1384 struct device_node *np = data->i2c_client->dev.of_node;
1385 u32 m_num = 0;
1386 u32 m_den = 0;
1387 int sel;
1388
1389 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1390 dev_err(&data->i2c_client->dev,
1391 "PLL configuration requires silabs,pll-m-num\n");
1392 }
1393 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1394 dev_err(&data->i2c_client->dev,
1395 "PLL configuration requires silabs,pll-m-den\n");
1396 }
1397
1398 if (!m_num || !m_den) {
1399 dev_err(&data->i2c_client->dev,
1400 "PLL configuration invalid, assume 14GHz\n");
1401 sel = si5341_clk_get_selected_input(data);
1402 if (sel < 0)
1403 return sel;
1404
1405 m_den = clk_get_rate(data->input_clk[sel]) / 10;
1406 m_num = 1400000000;
1407 }
1408
1409 return si5341_encode_44_32(data->regmap,
1410 SI5341_PLL_M_NUM, m_num, m_den);
1411 }
1412
si5341_clk_select_active_input(struct clk_si5341 * data)1413 static int si5341_clk_select_active_input(struct clk_si5341 *data)
1414 {
1415 int res;
1416 int err;
1417 int i;
1418
1419 res = si5341_clk_get_selected_input(data);
1420 if (res < 0)
1421 return res;
1422
1423 /* If the current register setting is invalid, pick the first input */
1424 if (!data->input_clk[res]) {
1425 dev_dbg(&data->i2c_client->dev,
1426 "Input %d not connected, rerouting\n", res);
1427 res = -ENODEV;
1428 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1429 if (data->input_clk[i]) {
1430 res = i;
1431 break;
1432 }
1433 }
1434 if (res < 0) {
1435 dev_err(&data->i2c_client->dev,
1436 "No clock input available\n");
1437 return res;
1438 }
1439 }
1440
1441 /* Make sure the selected clock is also enabled and routed */
1442 err = si5341_clk_reparent(data, res);
1443 if (err < 0)
1444 return err;
1445
1446 err = clk_prepare_enable(data->input_clk[res]);
1447 if (err < 0)
1448 return err;
1449
1450 return res;
1451 }
1452
input_present_show(struct device * dev,struct device_attribute * attr,char * buf)1453 static ssize_t input_present_show(struct device *dev,
1454 struct device_attribute *attr,
1455 char *buf)
1456 {
1457 struct clk_si5341 *data = dev_get_drvdata(dev);
1458 u32 status;
1459 int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1460
1461 if (res < 0)
1462 return res;
1463 res = !(status & SI5341_STATUS_LOSREF);
1464 return snprintf(buf, PAGE_SIZE, "%d\n", res);
1465 }
1466 static DEVICE_ATTR_RO(input_present);
1467
input_present_sticky_show(struct device * dev,struct device_attribute * attr,char * buf)1468 static ssize_t input_present_sticky_show(struct device *dev,
1469 struct device_attribute *attr,
1470 char *buf)
1471 {
1472 struct clk_si5341 *data = dev_get_drvdata(dev);
1473 u32 status;
1474 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1475
1476 if (res < 0)
1477 return res;
1478 res = !(status & SI5341_STATUS_LOSREF);
1479 return snprintf(buf, PAGE_SIZE, "%d\n", res);
1480 }
1481 static DEVICE_ATTR_RO(input_present_sticky);
1482
pll_locked_show(struct device * dev,struct device_attribute * attr,char * buf)1483 static ssize_t pll_locked_show(struct device *dev,
1484 struct device_attribute *attr,
1485 char *buf)
1486 {
1487 struct clk_si5341 *data = dev_get_drvdata(dev);
1488 u32 status;
1489 int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1490
1491 if (res < 0)
1492 return res;
1493 res = !(status & SI5341_STATUS_LOL);
1494 return snprintf(buf, PAGE_SIZE, "%d\n", res);
1495 }
1496 static DEVICE_ATTR_RO(pll_locked);
1497
pll_locked_sticky_show(struct device * dev,struct device_attribute * attr,char * buf)1498 static ssize_t pll_locked_sticky_show(struct device *dev,
1499 struct device_attribute *attr,
1500 char *buf)
1501 {
1502 struct clk_si5341 *data = dev_get_drvdata(dev);
1503 u32 status;
1504 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1505
1506 if (res < 0)
1507 return res;
1508 res = !(status & SI5341_STATUS_LOL);
1509 return snprintf(buf, PAGE_SIZE, "%d\n", res);
1510 }
1511 static DEVICE_ATTR_RO(pll_locked_sticky);
1512
clear_sticky_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1513 static ssize_t clear_sticky_store(struct device *dev,
1514 struct device_attribute *attr,
1515 const char *buf, size_t count)
1516 {
1517 struct clk_si5341 *data = dev_get_drvdata(dev);
1518 long val;
1519
1520 if (kstrtol(buf, 10, &val))
1521 return -EINVAL;
1522 if (val) {
1523 int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1524
1525 if (res < 0)
1526 return res;
1527 }
1528 return count;
1529 }
1530 static DEVICE_ATTR_WO(clear_sticky);
1531
1532 static const struct attribute *si5341_attributes[] = {
1533 &dev_attr_input_present.attr,
1534 &dev_attr_input_present_sticky.attr,
1535 &dev_attr_pll_locked.attr,
1536 &dev_attr_pll_locked_sticky.attr,
1537 &dev_attr_clear_sticky.attr,
1538 NULL
1539 };
1540
si5341_probe(struct i2c_client * client,const struct i2c_device_id * id)1541 static int si5341_probe(struct i2c_client *client,
1542 const struct i2c_device_id *id)
1543 {
1544 struct clk_si5341 *data;
1545 struct clk_init_data init;
1546 struct clk *input;
1547 const char *root_clock_name;
1548 const char *synth_clock_names[SI5341_NUM_SYNTH] = { NULL };
1549 int err;
1550 unsigned int i;
1551 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1552 bool initialization_required;
1553 u32 status;
1554
1555 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1556 if (!data)
1557 return -ENOMEM;
1558
1559 data->i2c_client = client;
1560
1561 /* Must be done before otherwise touching hardware */
1562 err = si5341_wait_device_ready(client);
1563 if (err)
1564 return err;
1565
1566 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1567 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1568 if (IS_ERR(input)) {
1569 if (PTR_ERR(input) == -EPROBE_DEFER)
1570 return -EPROBE_DEFER;
1571 data->input_clk_name[i] = si5341_input_clock_names[i];
1572 } else {
1573 data->input_clk[i] = input;
1574 data->input_clk_name[i] = __clk_get_name(input);
1575 }
1576 }
1577
1578 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1579 char reg_name[10];
1580
1581 snprintf(reg_name, sizeof(reg_name), "vddo%d", i);
1582 data->clk[i].vddo_reg = devm_regulator_get_optional(
1583 &client->dev, reg_name);
1584 if (IS_ERR(data->clk[i].vddo_reg)) {
1585 err = PTR_ERR(data->clk[i].vddo_reg);
1586 data->clk[i].vddo_reg = NULL;
1587 if (err == -ENODEV)
1588 continue;
1589 goto cleanup;
1590 } else {
1591 err = regulator_enable(data->clk[i].vddo_reg);
1592 if (err) {
1593 dev_err(&client->dev,
1594 "failed to enable %s regulator: %d\n",
1595 reg_name, err);
1596 data->clk[i].vddo_reg = NULL;
1597 goto cleanup;
1598 }
1599 }
1600 }
1601
1602 err = si5341_dt_parse_dt(data, config);
1603 if (err)
1604 goto cleanup;
1605
1606 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1607 &init.name))
1608 init.name = client->dev.of_node->name;
1609 root_clock_name = init.name;
1610
1611 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1612 if (IS_ERR(data->regmap)) {
1613 err = PTR_ERR(data->regmap);
1614 goto cleanup;
1615 }
1616
1617 i2c_set_clientdata(client, data);
1618
1619 err = si5341_probe_chip_id(data);
1620 if (err < 0)
1621 goto cleanup;
1622
1623 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1624 initialization_required = true;
1625 } else {
1626 err = si5341_is_programmed_already(data);
1627 if (err < 0)
1628 goto cleanup;
1629
1630 initialization_required = !err;
1631 }
1632
1633 if (initialization_required) {
1634 /* Populate the regmap cache in preparation for "cache only" */
1635 err = si5341_read_settings(data);
1636 if (err < 0)
1637 goto cleanup;
1638
1639 err = si5341_send_preamble(data);
1640 if (err < 0)
1641 goto cleanup;
1642
1643 /*
1644 * We intend to send all 'final' register values in a single
1645 * transaction. So cache all register writes until we're done
1646 * configuring.
1647 */
1648 regcache_cache_only(data->regmap, true);
1649
1650 /* Write the configuration pairs from the firmware blob */
1651 err = si5341_write_multiple(data, si5341_reg_defaults,
1652 ARRAY_SIZE(si5341_reg_defaults));
1653 if (err < 0)
1654 goto cleanup;
1655 }
1656
1657 /* Input must be up and running at this point */
1658 err = si5341_clk_select_active_input(data);
1659 if (err < 0)
1660 goto cleanup;
1661
1662 if (initialization_required) {
1663 /* PLL configuration is required */
1664 err = si5341_initialize_pll(data);
1665 if (err < 0)
1666 goto cleanup;
1667 }
1668
1669 /* Register the PLL */
1670 init.parent_names = data->input_clk_name;
1671 init.num_parents = SI5341_NUM_INPUTS;
1672 init.ops = &si5341_clk_ops;
1673 init.flags = 0;
1674 data->hw.init = &init;
1675
1676 err = devm_clk_hw_register(&client->dev, &data->hw);
1677 if (err) {
1678 dev_err(&client->dev, "clock registration failed\n");
1679 goto cleanup;
1680 }
1681
1682 init.num_parents = 1;
1683 init.parent_names = &root_clock_name;
1684 init.ops = &si5341_synth_clk_ops;
1685 for (i = 0; i < data->num_synth; ++i) {
1686 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1687 "%s.N%u", client->dev.of_node->name, i);
1688 if (!synth_clock_names[i]) {
1689 err = -ENOMEM;
1690 goto free_clk_names;
1691 }
1692 init.name = synth_clock_names[i];
1693 data->synth[i].index = i;
1694 data->synth[i].data = data;
1695 data->synth[i].hw.init = &init;
1696 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1697 if (err) {
1698 dev_err(&client->dev,
1699 "synth N%u registration failed\n", i);
1700 goto free_clk_names;
1701 }
1702 }
1703
1704 init.num_parents = data->num_synth;
1705 init.parent_names = synth_clock_names;
1706 init.ops = &si5341_output_clk_ops;
1707 for (i = 0; i < data->num_outputs; ++i) {
1708 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1709 client->dev.of_node->name, i);
1710 if (!init.name) {
1711 err = -ENOMEM;
1712 goto free_clk_names;
1713 }
1714 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1715 data->clk[i].index = i;
1716 data->clk[i].data = data;
1717 data->clk[i].hw.init = &init;
1718 if (config[i].out_format_drv_bits & 0x07) {
1719 regmap_write(data->regmap,
1720 SI5341_OUT_FORMAT(&data->clk[i]),
1721 config[i].out_format_drv_bits);
1722 regmap_write(data->regmap,
1723 SI5341_OUT_CM(&data->clk[i]),
1724 config[i].out_cm_ampl_bits);
1725 regmap_update_bits(data->regmap,
1726 SI5341_OUT_MUX_SEL(&data->clk[i]),
1727 SI5341_OUT_MUX_VDD_SEL_MASK,
1728 config[i].vdd_sel_bits);
1729 }
1730 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1731 kfree(init.name); /* clock framework made a copy of the name */
1732 if (err) {
1733 dev_err(&client->dev,
1734 "output %u registration failed\n", i);
1735 goto free_clk_names;
1736 }
1737 if (config[i].always_on)
1738 clk_prepare(data->clk[i].hw.clk);
1739 }
1740
1741 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get,
1742 data);
1743 if (err) {
1744 dev_err(&client->dev, "unable to add clk provider\n");
1745 goto free_clk_names;
1746 }
1747
1748 if (initialization_required) {
1749 /* Synchronize */
1750 regcache_cache_only(data->regmap, false);
1751 err = regcache_sync(data->regmap);
1752 if (err < 0)
1753 goto free_clk_names;
1754
1755 err = si5341_finalize_defaults(data);
1756 if (err < 0)
1757 goto free_clk_names;
1758 }
1759
1760 /* wait for device to report input clock present and PLL lock */
1761 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
1762 !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
1763 10000, 250000);
1764 if (err) {
1765 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
1766 goto free_clk_names;
1767 }
1768
1769 /* clear sticky alarm bits from initialization */
1770 err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1771 if (err) {
1772 dev_err(&client->dev, "unable to clear sticky status\n");
1773 goto free_clk_names;
1774 }
1775
1776 err = sysfs_create_files(&client->dev.kobj, si5341_attributes);
1777 if (err)
1778 dev_err(&client->dev, "unable to create sysfs files\n");
1779
1780 free_clk_names:
1781 /* Free the names, clk framework makes copies */
1782 for (i = 0; i < data->num_synth; ++i)
1783 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1784
1785 cleanup:
1786 if (err) {
1787 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1788 if (data->clk[i].vddo_reg)
1789 regulator_disable(data->clk[i].vddo_reg);
1790 }
1791 }
1792 return err;
1793 }
1794
si5341_remove(struct i2c_client * client)1795 static int si5341_remove(struct i2c_client *client)
1796 {
1797 struct clk_si5341 *data = i2c_get_clientdata(client);
1798 int i;
1799
1800 sysfs_remove_files(&client->dev.kobj, si5341_attributes);
1801
1802 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1803 if (data->clk[i].vddo_reg)
1804 regulator_disable(data->clk[i].vddo_reg);
1805 }
1806
1807 return 0;
1808 }
1809
1810 static const struct i2c_device_id si5341_id[] = {
1811 { "si5340", 0 },
1812 { "si5341", 1 },
1813 { "si5342", 2 },
1814 { "si5344", 4 },
1815 { "si5345", 5 },
1816 { }
1817 };
1818 MODULE_DEVICE_TABLE(i2c, si5341_id);
1819
1820 static const struct of_device_id clk_si5341_of_match[] = {
1821 { .compatible = "silabs,si5340" },
1822 { .compatible = "silabs,si5341" },
1823 { .compatible = "silabs,si5342" },
1824 { .compatible = "silabs,si5344" },
1825 { .compatible = "silabs,si5345" },
1826 { }
1827 };
1828 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1829
1830 static struct i2c_driver si5341_driver = {
1831 .driver = {
1832 .name = "si5341",
1833 .of_match_table = clk_si5341_of_match,
1834 },
1835 .probe = si5341_probe,
1836 .remove = si5341_remove,
1837 .id_table = si5341_id,
1838 };
1839 module_i2c_driver(si5341_driver);
1840
1841 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1842 MODULE_DESCRIPTION("Si5341 driver");
1843 MODULE_LICENSE("GPL");
1844