1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
68 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
69 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
70 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
71 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
72 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
73 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
74 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
75 *
76 * Features supported by this driver:
77 * Software PEC no
78 * Hardware PEC yes
79 * Block buffer yes
80 * Block process call transaction yes
81 * I2C block read transaction yes (doesn't use the block buffer)
82 * Slave mode no
83 * SMBus Host Notify yes
84 * Interrupt processing yes
85 *
86 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
87 */
88
89 #include <linux/interrupt.h>
90 #include <linux/module.h>
91 #include <linux/pci.h>
92 #include <linux/kernel.h>
93 #include <linux/stddef.h>
94 #include <linux/delay.h>
95 #include <linux/ioport.h>
96 #include <linux/init.h>
97 #include <linux/i2c.h>
98 #include <linux/i2c-smbus.h>
99 #include <linux/acpi.h>
100 #include <linux/io.h>
101 #include <linux/dmi.h>
102 #include <linux/slab.h>
103 #include <linux/string.h>
104 #include <linux/wait.h>
105 #include <linux/err.h>
106 #include <linux/platform_device.h>
107 #include <linux/platform_data/itco_wdt.h>
108 #include <linux/pm_runtime.h>
109
110 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
111 #include <linux/gpio/machine.h>
112 #include <linux/platform_data/i2c-mux-gpio.h>
113 #endif
114
115 /* I801 SMBus address offsets */
116 #define SMBHSTSTS(p) (0 + (p)->smba)
117 #define SMBHSTCNT(p) (2 + (p)->smba)
118 #define SMBHSTCMD(p) (3 + (p)->smba)
119 #define SMBHSTADD(p) (4 + (p)->smba)
120 #define SMBHSTDAT0(p) (5 + (p)->smba)
121 #define SMBHSTDAT1(p) (6 + (p)->smba)
122 #define SMBBLKDAT(p) (7 + (p)->smba)
123 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
124 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
125 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
126 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
127 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
128 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
129
130 /* PCI Address Constants */
131 #define SMBBAR 4
132 #define SMBPCICTL 0x004
133 #define SMBPCISTS 0x006
134 #define SMBHSTCFG 0x040
135 #define TCOBASE 0x050
136 #define TCOCTL 0x054
137
138 #define SBREG_BAR 0x10
139 #define SBREG_SMBCTRL 0xc6000c
140 #define SBREG_SMBCTRL_DNV 0xcf000c
141
142 /* Host status bits for SMBPCISTS */
143 #define SMBPCISTS_INTS BIT(3)
144
145 /* Control bits for SMBPCICTL */
146 #define SMBPCICTL_INTDIS BIT(10)
147
148 /* Host configuration bits for SMBHSTCFG */
149 #define SMBHSTCFG_HST_EN BIT(0)
150 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
151 #define SMBHSTCFG_I2C_EN BIT(2)
152 #define SMBHSTCFG_SPD_WD BIT(4)
153
154 /* TCO configuration bits for TCOCTL */
155 #define TCOCTL_EN BIT(8)
156
157 /* Auxiliary status register bits, ICH4+ only */
158 #define SMBAUXSTS_CRCE BIT(0)
159 #define SMBAUXSTS_STCO BIT(1)
160
161 /* Auxiliary control register bits, ICH4+ only */
162 #define SMBAUXCTL_CRC BIT(0)
163 #define SMBAUXCTL_E32B BIT(1)
164
165 /* Other settings */
166 #define MAX_RETRIES 400
167
168 /* I801 command constants */
169 #define I801_QUICK 0x00
170 #define I801_BYTE 0x04
171 #define I801_BYTE_DATA 0x08
172 #define I801_WORD_DATA 0x0C
173 #define I801_PROC_CALL 0x10 /* unimplemented */
174 #define I801_BLOCK_DATA 0x14
175 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
176 #define I801_BLOCK_PROC_CALL 0x1C
177
178 /* I801 Host Control register bits */
179 #define SMBHSTCNT_INTREN BIT(0)
180 #define SMBHSTCNT_KILL BIT(1)
181 #define SMBHSTCNT_LAST_BYTE BIT(5)
182 #define SMBHSTCNT_START BIT(6)
183 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
184
185 /* I801 Hosts Status register bits */
186 #define SMBHSTSTS_BYTE_DONE BIT(7)
187 #define SMBHSTSTS_INUSE_STS BIT(6)
188 #define SMBHSTSTS_SMBALERT_STS BIT(5)
189 #define SMBHSTSTS_FAILED BIT(4)
190 #define SMBHSTSTS_BUS_ERR BIT(3)
191 #define SMBHSTSTS_DEV_ERR BIT(2)
192 #define SMBHSTSTS_INTR BIT(1)
193 #define SMBHSTSTS_HOST_BUSY BIT(0)
194
195 /* Host Notify Status register bits */
196 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
197
198 /* Host Notify Command register bits */
199 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
200
201 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
202 SMBHSTSTS_DEV_ERR)
203
204 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
205 STATUS_ERROR_FLAGS)
206
207 /* Older devices have their ID defined in <linux/pci_ids.h> */
208 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
209 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
210 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
211 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
212 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
213 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
214 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
216 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
220 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
221 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
222 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
223 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
224 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
225 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
226 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
227 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
228 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
229 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
230 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
231 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
232 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
233 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
234 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
235 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
237 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
238 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
239 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
240 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
241 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
242 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
243 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
244 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
245 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
246 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
247 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
248 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
249 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
250
251 struct i801_mux_config {
252 char *gpio_chip;
253 unsigned values[3];
254 int n_values;
255 unsigned classes[3];
256 unsigned gpios[2]; /* Relative to gpio_chip->base */
257 int n_gpios;
258 };
259
260 struct i801_priv {
261 struct i2c_adapter adapter;
262 unsigned long smba;
263 unsigned char original_hstcfg;
264 unsigned char original_slvcmd;
265 struct pci_dev *pci_dev;
266 unsigned int features;
267
268 /* isr processing */
269 wait_queue_head_t waitq;
270 u8 status;
271
272 /* Command state used by isr for byte-by-byte block transactions */
273 u8 cmd;
274 bool is_read;
275 int count;
276 int len;
277 u8 *data;
278
279 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
280 const struct i801_mux_config *mux_drvdata;
281 struct platform_device *mux_pdev;
282 struct gpiod_lookup_table *lookup;
283 #endif
284 struct platform_device *tco_pdev;
285
286 /*
287 * If set to true the host controller registers are reserved for
288 * ACPI AML use. Protected by acpi_lock.
289 */
290 bool acpi_reserved;
291 struct mutex acpi_lock;
292 };
293
294 #define FEATURE_SMBUS_PEC BIT(0)
295 #define FEATURE_BLOCK_BUFFER BIT(1)
296 #define FEATURE_BLOCK_PROC BIT(2)
297 #define FEATURE_I2C_BLOCK_READ BIT(3)
298 #define FEATURE_IRQ BIT(4)
299 #define FEATURE_HOST_NOTIFY BIT(5)
300 /* Not really a feature, but it's convenient to handle it as such */
301 #define FEATURE_IDF BIT(15)
302 #define FEATURE_TCO_SPT BIT(16)
303 #define FEATURE_TCO_CNL BIT(17)
304
305 static const char *i801_feature_names[] = {
306 "SMBus PEC",
307 "Block buffer",
308 "Block process call",
309 "I2C block read",
310 "Interrupt",
311 "SMBus Host Notify",
312 };
313
314 static unsigned int disable_features;
315 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
316 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
317 "\t\t 0x01 disable SMBus PEC\n"
318 "\t\t 0x02 disable the block buffer\n"
319 "\t\t 0x08 disable the I2C block read functionality\n"
320 "\t\t 0x10 don't use interrupts\n"
321 "\t\t 0x20 disable SMBus Host Notify ");
322
323 /* Make sure the SMBus host is ready to start transmitting.
324 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)325 static int i801_check_pre(struct i801_priv *priv)
326 {
327 int status;
328
329 status = inb_p(SMBHSTSTS(priv));
330 if (status & SMBHSTSTS_HOST_BUSY) {
331 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
332 return -EBUSY;
333 }
334
335 status &= STATUS_FLAGS;
336 if (status) {
337 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
338 status);
339 outb_p(status, SMBHSTSTS(priv));
340 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
341 if (status) {
342 dev_err(&priv->pci_dev->dev,
343 "Failed clearing status flags (%02x)\n",
344 status);
345 return -EBUSY;
346 }
347 }
348
349 /*
350 * Clear CRC status if needed.
351 * During normal operation, i801_check_post() takes care
352 * of it after every operation. We do it here only in case
353 * the hardware was already in this state when the driver
354 * started.
355 */
356 if (priv->features & FEATURE_SMBUS_PEC) {
357 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
358 if (status) {
359 dev_dbg(&priv->pci_dev->dev,
360 "Clearing aux status flags (%02x)\n", status);
361 outb_p(status, SMBAUXSTS(priv));
362 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
363 if (status) {
364 dev_err(&priv->pci_dev->dev,
365 "Failed clearing aux status flags (%02x)\n",
366 status);
367 return -EBUSY;
368 }
369 }
370 }
371
372 return 0;
373 }
374
375 /*
376 * Convert the status register to an error code, and clear it.
377 * Note that status only contains the bits we want to clear, not the
378 * actual register value.
379 */
i801_check_post(struct i801_priv * priv,int status)380 static int i801_check_post(struct i801_priv *priv, int status)
381 {
382 int result = 0;
383
384 /*
385 * If the SMBus is still busy, we give up
386 * Note: This timeout condition only happens when using polling
387 * transactions. For interrupt operation, NAK/timeout is indicated by
388 * DEV_ERR.
389 */
390 if (unlikely(status < 0)) {
391 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
392 /* try to stop the current command */
393 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
394 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
395 usleep_range(1000, 2000);
396 outb_p(0, SMBHSTCNT(priv));
397
398 /* Check if it worked */
399 status = inb_p(SMBHSTSTS(priv));
400 if ((status & SMBHSTSTS_HOST_BUSY) ||
401 !(status & SMBHSTSTS_FAILED))
402 dev_err(&priv->pci_dev->dev,
403 "Failed terminating the transaction\n");
404 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
405 return -ETIMEDOUT;
406 }
407
408 if (status & SMBHSTSTS_FAILED) {
409 result = -EIO;
410 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
411 }
412 if (status & SMBHSTSTS_DEV_ERR) {
413 /*
414 * This may be a PEC error, check and clear it.
415 *
416 * AUXSTS is handled differently from HSTSTS.
417 * For HSTSTS, i801_isr() or i801_wait_intr()
418 * has already cleared the error bits in hardware,
419 * and we are passed a copy of the original value
420 * in "status".
421 * For AUXSTS, the hardware register is left
422 * for us to handle here.
423 * This is asymmetric, slightly iffy, but safe,
424 * since all this code is serialized and the CRCE
425 * bit is harmless as long as it's cleared before
426 * the next operation.
427 */
428 if ((priv->features & FEATURE_SMBUS_PEC) &&
429 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
430 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
431 result = -EBADMSG;
432 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
433 } else {
434 result = -ENXIO;
435 dev_dbg(&priv->pci_dev->dev, "No response\n");
436 }
437 }
438 if (status & SMBHSTSTS_BUS_ERR) {
439 result = -EAGAIN;
440 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
441 }
442
443 /* Clear status flags except BYTE_DONE, to be cleared by caller */
444 outb_p(status, SMBHSTSTS(priv));
445
446 return result;
447 }
448
449 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)450 static int i801_wait_intr(struct i801_priv *priv)
451 {
452 int timeout = 0;
453 int status;
454
455 /* We will always wait for a fraction of a second! */
456 do {
457 usleep_range(250, 500);
458 status = inb_p(SMBHSTSTS(priv));
459 } while (((status & SMBHSTSTS_HOST_BUSY) ||
460 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
461 (timeout++ < MAX_RETRIES));
462
463 if (timeout > MAX_RETRIES) {
464 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
465 return -ETIMEDOUT;
466 }
467 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
468 }
469
470 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)471 static int i801_wait_byte_done(struct i801_priv *priv)
472 {
473 int timeout = 0;
474 int status;
475
476 /* We will always wait for a fraction of a second! */
477 do {
478 usleep_range(250, 500);
479 status = inb_p(SMBHSTSTS(priv));
480 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
481 (timeout++ < MAX_RETRIES));
482
483 if (timeout > MAX_RETRIES) {
484 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
485 return -ETIMEDOUT;
486 }
487 return status & STATUS_ERROR_FLAGS;
488 }
489
i801_transaction(struct i801_priv * priv,int xact)490 static int i801_transaction(struct i801_priv *priv, int xact)
491 {
492 int status;
493 int result;
494 const struct i2c_adapter *adap = &priv->adapter;
495
496 result = i801_check_pre(priv);
497 if (result < 0)
498 return result;
499
500 if (priv->features & FEATURE_IRQ) {
501 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
502 SMBHSTCNT(priv));
503 result = wait_event_timeout(priv->waitq,
504 (status = priv->status),
505 adap->timeout);
506 if (!result) {
507 status = -ETIMEDOUT;
508 dev_warn(&priv->pci_dev->dev,
509 "Timeout waiting for interrupt!\n");
510 }
511 priv->status = 0;
512 return i801_check_post(priv, status);
513 }
514
515 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
516 * SMBSCMD are passed in xact */
517 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
518
519 status = i801_wait_intr(priv);
520 return i801_check_post(priv, status);
521 }
522
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command,int hwpec)523 static int i801_block_transaction_by_block(struct i801_priv *priv,
524 union i2c_smbus_data *data,
525 char read_write, int command,
526 int hwpec)
527 {
528 int i, len;
529 int status;
530 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
531
532 switch (command) {
533 case I2C_SMBUS_BLOCK_PROC_CALL:
534 xact |= I801_BLOCK_PROC_CALL;
535 break;
536 case I2C_SMBUS_BLOCK_DATA:
537 xact |= I801_BLOCK_DATA;
538 break;
539 default:
540 return -EOPNOTSUPP;
541 }
542
543 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
544
545 /* Use 32-byte buffer to process this transaction */
546 if (read_write == I2C_SMBUS_WRITE) {
547 len = data->block[0];
548 outb_p(len, SMBHSTDAT0(priv));
549 for (i = 0; i < len; i++)
550 outb_p(data->block[i+1], SMBBLKDAT(priv));
551 }
552
553 status = i801_transaction(priv, xact);
554 if (status)
555 return status;
556
557 if (read_write == I2C_SMBUS_READ ||
558 command == I2C_SMBUS_BLOCK_PROC_CALL) {
559 len = inb_p(SMBHSTDAT0(priv));
560 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
561 return -EPROTO;
562
563 data->block[0] = len;
564 for (i = 0; i < len; i++)
565 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
566 }
567 return 0;
568 }
569
i801_isr_byte_done(struct i801_priv * priv)570 static void i801_isr_byte_done(struct i801_priv *priv)
571 {
572 if (priv->is_read) {
573 /* For SMBus block reads, length is received with first byte */
574 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
575 (priv->count == 0)) {
576 priv->len = inb_p(SMBHSTDAT0(priv));
577 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
578 dev_err(&priv->pci_dev->dev,
579 "Illegal SMBus block read size %d\n",
580 priv->len);
581 /* FIXME: Recover */
582 priv->len = I2C_SMBUS_BLOCK_MAX;
583 } else {
584 dev_dbg(&priv->pci_dev->dev,
585 "SMBus block read size is %d\n",
586 priv->len);
587 }
588 priv->data[-1] = priv->len;
589 }
590
591 /* Read next byte */
592 if (priv->count < priv->len)
593 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
594 else
595 dev_dbg(&priv->pci_dev->dev,
596 "Discarding extra byte on block read\n");
597
598 /* Set LAST_BYTE for last byte of read transaction */
599 if (priv->count == priv->len - 1)
600 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
601 SMBHSTCNT(priv));
602 } else if (priv->count < priv->len - 1) {
603 /* Write next byte, except for IRQ after last byte */
604 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
605 }
606
607 /* Clear BYTE_DONE to continue with next byte */
608 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
609 }
610
i801_host_notify_isr(struct i801_priv * priv)611 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
612 {
613 unsigned short addr;
614
615 addr = inb_p(SMBNTFDADD(priv)) >> 1;
616
617 /*
618 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
619 * always returns 0. Our current implementation doesn't provide
620 * data, so we just ignore it.
621 */
622 i2c_handle_smbus_host_notify(&priv->adapter, addr);
623
624 /* clear Host Notify bit and return */
625 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
626 return IRQ_HANDLED;
627 }
628
629 /*
630 * There are three kinds of interrupts:
631 *
632 * 1) i801 signals transaction completion with one of these interrupts:
633 * INTR - Success
634 * DEV_ERR - Invalid command, NAK or communication timeout
635 * BUS_ERR - SMI# transaction collision
636 * FAILED - transaction was canceled due to a KILL request
637 * When any of these occur, update ->status and wake up the waitq.
638 * ->status must be cleared before kicking off the next transaction.
639 *
640 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
641 * occurs for each byte of a byte-by-byte to prepare the next byte.
642 *
643 * 3) Host Notify interrupts
644 */
i801_isr(int irq,void * dev_id)645 static irqreturn_t i801_isr(int irq, void *dev_id)
646 {
647 struct i801_priv *priv = dev_id;
648 u16 pcists;
649 u8 status;
650
651 /* Confirm this is our interrupt */
652 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
653 if (!(pcists & SMBPCISTS_INTS))
654 return IRQ_NONE;
655
656 if (priv->features & FEATURE_HOST_NOTIFY) {
657 status = inb_p(SMBSLVSTS(priv));
658 if (status & SMBSLVSTS_HST_NTFY_STS)
659 return i801_host_notify_isr(priv);
660 }
661
662 status = inb_p(SMBHSTSTS(priv));
663 if (status & SMBHSTSTS_BYTE_DONE)
664 i801_isr_byte_done(priv);
665
666 /*
667 * Clear irq sources and report transaction result.
668 * ->status must be cleared before the next transaction is started.
669 */
670 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
671 if (status) {
672 outb_p(status, SMBHSTSTS(priv));
673 priv->status = status;
674 wake_up(&priv->waitq);
675 }
676
677 return IRQ_HANDLED;
678 }
679
680 /*
681 * For "byte-by-byte" block transactions:
682 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
683 * I2C read uses cmd=I801_I2C_BLOCK_DATA
684 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command,int hwpec)685 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
686 union i2c_smbus_data *data,
687 char read_write, int command,
688 int hwpec)
689 {
690 int i, len;
691 int smbcmd;
692 int status;
693 int result;
694 const struct i2c_adapter *adap = &priv->adapter;
695
696 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
697 return -EOPNOTSUPP;
698
699 result = i801_check_pre(priv);
700 if (result < 0)
701 return result;
702
703 len = data->block[0];
704
705 if (read_write == I2C_SMBUS_WRITE) {
706 outb_p(len, SMBHSTDAT0(priv));
707 outb_p(data->block[1], SMBBLKDAT(priv));
708 }
709
710 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
711 read_write == I2C_SMBUS_READ)
712 smbcmd = I801_I2C_BLOCK_DATA;
713 else
714 smbcmd = I801_BLOCK_DATA;
715
716 if (priv->features & FEATURE_IRQ) {
717 priv->is_read = (read_write == I2C_SMBUS_READ);
718 if (len == 1 && priv->is_read)
719 smbcmd |= SMBHSTCNT_LAST_BYTE;
720 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
721 priv->len = len;
722 priv->count = 0;
723 priv->data = &data->block[1];
724
725 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
726 result = wait_event_timeout(priv->waitq,
727 (status = priv->status),
728 adap->timeout);
729 if (!result) {
730 status = -ETIMEDOUT;
731 dev_warn(&priv->pci_dev->dev,
732 "Timeout waiting for interrupt!\n");
733 }
734 priv->status = 0;
735 return i801_check_post(priv, status);
736 }
737
738 if (len == 1 && read_write == I2C_SMBUS_READ)
739 smbcmd |= SMBHSTCNT_LAST_BYTE;
740 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
741
742 for (i = 1; i <= len; i++) {
743 status = i801_wait_byte_done(priv);
744 if (status)
745 goto exit;
746
747 if (i == 1 && read_write == I2C_SMBUS_READ
748 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
749 len = inb_p(SMBHSTDAT0(priv));
750 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
751 dev_err(&priv->pci_dev->dev,
752 "Illegal SMBus block read size %d\n",
753 len);
754 /* Recover */
755 while (inb_p(SMBHSTSTS(priv)) &
756 SMBHSTSTS_HOST_BUSY)
757 outb_p(SMBHSTSTS_BYTE_DONE,
758 SMBHSTSTS(priv));
759 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
760 return -EPROTO;
761 }
762 data->block[0] = len;
763 }
764
765 if (read_write == I2C_SMBUS_READ) {
766 data->block[i] = inb_p(SMBBLKDAT(priv));
767 if (i == len - 1)
768 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
769 }
770
771 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
772 outb_p(data->block[i+1], SMBBLKDAT(priv));
773
774 /* signals SMBBLKDAT ready */
775 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
776 }
777
778 status = i801_wait_intr(priv);
779 exit:
780 return i801_check_post(priv, status);
781 }
782
i801_set_block_buffer_mode(struct i801_priv * priv)783 static int i801_set_block_buffer_mode(struct i801_priv *priv)
784 {
785 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
786 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
787 return -EIO;
788 return 0;
789 }
790
791 /* Block transaction function */
i801_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command,int hwpec)792 static int i801_block_transaction(struct i801_priv *priv,
793 union i2c_smbus_data *data, char read_write,
794 int command, int hwpec)
795 {
796 int result = 0;
797 unsigned char hostc;
798
799 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
800 data->block[0] = I2C_SMBUS_BLOCK_MAX;
801 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
802 return -EPROTO;
803
804 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
805 if (read_write == I2C_SMBUS_WRITE) {
806 /* set I2C_EN bit in configuration register */
807 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
808 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
809 hostc | SMBHSTCFG_I2C_EN);
810 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
811 dev_err(&priv->pci_dev->dev,
812 "I2C block read is unsupported!\n");
813 return -EOPNOTSUPP;
814 }
815 }
816
817 /* Experience has shown that the block buffer can only be used for
818 SMBus (not I2C) block transactions, even though the datasheet
819 doesn't mention this limitation. */
820 if ((priv->features & FEATURE_BLOCK_BUFFER)
821 && command != I2C_SMBUS_I2C_BLOCK_DATA
822 && i801_set_block_buffer_mode(priv) == 0)
823 result = i801_block_transaction_by_block(priv, data,
824 read_write,
825 command, hwpec);
826 else
827 result = i801_block_transaction_byte_by_byte(priv, data,
828 read_write,
829 command, hwpec);
830
831 if (command == I2C_SMBUS_I2C_BLOCK_DATA
832 && read_write == I2C_SMBUS_WRITE) {
833 /* restore saved configuration register value */
834 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
835 }
836 return result;
837 }
838
839 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)840 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
841 unsigned short flags, char read_write, u8 command,
842 int size, union i2c_smbus_data *data)
843 {
844 int hwpec;
845 int block = 0;
846 int ret = 0, xact = 0;
847 struct i801_priv *priv = i2c_get_adapdata(adap);
848
849 mutex_lock(&priv->acpi_lock);
850 if (priv->acpi_reserved) {
851 mutex_unlock(&priv->acpi_lock);
852 return -EBUSY;
853 }
854
855 pm_runtime_get_sync(&priv->pci_dev->dev);
856
857 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
858 && size != I2C_SMBUS_QUICK
859 && size != I2C_SMBUS_I2C_BLOCK_DATA;
860
861 switch (size) {
862 case I2C_SMBUS_QUICK:
863 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
864 SMBHSTADD(priv));
865 xact = I801_QUICK;
866 break;
867 case I2C_SMBUS_BYTE:
868 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
869 SMBHSTADD(priv));
870 if (read_write == I2C_SMBUS_WRITE)
871 outb_p(command, SMBHSTCMD(priv));
872 xact = I801_BYTE;
873 break;
874 case I2C_SMBUS_BYTE_DATA:
875 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
876 SMBHSTADD(priv));
877 outb_p(command, SMBHSTCMD(priv));
878 if (read_write == I2C_SMBUS_WRITE)
879 outb_p(data->byte, SMBHSTDAT0(priv));
880 xact = I801_BYTE_DATA;
881 break;
882 case I2C_SMBUS_WORD_DATA:
883 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
884 SMBHSTADD(priv));
885 outb_p(command, SMBHSTCMD(priv));
886 if (read_write == I2C_SMBUS_WRITE) {
887 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
888 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
889 }
890 xact = I801_WORD_DATA;
891 break;
892 case I2C_SMBUS_BLOCK_DATA:
893 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
894 SMBHSTADD(priv));
895 outb_p(command, SMBHSTCMD(priv));
896 block = 1;
897 break;
898 case I2C_SMBUS_I2C_BLOCK_DATA:
899 /*
900 * NB: page 240 of ICH5 datasheet shows that the R/#W
901 * bit should be cleared here, even when reading.
902 * However if SPD Write Disable is set (Lynx Point and later),
903 * the read will fail if we don't set the R/#W bit.
904 */
905 outb_p(((addr & 0x7f) << 1) |
906 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
907 (read_write & 0x01) : 0),
908 SMBHSTADD(priv));
909 if (read_write == I2C_SMBUS_READ) {
910 /* NB: page 240 of ICH5 datasheet also shows
911 * that DATA1 is the cmd field when reading */
912 outb_p(command, SMBHSTDAT1(priv));
913 } else
914 outb_p(command, SMBHSTCMD(priv));
915 block = 1;
916 break;
917 case I2C_SMBUS_BLOCK_PROC_CALL:
918 /*
919 * Bit 0 of the slave address register always indicate a write
920 * command.
921 */
922 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
923 outb_p(command, SMBHSTCMD(priv));
924 block = 1;
925 break;
926 default:
927 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
928 size);
929 ret = -EOPNOTSUPP;
930 goto out;
931 }
932
933 if (hwpec) /* enable/disable hardware PEC */
934 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
935 else
936 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
937 SMBAUXCTL(priv));
938
939 if (block)
940 ret = i801_block_transaction(priv, data, read_write, size,
941 hwpec);
942 else
943 ret = i801_transaction(priv, xact);
944
945 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
946 time, so we forcibly disable it after every transaction. Turn off
947 E32B for the same reason. */
948 if (hwpec || block)
949 outb_p(inb_p(SMBAUXCTL(priv)) &
950 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
951
952 if (block)
953 goto out;
954 if (ret)
955 goto out;
956 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
957 goto out;
958
959 switch (xact & 0x7f) {
960 case I801_BYTE: /* Result put in SMBHSTDAT0 */
961 case I801_BYTE_DATA:
962 data->byte = inb_p(SMBHSTDAT0(priv));
963 break;
964 case I801_WORD_DATA:
965 data->word = inb_p(SMBHSTDAT0(priv)) +
966 (inb_p(SMBHSTDAT1(priv)) << 8);
967 break;
968 }
969
970 out:
971 /* Unlock the SMBus device for use by BIOS/ACPI */
972 outb_p(SMBHSTSTS_INUSE_STS, SMBHSTSTS(priv));
973
974 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
975 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
976 mutex_unlock(&priv->acpi_lock);
977 return ret;
978 }
979
980
i801_func(struct i2c_adapter * adapter)981 static u32 i801_func(struct i2c_adapter *adapter)
982 {
983 struct i801_priv *priv = i2c_get_adapdata(adapter);
984
985 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
986 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
987 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
988 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
989 ((priv->features & FEATURE_BLOCK_PROC) ?
990 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
991 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
992 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
993 ((priv->features & FEATURE_HOST_NOTIFY) ?
994 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
995 }
996
i801_enable_host_notify(struct i2c_adapter * adapter)997 static void i801_enable_host_notify(struct i2c_adapter *adapter)
998 {
999 struct i801_priv *priv = i2c_get_adapdata(adapter);
1000
1001 if (!(priv->features & FEATURE_HOST_NOTIFY))
1002 return;
1003
1004 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1005 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1006 SMBSLVCMD(priv));
1007
1008 /* clear Host Notify bit to allow a new notification */
1009 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1010 }
1011
i801_disable_host_notify(struct i801_priv * priv)1012 static void i801_disable_host_notify(struct i801_priv *priv)
1013 {
1014 if (!(priv->features & FEATURE_HOST_NOTIFY))
1015 return;
1016
1017 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1018 }
1019
1020 static const struct i2c_algorithm smbus_algorithm = {
1021 .smbus_xfer = i801_access,
1022 .functionality = i801_func,
1023 };
1024
1025 static const struct pci_device_id i801_ids[] = {
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) },
1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1078 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1079 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
1080 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1081 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) },
1082 { 0, }
1083 };
1084
1085 MODULE_DEVICE_TABLE(pci, i801_ids);
1086
1087 #if defined CONFIG_X86 && defined CONFIG_DMI
1088 static unsigned char apanel_addr;
1089
1090 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1091 static __init const void __iomem *bios_signature(const void __iomem *bios)
1092 {
1093 ssize_t offset;
1094 const unsigned char signature[] = "FJKEYINF";
1095
1096 for (offset = 0; offset < 0x10000; offset += 0x10) {
1097 if (check_signature(bios + offset, signature,
1098 sizeof(signature)-1))
1099 return bios + offset;
1100 }
1101 return NULL;
1102 }
1103
input_apanel_init(void)1104 static void __init input_apanel_init(void)
1105 {
1106 void __iomem *bios;
1107 const void __iomem *p;
1108
1109 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1110 p = bios_signature(bios);
1111 if (p) {
1112 /* just use the first address */
1113 apanel_addr = readb(p + 8 + 3) >> 1;
1114 }
1115 iounmap(bios);
1116 }
1117
1118 struct dmi_onboard_device_info {
1119 const char *name;
1120 u8 type;
1121 unsigned short i2c_addr;
1122 const char *i2c_type;
1123 };
1124
1125 static const struct dmi_onboard_device_info dmi_devices[] = {
1126 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1127 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1128 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1129 };
1130
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1131 static void dmi_check_onboard_device(u8 type, const char *name,
1132 struct i2c_adapter *adap)
1133 {
1134 int i;
1135 struct i2c_board_info info;
1136
1137 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1138 /* & ~0x80, ignore enabled/disabled bit */
1139 if ((type & ~0x80) != dmi_devices[i].type)
1140 continue;
1141 if (strcasecmp(name, dmi_devices[i].name))
1142 continue;
1143
1144 memset(&info, 0, sizeof(struct i2c_board_info));
1145 info.addr = dmi_devices[i].i2c_addr;
1146 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1147 i2c_new_client_device(adap, &info);
1148 break;
1149 }
1150 }
1151
1152 /* We use our own function to check for onboard devices instead of
1153 dmi_find_device() as some buggy BIOS's have the devices we are interested
1154 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1155 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1156 {
1157 int i, count;
1158
1159 if (dm->type != 10)
1160 return;
1161
1162 count = (dm->length - sizeof(struct dmi_header)) / 2;
1163 for (i = 0; i < count; i++) {
1164 const u8 *d = (char *)(dm + 1) + (i * 2);
1165 const char *name = ((char *) dm) + dm->length;
1166 u8 type = d[0];
1167 u8 s = d[1];
1168
1169 if (!s)
1170 continue;
1171 s--;
1172 while (s > 0 && name[0]) {
1173 name += strlen(name) + 1;
1174 s--;
1175 }
1176 if (name[0] == 0) /* Bogus string reference */
1177 continue;
1178
1179 dmi_check_onboard_device(type, name, adap);
1180 }
1181 }
1182
1183 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1184 static const char *const acpi_smo8800_ids[] = {
1185 "SMO8800",
1186 "SMO8801",
1187 "SMO8810",
1188 "SMO8811",
1189 "SMO8820",
1190 "SMO8821",
1191 "SMO8830",
1192 "SMO8831",
1193 };
1194
check_acpi_smo88xx_device(acpi_handle obj_handle,u32 nesting_level,void * context,void ** return_value)1195 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1196 u32 nesting_level,
1197 void *context,
1198 void **return_value)
1199 {
1200 struct acpi_device_info *info;
1201 acpi_status status;
1202 char *hid;
1203 int i;
1204
1205 status = acpi_get_object_info(obj_handle, &info);
1206 if (ACPI_FAILURE(status))
1207 return AE_OK;
1208
1209 if (!(info->valid & ACPI_VALID_HID))
1210 goto smo88xx_not_found;
1211
1212 hid = info->hardware_id.string;
1213 if (!hid)
1214 goto smo88xx_not_found;
1215
1216 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1217 if (i < 0)
1218 goto smo88xx_not_found;
1219
1220 kfree(info);
1221
1222 *((bool *)return_value) = true;
1223 return AE_CTRL_TERMINATE;
1224
1225 smo88xx_not_found:
1226 kfree(info);
1227 return AE_OK;
1228 }
1229
is_dell_system_with_lis3lv02d(void)1230 static bool is_dell_system_with_lis3lv02d(void)
1231 {
1232 bool found;
1233 const char *vendor;
1234
1235 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1236 if (!vendor || strcmp(vendor, "Dell Inc."))
1237 return false;
1238
1239 /*
1240 * Check that ACPI device SMO88xx is present and is functioning.
1241 * Function acpi_get_devices() already filters all ACPI devices
1242 * which are not present or are not functioning.
1243 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1244 * accelerometer but unfortunately ACPI does not provide any other
1245 * information (like I2C address).
1246 */
1247 found = false;
1248 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1249 (void **)&found);
1250
1251 return found;
1252 }
1253
1254 /*
1255 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1256 * so it is needed to define mapping table based on DMI product names.
1257 */
1258 static const struct {
1259 const char *dmi_product_name;
1260 unsigned short i2c_addr;
1261 } dell_lis3lv02d_devices[] = {
1262 /*
1263 * Dell platform team told us that these Latitude devices have
1264 * ST microelectronics accelerometer at I2C address 0x29.
1265 */
1266 { "Latitude E5250", 0x29 },
1267 { "Latitude E5450", 0x29 },
1268 { "Latitude E5550", 0x29 },
1269 { "Latitude E6440", 0x29 },
1270 { "Latitude E6440 ATG", 0x29 },
1271 { "Latitude E6540", 0x29 },
1272 /*
1273 * Additional individual entries were added after verification.
1274 */
1275 { "Latitude 5480", 0x29 },
1276 { "Vostro V131", 0x1d },
1277 { "Vostro 5568", 0x29 },
1278 };
1279
register_dell_lis3lv02d_i2c_device(struct i801_priv * priv)1280 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1281 {
1282 struct i2c_board_info info;
1283 const char *dmi_product_name;
1284 int i;
1285
1286 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1287 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1288 if (strcmp(dmi_product_name,
1289 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1290 break;
1291 }
1292
1293 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1294 dev_warn(&priv->pci_dev->dev,
1295 "Accelerometer lis3lv02d is present on SMBus but its"
1296 " address is unknown, skipping registration\n");
1297 return;
1298 }
1299
1300 memset(&info, 0, sizeof(struct i2c_board_info));
1301 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1302 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1303 i2c_new_client_device(&priv->adapter, &info);
1304 }
1305
1306 /* Register optional slaves */
i801_probe_optional_slaves(struct i801_priv * priv)1307 static void i801_probe_optional_slaves(struct i801_priv *priv)
1308 {
1309 /* Only register slaves on main SMBus channel */
1310 if (priv->features & FEATURE_IDF)
1311 return;
1312
1313 if (apanel_addr) {
1314 struct i2c_board_info info;
1315
1316 memset(&info, 0, sizeof(struct i2c_board_info));
1317 info.addr = apanel_addr;
1318 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1319 i2c_new_client_device(&priv->adapter, &info);
1320 }
1321
1322 if (dmi_name_in_vendors("FUJITSU"))
1323 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1324
1325 if (is_dell_system_with_lis3lv02d())
1326 register_dell_lis3lv02d_i2c_device(priv);
1327
1328 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1329 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1330 if (!priv->mux_drvdata)
1331 #endif
1332 i2c_register_spd(&priv->adapter);
1333 }
1334 #else
input_apanel_init(void)1335 static void __init input_apanel_init(void) {}
i801_probe_optional_slaves(struct i801_priv * priv)1336 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1337 #endif /* CONFIG_X86 && CONFIG_DMI */
1338
1339 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1340 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1341 .gpio_chip = "gpio_ich",
1342 .values = { 0x02, 0x03 },
1343 .n_values = 2,
1344 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1345 .gpios = { 52, 53 },
1346 .n_gpios = 2,
1347 };
1348
1349 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1350 .gpio_chip = "gpio_ich",
1351 .values = { 0x02, 0x03, 0x01 },
1352 .n_values = 3,
1353 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1354 .gpios = { 52, 53 },
1355 .n_gpios = 2,
1356 };
1357
1358 static const struct dmi_system_id mux_dmi_table[] = {
1359 {
1360 .matches = {
1361 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1362 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1363 },
1364 .driver_data = &i801_mux_config_asus_z8_d12,
1365 },
1366 {
1367 .matches = {
1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1369 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1370 },
1371 .driver_data = &i801_mux_config_asus_z8_d12,
1372 },
1373 {
1374 .matches = {
1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1376 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1377 },
1378 .driver_data = &i801_mux_config_asus_z8_d12,
1379 },
1380 {
1381 .matches = {
1382 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1383 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1384 },
1385 .driver_data = &i801_mux_config_asus_z8_d12,
1386 },
1387 {
1388 .matches = {
1389 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1390 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1391 },
1392 .driver_data = &i801_mux_config_asus_z8_d12,
1393 },
1394 {
1395 .matches = {
1396 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1397 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1398 },
1399 .driver_data = &i801_mux_config_asus_z8_d12,
1400 },
1401 {
1402 .matches = {
1403 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1404 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1405 },
1406 .driver_data = &i801_mux_config_asus_z8_d18,
1407 },
1408 {
1409 .matches = {
1410 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1411 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1412 },
1413 .driver_data = &i801_mux_config_asus_z8_d18,
1414 },
1415 {
1416 .matches = {
1417 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1418 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1419 },
1420 .driver_data = &i801_mux_config_asus_z8_d12,
1421 },
1422 { }
1423 };
1424
1425 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1426 static int i801_add_mux(struct i801_priv *priv)
1427 {
1428 struct device *dev = &priv->adapter.dev;
1429 const struct i801_mux_config *mux_config;
1430 struct i2c_mux_gpio_platform_data gpio_data;
1431 struct gpiod_lookup_table *lookup;
1432 int err, i;
1433
1434 if (!priv->mux_drvdata)
1435 return 0;
1436 mux_config = priv->mux_drvdata;
1437
1438 /* Prepare the platform data */
1439 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1440 gpio_data.parent = priv->adapter.nr;
1441 gpio_data.values = mux_config->values;
1442 gpio_data.n_values = mux_config->n_values;
1443 gpio_data.classes = mux_config->classes;
1444 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1445
1446 /* Register GPIO descriptor lookup table */
1447 lookup = devm_kzalloc(dev,
1448 struct_size(lookup, table, mux_config->n_gpios + 1),
1449 GFP_KERNEL);
1450 if (!lookup)
1451 return -ENOMEM;
1452 lookup->dev_id = "i2c-mux-gpio";
1453 for (i = 0; i < mux_config->n_gpios; i++) {
1454 lookup->table[i] = (struct gpiod_lookup)
1455 GPIO_LOOKUP(mux_config->gpio_chip,
1456 mux_config->gpios[i], "mux", 0);
1457 }
1458 gpiod_add_lookup_table(lookup);
1459 priv->lookup = lookup;
1460
1461 /*
1462 * Register the mux device, we use PLATFORM_DEVID_NONE here
1463 * because since we are referring to the GPIO chip by name we are
1464 * anyways in deep trouble if there is more than one of these
1465 * devices, and there should likely only be one platform controller
1466 * hub.
1467 */
1468 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1469 PLATFORM_DEVID_NONE, &gpio_data,
1470 sizeof(struct i2c_mux_gpio_platform_data));
1471 if (IS_ERR(priv->mux_pdev)) {
1472 err = PTR_ERR(priv->mux_pdev);
1473 gpiod_remove_lookup_table(lookup);
1474 priv->mux_pdev = NULL;
1475 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1476 return err;
1477 }
1478
1479 return 0;
1480 }
1481
i801_del_mux(struct i801_priv * priv)1482 static void i801_del_mux(struct i801_priv *priv)
1483 {
1484 if (priv->mux_pdev)
1485 platform_device_unregister(priv->mux_pdev);
1486 if (priv->lookup)
1487 gpiod_remove_lookup_table(priv->lookup);
1488 }
1489
i801_get_adapter_class(struct i801_priv * priv)1490 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1491 {
1492 const struct dmi_system_id *id;
1493 const struct i801_mux_config *mux_config;
1494 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1495 int i;
1496
1497 id = dmi_first_match(mux_dmi_table);
1498 if (id) {
1499 /* Remove branch classes from trunk */
1500 mux_config = id->driver_data;
1501 for (i = 0; i < mux_config->n_values; i++)
1502 class &= ~mux_config->classes[i];
1503
1504 /* Remember for later */
1505 priv->mux_drvdata = mux_config;
1506 }
1507
1508 return class;
1509 }
1510 #else
i801_add_mux(struct i801_priv * priv)1511 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
i801_del_mux(struct i801_priv * priv)1512 static inline void i801_del_mux(struct i801_priv *priv) { }
1513
i801_get_adapter_class(struct i801_priv * priv)1514 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1515 {
1516 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1517 }
1518 #endif
1519
1520 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1521 .name = "Intel PCH",
1522 .version = 4,
1523 };
1524
1525 static DEFINE_SPINLOCK(p2sb_spinlock);
1526
1527 static struct platform_device *
i801_add_tco_spt(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1528 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1529 struct resource *tco_res)
1530 {
1531 struct resource *res;
1532 unsigned int devfn;
1533 u64 base64_addr;
1534 u32 base_addr;
1535 u8 hidden;
1536
1537 /*
1538 * We must access the NO_REBOOT bit over the Primary to Sideband
1539 * bridge (P2SB). The BIOS prevents the P2SB device from being
1540 * enumerated by the PCI subsystem, so we need to unhide/hide it
1541 * to lookup the P2SB BAR.
1542 */
1543 spin_lock(&p2sb_spinlock);
1544
1545 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1546
1547 /* Unhide the P2SB device, if it is hidden */
1548 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1549 if (hidden)
1550 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1551
1552 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1553 base64_addr = base_addr & 0xfffffff0;
1554
1555 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1556 base64_addr |= (u64)base_addr << 32;
1557
1558 /* Hide the P2SB device, if it was hidden before */
1559 if (hidden)
1560 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1561 spin_unlock(&p2sb_spinlock);
1562
1563 res = &tco_res[1];
1564 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1565 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1566 else
1567 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1568
1569 res->end = res->start + 3;
1570 res->flags = IORESOURCE_MEM;
1571
1572 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1573 tco_res, 2, &spt_tco_platform_data,
1574 sizeof(spt_tco_platform_data));
1575 }
1576
1577 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1578 .name = "Intel PCH",
1579 .version = 6,
1580 };
1581
1582 static struct platform_device *
i801_add_tco_cnl(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1583 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1584 struct resource *tco_res)
1585 {
1586 return platform_device_register_resndata(&pci_dev->dev,
1587 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1588 sizeof(cnl_tco_platform_data));
1589 }
1590
i801_add_tco(struct i801_priv * priv)1591 static void i801_add_tco(struct i801_priv *priv)
1592 {
1593 struct pci_dev *pci_dev = priv->pci_dev;
1594 struct resource tco_res[2], *res;
1595 u32 tco_base, tco_ctl;
1596
1597 /* If we have ACPI based watchdog use that instead */
1598 if (acpi_has_watchdog())
1599 return;
1600
1601 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1602 return;
1603
1604 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1605 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1606 if (!(tco_ctl & TCOCTL_EN))
1607 return;
1608
1609 memset(tco_res, 0, sizeof(tco_res));
1610 /*
1611 * Always populate the main iTCO IO resource here. The second entry
1612 * for NO_REBOOT MMIO is filled by the SPT specific function.
1613 */
1614 res = &tco_res[0];
1615 res->start = tco_base & ~1;
1616 res->end = res->start + 32 - 1;
1617 res->flags = IORESOURCE_IO;
1618
1619 if (priv->features & FEATURE_TCO_CNL)
1620 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1621 else
1622 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1623
1624 if (IS_ERR(priv->tco_pdev))
1625 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1626 }
1627
1628 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1629 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1630 acpi_physical_address address)
1631 {
1632 return address >= priv->smba &&
1633 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1634 }
1635
1636 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1637 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1638 u64 *value, void *handler_context, void *region_context)
1639 {
1640 struct i801_priv *priv = handler_context;
1641 struct pci_dev *pdev = priv->pci_dev;
1642 acpi_status status;
1643
1644 /*
1645 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1646 * further access from the driver itself. This device is now owned
1647 * by the system firmware.
1648 */
1649 mutex_lock(&priv->acpi_lock);
1650
1651 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1652 priv->acpi_reserved = true;
1653
1654 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1655 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1656
1657 /*
1658 * BIOS is accessing the host controller so prevent it from
1659 * suspending automatically from now on.
1660 */
1661 pm_runtime_get_sync(&pdev->dev);
1662 }
1663
1664 if ((function & ACPI_IO_MASK) == ACPI_READ)
1665 status = acpi_os_read_port(address, (u32 *)value, bits);
1666 else
1667 status = acpi_os_write_port(address, (u32)*value, bits);
1668
1669 mutex_unlock(&priv->acpi_lock);
1670
1671 return status;
1672 }
1673
i801_acpi_probe(struct i801_priv * priv)1674 static int i801_acpi_probe(struct i801_priv *priv)
1675 {
1676 struct acpi_device *adev;
1677 acpi_status status;
1678
1679 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1680 if (adev) {
1681 status = acpi_install_address_space_handler(adev->handle,
1682 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1683 NULL, priv);
1684 if (ACPI_SUCCESS(status))
1685 return 0;
1686 }
1687
1688 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1689 }
1690
i801_acpi_remove(struct i801_priv * priv)1691 static void i801_acpi_remove(struct i801_priv *priv)
1692 {
1693 struct acpi_device *adev;
1694
1695 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1696 if (!adev)
1697 return;
1698
1699 acpi_remove_address_space_handler(adev->handle,
1700 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1701
1702 mutex_lock(&priv->acpi_lock);
1703 if (priv->acpi_reserved)
1704 pm_runtime_put(&priv->pci_dev->dev);
1705 mutex_unlock(&priv->acpi_lock);
1706 }
1707 #else
i801_acpi_probe(struct i801_priv * priv)1708 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1709 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1710 #endif
1711
i801_setup_hstcfg(struct i801_priv * priv)1712 static unsigned char i801_setup_hstcfg(struct i801_priv *priv)
1713 {
1714 unsigned char hstcfg = priv->original_hstcfg;
1715
1716 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1717 hstcfg |= SMBHSTCFG_HST_EN;
1718 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1719 return hstcfg;
1720 }
1721
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1722 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1723 {
1724 unsigned char temp;
1725 int err, i;
1726 struct i801_priv *priv;
1727
1728 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1729 if (!priv)
1730 return -ENOMEM;
1731
1732 i2c_set_adapdata(&priv->adapter, priv);
1733 priv->adapter.owner = THIS_MODULE;
1734 priv->adapter.class = i801_get_adapter_class(priv);
1735 priv->adapter.algo = &smbus_algorithm;
1736 priv->adapter.dev.parent = &dev->dev;
1737 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1738 priv->adapter.retries = 3;
1739 mutex_init(&priv->acpi_lock);
1740
1741 priv->pci_dev = dev;
1742 switch (dev->device) {
1743 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1744 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1745 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1746 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1747 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1748 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1749 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
1750 priv->features |= FEATURE_BLOCK_PROC;
1751 priv->features |= FEATURE_I2C_BLOCK_READ;
1752 priv->features |= FEATURE_IRQ;
1753 priv->features |= FEATURE_SMBUS_PEC;
1754 priv->features |= FEATURE_BLOCK_BUFFER;
1755 priv->features |= FEATURE_TCO_SPT;
1756 priv->features |= FEATURE_HOST_NOTIFY;
1757 break;
1758
1759 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1760 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1761 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1762 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1763 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1764 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1765 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1766 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1767 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS:
1768 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1769 case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
1770 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS:
1771 priv->features |= FEATURE_BLOCK_PROC;
1772 priv->features |= FEATURE_I2C_BLOCK_READ;
1773 priv->features |= FEATURE_IRQ;
1774 priv->features |= FEATURE_SMBUS_PEC;
1775 priv->features |= FEATURE_BLOCK_BUFFER;
1776 priv->features |= FEATURE_TCO_CNL;
1777 priv->features |= FEATURE_HOST_NOTIFY;
1778 break;
1779
1780 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1781 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1782 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1783 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1784 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1785 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1786 priv->features |= FEATURE_IDF;
1787 fallthrough;
1788 default:
1789 priv->features |= FEATURE_BLOCK_PROC;
1790 priv->features |= FEATURE_I2C_BLOCK_READ;
1791 priv->features |= FEATURE_IRQ;
1792 fallthrough;
1793 case PCI_DEVICE_ID_INTEL_82801DB_3:
1794 priv->features |= FEATURE_SMBUS_PEC;
1795 priv->features |= FEATURE_BLOCK_BUFFER;
1796 fallthrough;
1797 case PCI_DEVICE_ID_INTEL_82801CA_3:
1798 priv->features |= FEATURE_HOST_NOTIFY;
1799 fallthrough;
1800 case PCI_DEVICE_ID_INTEL_82801BA_2:
1801 case PCI_DEVICE_ID_INTEL_82801AB_3:
1802 case PCI_DEVICE_ID_INTEL_82801AA_3:
1803 break;
1804 }
1805
1806 /* Disable features on user request */
1807 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1808 if (priv->features & disable_features & (1 << i))
1809 dev_notice(&dev->dev, "%s disabled by user\n",
1810 i801_feature_names[i]);
1811 }
1812 priv->features &= ~disable_features;
1813
1814 err = pcim_enable_device(dev);
1815 if (err) {
1816 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1817 err);
1818 return err;
1819 }
1820 pcim_pin_device(dev);
1821
1822 /* Determine the address of the SMBus area */
1823 priv->smba = pci_resource_start(dev, SMBBAR);
1824 if (!priv->smba) {
1825 dev_err(&dev->dev,
1826 "SMBus base address uninitialized, upgrade BIOS\n");
1827 return -ENODEV;
1828 }
1829
1830 if (i801_acpi_probe(priv))
1831 return -ENODEV;
1832
1833 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1834 dev_driver_string(&dev->dev));
1835 if (err) {
1836 dev_err(&dev->dev,
1837 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1838 priv->smba,
1839 (unsigned long long)pci_resource_end(dev, SMBBAR));
1840 i801_acpi_remove(priv);
1841 return err;
1842 }
1843
1844 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1845 temp = i801_setup_hstcfg(priv);
1846 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1847 dev_info(&dev->dev, "Enabling SMBus device\n");
1848
1849 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1850 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1851 /* Disable SMBus interrupt feature if SMBus using SMI# */
1852 priv->features &= ~FEATURE_IRQ;
1853 }
1854 if (temp & SMBHSTCFG_SPD_WD)
1855 dev_info(&dev->dev, "SPD Write Disable is set\n");
1856
1857 /* Clear special mode bits */
1858 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1859 outb_p(inb_p(SMBAUXCTL(priv)) &
1860 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1861
1862 /* Remember original Host Notify setting */
1863 if (priv->features & FEATURE_HOST_NOTIFY)
1864 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1865
1866 /* Default timeout in interrupt mode: 200 ms */
1867 priv->adapter.timeout = HZ / 5;
1868
1869 if (dev->irq == IRQ_NOTCONNECTED)
1870 priv->features &= ~FEATURE_IRQ;
1871
1872 if (priv->features & FEATURE_IRQ) {
1873 u16 pcictl, pcists;
1874
1875 /* Complain if an interrupt is already pending */
1876 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1877 if (pcists & SMBPCISTS_INTS)
1878 dev_warn(&dev->dev, "An interrupt is pending!\n");
1879
1880 /* Check if interrupts have been disabled */
1881 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1882 if (pcictl & SMBPCICTL_INTDIS) {
1883 dev_info(&dev->dev, "Interrupts are disabled\n");
1884 priv->features &= ~FEATURE_IRQ;
1885 }
1886 }
1887
1888 if (priv->features & FEATURE_IRQ) {
1889 init_waitqueue_head(&priv->waitq);
1890
1891 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1892 IRQF_SHARED,
1893 dev_driver_string(&dev->dev), priv);
1894 if (err) {
1895 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1896 dev->irq, err);
1897 priv->features &= ~FEATURE_IRQ;
1898 }
1899 }
1900 dev_info(&dev->dev, "SMBus using %s\n",
1901 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1902
1903 i801_add_tco(priv);
1904
1905 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1906 "SMBus I801 adapter at %04lx", priv->smba);
1907 err = i2c_add_adapter(&priv->adapter);
1908 if (err) {
1909 platform_device_unregister(priv->tco_pdev);
1910 i801_acpi_remove(priv);
1911 return err;
1912 }
1913
1914 i801_enable_host_notify(&priv->adapter);
1915
1916 i801_probe_optional_slaves(priv);
1917 /* We ignore errors - multiplexing is optional */
1918 i801_add_mux(priv);
1919
1920 pci_set_drvdata(dev, priv);
1921
1922 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1923 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1924 pm_runtime_use_autosuspend(&dev->dev);
1925 pm_runtime_put_autosuspend(&dev->dev);
1926 pm_runtime_allow(&dev->dev);
1927
1928 return 0;
1929 }
1930
i801_remove(struct pci_dev * dev)1931 static void i801_remove(struct pci_dev *dev)
1932 {
1933 struct i801_priv *priv = pci_get_drvdata(dev);
1934
1935 pm_runtime_forbid(&dev->dev);
1936 pm_runtime_get_noresume(&dev->dev);
1937
1938 i801_disable_host_notify(priv);
1939 i801_del_mux(priv);
1940 i2c_del_adapter(&priv->adapter);
1941 i801_acpi_remove(priv);
1942 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1943
1944 platform_device_unregister(priv->tco_pdev);
1945
1946 /*
1947 * do not call pci_disable_device(dev) since it can cause hard hangs on
1948 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1949 */
1950 }
1951
i801_shutdown(struct pci_dev * dev)1952 static void i801_shutdown(struct pci_dev *dev)
1953 {
1954 struct i801_priv *priv = pci_get_drvdata(dev);
1955
1956 /* Restore config registers to avoid hard hang on some systems */
1957 i801_disable_host_notify(priv);
1958 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1959 }
1960
1961 #ifdef CONFIG_PM_SLEEP
i801_suspend(struct device * dev)1962 static int i801_suspend(struct device *dev)
1963 {
1964 struct i801_priv *priv = dev_get_drvdata(dev);
1965
1966 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1967 return 0;
1968 }
1969
i801_resume(struct device * dev)1970 static int i801_resume(struct device *dev)
1971 {
1972 struct i801_priv *priv = dev_get_drvdata(dev);
1973
1974 i801_setup_hstcfg(priv);
1975 i801_enable_host_notify(&priv->adapter);
1976
1977 return 0;
1978 }
1979 #endif
1980
1981 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1982
1983 static struct pci_driver i801_driver = {
1984 .name = "i801_smbus",
1985 .id_table = i801_ids,
1986 .probe = i801_probe,
1987 .remove = i801_remove,
1988 .shutdown = i801_shutdown,
1989 .driver = {
1990 .pm = &i801_pm_ops,
1991 },
1992 };
1993
i2c_i801_init(void)1994 static int __init i2c_i801_init(void)
1995 {
1996 if (dmi_name_in_vendors("FUJITSU"))
1997 input_apanel_init();
1998 return pci_register_driver(&i801_driver);
1999 }
2000
i2c_i801_exit(void)2001 static void __exit i2c_i801_exit(void)
2002 {
2003 pci_unregister_driver(&i801_driver);
2004 }
2005
2006 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
2007 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
2008 MODULE_DESCRIPTION("I801 SMBus driver");
2009 MODULE_LICENSE("GPL");
2010
2011 module_init(i2c_i801_init);
2012 module_exit(i2c_i801_exit);
2013