| /Documentation/devicetree/bindings/phy/ |
| D | microchip,sparx5-serdes.yaml | 34 * 100 Mbps (100BASE-FX)
35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
44 * 100 Mbps (100BASE-FX)
45 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
49 * 10 Gbps (10G-USGMII)
50 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
57 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
61 * 10 Gbps (10G-USGMII)
62 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
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| D | transmit-amplitude.yaml | 42 - 1000base-x
43 - 2500base-x
47 - 10gbase-kr
49 - 10gbase-r
83 - dp-uhbr-10
102 tx-p2p-microvolt-names = "2500base-x", "usb-hs", "usb-ss";
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,lan8650.yaml | 7 title: Microchip LAN8650/1 10BASE-T1S MACPHY Ethernet Controllers
14 PHY to enable 10BASE‑T1S networks. The Ethernet Media Access Controller
15 (MAC) module implements a 10 Mbps half duplex Ethernet MAC, compatible
16 with the IEEE 802.3 standard and a 10BASE-T1S physical layer transceiver
18 the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x MACPHY Serial
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| D | qcom,qca807x.yaml | 15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
47 Option 2 PSGMII for copper 1000BASE-X / 100BASE-FX
108 is set to 1/4 with cable < 10m.
111 with cable < 10m.
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| D | adi,adin1110.yaml | 13 The ADIN1110 is a low power single port 10BASE-T1L MAC-
19 switch with integrated 10BASE-T1L PHYs and one serial peripheral
23 10 Mbps single pair Ethernet (SPE).
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| D | ti,dp83869.yaml | 18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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| /Documentation/ABI/testing/ |
| D | debugfs-intel-iommu | 13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
131 Base: 0x10022e000 Head: 20 Tail: 20
145 Base: 0x10026e000 Head: 32 Tail: 32
191 IOMMU: dmar0 Register Base Address: 26be37000
192 <0.1us 0.1us-1us 1us-10us 10us-100us 100us-1ms
195 1ms-10ms >=10ms min(us) max(us) average(us)
200 IOMMU: dmar2 Register Base Address: fed91000
201 <0.1us 0.1us-1us 1us-10us 10us-100us 100us-1ms
[all …]
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| /Documentation/devicetree/bindings/cache/ |
| D | qcom,llcc.yaml | 42 maxItems: 10
46 maxItems: 10
76 - description: LLCC0 base register region
77 - description: LLCC broadcast base register region
93 - description: LLCC0 base register region
94 - description: LLCC1 base register region
95 - description: LLCC2 base register region
96 - description: LLCC3 base register region
97 - description: LLCC4 base register region
98 - description: LLCC5 base register region
[all …]
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
76 Intel(R) SST-BF (feature base-freq) is not supported
88 guaranteed base frequency. Once the user issues a command to use a specific
90 a change in the base frequency dynamically. This feature is called
112 base performance profile (which is performance level 0).
152 enable-cpu-list:0,1,2,3,4,5,6,7,8,9,10,11,12,13,28,29,30,31,32,33,34,35,36,37,38,39,40,41
154 base-frequency(MHz):2600
156 speed-select-base-freq:disabled
168 condition is met, then base frequency of 2600 MHz can be maintained. To
181 enable-cpu-list:0,1,2,3,5,7,8,9,10,11,28,29,30,31,33,35,36,37,38,39
[all …]
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/ |
| D | brg.txt | 11 - clock-frequency : Specifies the base frequency driving
19 reg = <119f0 10 115f0 10>;
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| /Documentation/networking/device_drivers/ethernet/cirrus/ |
| D | cs89x0.rst | 68 computers on 10 Mbps Ethernet networks. The adapters are designed for operation
70 10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5
116 * One available IRQ (5,10,11,or 12 for the CS8900, 3-7,9-15 for CS8920).
118 * Appropriate cable (and connector for AUI, 10BASE-2) for your network
176 IRQ: 10
177 Base I/O Address: 300
178 Memory Base Address: D0000
183 10BASE-T (10BASE-T only adapter)
228 This example loads the module and configures the adapter to use an IO port base
229 address of 200h, interrupt 10, and use the AUI media connection. The following
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | lpc1850-cgu.txt | 5 a base clock and itself is one of the inputs to the two Clock
13 corresponds to one of the base clocks for the LPC18xx.
25 Shall define the base and range of the address space
29 are the base clock numbers defined below.
35 Shall be an ordered list of numbers defining the base clock
41 Which base clocks that are available on the CGU depends on the
42 specific LPC part. Base clocks are numbered from 0 to 27.
45 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
46 1 BASE_USB0_CLK Base clock for USB0
47 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
[all …]
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| /Documentation/devicetree/bindings/dma/ |
| D | stericsson,dma40.yaml | 32 10: Multi-Channel Display Engine MCDE RX
59 37: USB OTG in/out endpoints 2 & 10
117 - description: DMA40 memory base
119 - description: DMA40 memory base
120 - description: LCPA memory base, deprecated, use eSRAM pool instead
127 - const: base
129 - const: base
143 Second phandle is the LCLA (Logical Channel Link base Address) memory.
172 reg-names = "base";
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| /Documentation/networking/device_drivers/ethernet/3com/ |
| D | vortex.rst | 33 - 3c590 Vortex 10Mbps
34 - 3c592 EISA 10Mbps Demon/Vortex
38 - 3c595 Vortex 100base-MII
39 - 3c900 Boomerang 10baseT
40 - 3c900 Boomerang 10Mbps Combo
41 - 3c900 Cyclone 10Mbps TPO
42 - 3c900 Cyclone 10Mbps Combo
43 - 3c900 Cyclone 10Mbps TPC
44 - 3c900B-FL Cyclone 10base-FL
48 - 3c905B Cyclone 10/100/BNC
[all …]
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| /Documentation/admin-guide/device-mapper/ |
| D | snapshot.rst | 105 lvcreate -L 1G -n base volumeGroup
106 lvcreate -L 100M --snapshot -n snap volumeGroup/base
112 volumeGroup-base-real: 0 2097152 linear 8:19 384
115 volumeGroup-base: 0 2097152 snapshot-origin 254:11
118 brw------- 1 root root 254, 11 29 ago 18:15 /dev/mapper/volumeGroup-base-real
121 brw------- 1 root root 254, 10 29 ago 18:14 /dev/mapper/volumeGroup-base
142 volumeGroup-base-real: 0 2097152 linear 8:19 384
143 volumeGroup-base-cow: 0 204800 linear 8:19 2097536
144 volumeGroup-base: 0 2097152 snapshot-merge 254:11 254:12 P 16
147 brw------- 1 root root 254, 11 29 ago 18:15 /dev/mapper/volumeGroup-base-real
[all …]
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,dcc.yaml | 29 - description: DCC base
30 - description: DCC RAM base
40 dma@10a2000{
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,nsp-gpio.txt | 9 GPIO base, IO control registers
33 2. GPIO base pin offset.
34 3 Pin-control base pin offset.
35 4. number of gpio pins which are linearly mapped from pin base.
52 Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)
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| D | mediatek,mt8192-pinctrl.yaml | 36 Physical address base for GPIO base registers. There are 11 GPIO physical
37 address base in mt8192.
42 GPIO base register names.
81 support 2/4/6/8/10/12/14/16mA in mt8192.
82 enum: [2, 4, 6, 8, 10, 12, 14, 16]
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| D | brcm,iproc-gpio.txt | 24 Define the base and range of the I/O address space that contains SoC
50 2. GPIO base pin offset.
51 3 Pin-control base pin offset.
52 4. number of gpio pins which are linearly mapped from pin base.
70 Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)
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| /Documentation/networking/device_drivers/ethernet/wangxun/ |
| D | txgbe.rst | 4 Linux Base Driver for WangXun(R) 10 Gigabit PCI Express Adapters
7 WangXun 10 Gigabit Linux driver.
|
| /Documentation/devicetree/bindings/media/ |
| D | qcom,sdm845-camss.yaml | 64 minItems: 10
65 maxItems: 10
97 $ref: /schemas/graph.yaml#/$defs/port-base
116 $ref: /schemas/graph.yaml#/$defs/port-base
135 $ref: /schemas/graph.yaml#/$defs/port-base
154 $ref: /schemas/graph.yaml#/$defs/port-base
173 minItems: 10
174 maxItems: 10
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| /Documentation/driver-api/media/drivers/ |
| D | radiotrack.rst | 56 The RadioTrack (base) ioport is configurable for 0x30c or 0x20c. Only one
129 Default: BASE <-- 0xc8 (current volume, no stereo detect,
132 Card Off: BASE <-- 0x00 (audio mute, no stereo detect,
135 Card On: BASE <-- 0x00 (see "Card Off", clears any unfinished business)
136 BASE <-- 0xc8 (see "Default")
138 Volume Down: BASE <-- 0x48 (volume down, no stereo detect,
140 wait 10 msec
141 BASE <-- 0xc8 (see "Default")
143 Volume Up: BASE <-- 0x88 (volume up, no stereo detect,
145 wait 10 msec
[all …]
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.yaml | 22 RGB444, YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
54 $ref: /schemas/graph.yaml#/$defs/port-base
80 $ref: /schemas/graph.yaml#/$defs/port-base
103 $ref: /schemas/graph.yaml#/$defs/port-base
113 enum: [6, 7, 8, 10, 12]
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| /Documentation/networking/ |
| D | oa-tc6-framework.rst | 4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
10 The IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
78 10BASE-T1x MAC-PHY Serial Interface Specification,
121 | 10BASE-T1x MAC-PHY Device |
146 transaction protocol specified in the OPEN Alliance 10BASE-T1x MAC-PHY
150 for Ethernet frames specified in the OPEN Alliance 10BASE-T1x MAC-PHY
[all …]
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| /Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.yaml | 26 same hardware "isolation context" and a 10-bit value called an ICID
96 (icid-base,iommu,iommu-base,length).
98 Any ICID i in the interval [icid-base, icid-base + length) is
100 (i - icid-base + iommu-base).
108 (icid-base,gic-its,msi-base,length).
110 Any ICID in the interval [icid-base, icid-base + length) is
112 (i - icid-base + msi-base).
161 reg = <0x0c000000 0x40>, /* MC portal base */
|