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1# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Last Level Cache Controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12description: |
13  LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
14  that can be shared by multiple clients. Clients here are different cores in the
15  SoC, the idea is to minimize the local caches at the clients and migrate to
16  common pool of memory. Cache memory is divided into partitions called slices
17  which are assigned to clients. Clients can query the slice details, activate
18  and deactivate them.
19
20properties:
21  compatible:
22    enum:
23      - qcom,qdu1000-llcc
24      - qcom,sa8775p-llcc
25      - qcom,sc7180-llcc
26      - qcom,sc7280-llcc
27      - qcom,sc8180x-llcc
28      - qcom,sc8280xp-llcc
29      - qcom,sdm845-llcc
30      - qcom,sm6350-llcc
31      - qcom,sm7150-llcc
32      - qcom,sm8150-llcc
33      - qcom,sm8250-llcc
34      - qcom,sm8350-llcc
35      - qcom,sm8450-llcc
36      - qcom,sm8550-llcc
37      - qcom,sm8650-llcc
38      - qcom,x1e80100-llcc
39
40  reg:
41    minItems: 2
42    maxItems: 10
43
44  reg-names:
45    minItems: 2
46    maxItems: 10
47
48  interrupts:
49    maxItems: 1
50
51  nvmem-cells:
52    items:
53      - description: Reference to an nvmem node for multi channel DDR
54
55  nvmem-cell-names:
56    items:
57      - const: multi-chan-ddr
58
59required:
60  - compatible
61  - reg
62  - reg-names
63
64allOf:
65  - if:
66      properties:
67        compatible:
68          contains:
69            enum:
70              - qcom,sc7180-llcc
71              - qcom,sm6350-llcc
72    then:
73      properties:
74        reg:
75          items:
76            - description: LLCC0 base register region
77            - description: LLCC broadcast base register region
78        reg-names:
79          items:
80            - const: llcc0_base
81            - const: llcc_broadcast_base
82
83  - if:
84      properties:
85        compatible:
86          contains:
87            enum:
88              - qcom,sa8775p-llcc
89    then:
90      properties:
91        reg:
92          items:
93            - description: LLCC0 base register region
94            - description: LLCC1 base register region
95            - description: LLCC2 base register region
96            - description: LLCC3 base register region
97            - description: LLCC4 base register region
98            - description: LLCC5 base register region
99            - description: LLCC broadcast base register region
100        reg-names:
101          items:
102            - const: llcc0_base
103            - const: llcc1_base
104            - const: llcc2_base
105            - const: llcc3_base
106            - const: llcc4_base
107            - const: llcc5_base
108            - const: llcc_broadcast_base
109
110  - if:
111      properties:
112        compatible:
113          contains:
114            enum:
115              - qcom,sc7280-llcc
116    then:
117      properties:
118        reg:
119          items:
120            - description: LLCC0 base register region
121            - description: LLCC1 base register region
122            - description: LLCC broadcast base register region
123        reg-names:
124          items:
125            - const: llcc0_base
126            - const: llcc1_base
127            - const: llcc_broadcast_base
128
129  - if:
130      properties:
131        compatible:
132          contains:
133            enum:
134              - qcom,qdu1000-llcc
135              - qcom,sc8180x-llcc
136              - qcom,sc8280xp-llcc
137    then:
138      properties:
139        reg:
140          items:
141            - description: LLCC0 base register region
142            - description: LLCC1 base register region
143            - description: LLCC2 base register region
144            - description: LLCC3 base register region
145            - description: LLCC4 base register region
146            - description: LLCC5 base register region
147            - description: LLCC6 base register region
148            - description: LLCC7 base register region
149            - description: LLCC broadcast base register region
150        reg-names:
151          items:
152            - const: llcc0_base
153            - const: llcc1_base
154            - const: llcc2_base
155            - const: llcc3_base
156            - const: llcc4_base
157            - const: llcc5_base
158            - const: llcc6_base
159            - const: llcc7_base
160            - const: llcc_broadcast_base
161
162  - if:
163      properties:
164        compatible:
165          contains:
166            enum:
167              - qcom,x1e80100-llcc
168    then:
169      properties:
170        reg:
171          items:
172            - description: LLCC0 base register region
173            - description: LLCC1 base register region
174            - description: LLCC2 base register region
175            - description: LLCC3 base register region
176            - description: LLCC4 base register region
177            - description: LLCC5 base register region
178            - description: LLCC6 base register region
179            - description: LLCC7 base register region
180            - description: LLCC broadcast base register region
181            - description: LLCC broadcast AND register region
182        reg-names:
183          items:
184            - const: llcc0_base
185            - const: llcc1_base
186            - const: llcc2_base
187            - const: llcc3_base
188            - const: llcc4_base
189            - const: llcc5_base
190            - const: llcc6_base
191            - const: llcc7_base
192            - const: llcc_broadcast_base
193            - const: llcc_broadcast_and_base
194
195  - if:
196      properties:
197        compatible:
198          contains:
199            enum:
200              - qcom,sdm845-llcc
201              - qcom,sm8150-llcc
202              - qcom,sm8250-llcc
203              - qcom,sm8350-llcc
204    then:
205      properties:
206        reg:
207          items:
208            - description: LLCC0 base register region
209            - description: LLCC1 base register region
210            - description: LLCC2 base register region
211            - description: LLCC3 base register region
212            - description: LLCC broadcast base register region
213        reg-names:
214          items:
215            - const: llcc0_base
216            - const: llcc1_base
217            - const: llcc2_base
218            - const: llcc3_base
219            - const: llcc_broadcast_base
220
221  - if:
222      properties:
223        compatible:
224          contains:
225            enum:
226              - qcom,sm8450-llcc
227              - qcom,sm8550-llcc
228              - qcom,sm8650-llcc
229    then:
230      properties:
231        reg:
232          items:
233            - description: LLCC0 base register region
234            - description: LLCC1 base register region
235            - description: LLCC2 base register region
236            - description: LLCC3 base register region
237            - description: LLCC broadcast OR register region
238            - description: LLCC broadcast AND register region
239        reg-names:
240          items:
241            - const: llcc0_base
242            - const: llcc1_base
243            - const: llcc2_base
244            - const: llcc3_base
245            - const: llcc_broadcast_base
246            - const: llcc_broadcast_and_base
247
248additionalProperties: false
249
250examples:
251  - |
252    #include <dt-bindings/interrupt-controller/arm-gic.h>
253
254    soc {
255        #address-cells = <2>;
256        #size-cells = <2>;
257
258        system-cache-controller@1100000 {
259            compatible = "qcom,sdm845-llcc";
260            reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
261                <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
262                <0 0x01300000 0 0x50000>;
263            reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
264                "llcc3_base", "llcc_broadcast_base";
265            interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
266        };
267    };
268