Searched full:counter (Results 1 – 25 of 330) sorted by relevance
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-counter | 1 What: /sys/bus/counter/devices/counterX/cascade_counts_enable
5 Indicates the cascading of Counts on Counter X.
9 What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select
14 Counter X.
24 What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_available
31 What: /sys/bus/counter/devices/counterX/countY/count
37 What: /sys/bus/counter/devices/counterX/countY/capture
43 What: /sys/bus/counter/devices/counterX/countY/ceiling
48 respective counter.
50 What: /sys/bus/counter/devices/counterX/countY/floor
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| D | sysfs-fs-ubifs | 8 This counter keeps track of the number of accesses of nodes
11 The counter is reset to 0 with a remount.
20 This counter keeps track of the number of accesses of nodes
23 The counter is reset to 0 with a remount.
32 This counter keeps track of the number of accesses of nodes
35 The counter is reset to 0 with a remount.
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| D | sysfs-bus-iio-timer-stm32 | 12 The Counter Enable signal CNT_EN is used
54 | Prescaler +-> | Counter | +-> | Master | TRGO(2)
99 When counting up the counter starts from 0 and fires an
101 When counting down the counter start from preset value
114 Configure the device counter enable modes, in all case
116 attribute and the counter is clocked by the internal clock.
119 Counter is always ON.
140 Configure the device counter trigger mode
142 attribute and the counter is clocked by the connected trigger
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| /Documentation/driver-api/ |
| D | generic-counter.rst | 4 Generic Counter Interface
10 Counter devices are prevalent among a diverse spectrum of industries.
13 resolve the issue of duplicate code found among existing counter device
14 drivers by introducing a generic counter interface for consumption. The
15 Generic Counter interface enables drivers to support and expose a common
16 set of components and functionality present in counter devices.
21 Counter devices can vary greatly in design, but regardless of whether
23 counter devices consist of a core set of components. This core set of
24 components, shared by all counter devices, is what forms the essence of
25 the Generic Counter interface.
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| /Documentation/devicetree/bindings/counter/ |
| D | interrupt-counter.yaml | 4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
7 title: Interrupt counter
13 A generic interrupt counter to measure interrupt frequency. It was developed
22 const: interrupt-counter
46 counter-0 {
47 compatible = "interrupt-counter";
51 counter-1 {
52 compatible = "interrupt-counter";
56 counter-2 {
57 compatible = "interrupt-counter";
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| D | ftm-quaddec.txt | 1 FlexTimer Quadrature decoder counter
3 This driver exposes a simple counter for the quadrature decoder mode.
13 counter0: counter@29d0000 {
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| /Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 7 counters is implemented. This is controlled by the CSV modes programmed in counter
10 Selection of the value for each counter is done via the config registers. There
11 is one register for each counter. Counter 0 is special in that it always counts
13 interrupt is raised. If any other counter overflows, it continues counting, and
43 AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
44 When non-masked bits are matching corresponding AXI_ID bits then counter is
45 incremented. Perf counter is incremented if::
75 extension of AXI ID filter. One improvement is that counter 1-3 has their own
77 improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support
80 Filter is defined with 2 configuration registers per counter 1-3.
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| /Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| D | counters.rst | 21 There are several counter groups based on where the counter is being counted. In
22 addition, each group of counters may have different counter types.
24 These counter groups are based on which component in a networking setup,
99 hardware. The counters are an additional layer to the informative counter set,
102 .. [#accel] Traffic acceleration counter.
123 Ring / Netdev Counter
131 The counter names in the table below refers to both ring and port counters. The
133 notation for port counters doesn't include the [i]. A counter name
137 .. flat-table:: Ring / Software Port Counter Table
140 * - Counter
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 61 description: The frequency of the main counter, in Hz. Should be present
74 where reading certain values from the counter is unreliable. This also
75 affects writes to the tval register, due to the implicit counter read.
80 that reading the counter is unreliable unless the same value is returned
82 to the implicit counter read.
89 the tval registers, due to the implicit counter read.
100 description: The main counter does not tick when the system is in
102 Architecture Reference Manual's specification that the system counter "must
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| D | nxp,sysctr-timer.yaml | 7 title: NXP System Counter Module(sys_ctr)
13 The system counter(sys_ctr) is a programmable system counter
15 etc. it is intended for use in applications where the counter
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| D | fsl,ftm-timer.yaml | 32 - const: ftm-evt-counter-en
33 - const: ftm-src-counter-en
55 clock-names = "ftm-evt", "ftm-src", "ftm-evt-counter-en", "ftm-src-counter-en";
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| D | ti,keystone-timer.txt | 9 It is global timer is a free running up-counter and can generate interrupt
10 when the counter reaches preset counter values.
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| D | ti,da830-timer.yaml | 18 The timer is a free running up-counter and can generate interrupts when the
19 counter reaches preset counter values.
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| D | nxp,tpm-timer.yaml | 15 management applications. The counter, compare and capture registers
17 power modes. TPM can support global counter bus where one TPM drives
18 the counter bus for the others, provided bit width is the same.
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| D | img,pistachio-gptimer.txt | 10 "slow", slow counter clock
11 "fast", fast counter clock
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | counter.txt | 1 OMAP Counter-32K bindings
6 - ti,hwmods: Name of the hwmod associated to the counter, which is typically
11 counter32k: counter@4a304000 {
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| /Documentation/devicetree/bindings/mfd/ |
| D | st,stm32-lptimer.yaml | 14 - Several counter modes:
17 - simple counter from IN1 input signal.
66 counter:
72 const: st,stm32-lptimer-counter
140 counter {
141 compatible = "st,stm32-lptimer-counter";
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| D | st,stm32-timers.yaml | 11 - advanced-control timers consist of a 16-bit auto-reload counter driven
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
16 - basic timers consist of a 16-bit auto-reload counter driven by a
110 counter:
116 const: st,stm32-timer-counter
175 counter {
176 compatible = "st,stm32-timer-counter";
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| /Documentation/w1/slaves/ |
| D | w1_ds2423.rst | 6 * Maxim DS2423 based counter devices.
23 Result of each page is provided as an ASCII output where each counter
26 Each lines will contain the values of 42 bytes read from the counter and
30 a counter value expressed as an integer after c=
35 - 4 bytes for the counter value
40 - c=<int> current counter value
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| /Documentation/arch/arm64/ |
| D | perf.rst | 95 Perf Userspace PMU Hardware Counter Access
126 to the user the hardware counter's index and other necessary data. Using this
138 On heterogeneous systems such as big.LITTLE, userspace PMU counter access can
151 About chained events and counter sizes
154 counter along with userspace access. The sys_perf_event_open syscall will fail
155 if a 64-bit counter is requested and the hardware doesn't support 64-bit
156 counters. Chained events are not supported in conjunction with userspace counter
157 access. If a 32-bit counter is requested on hardware with 64-bit counters, then
158 userspace must treat the upper 32-bits read from the counter as UNKNOWN. The
159 'pmc_width' field in the user page will indicate the valid width of the counter
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| D | amu.rst | 23 system register interface to the counter registers and also supports an
26 Version 1 of the Activity Monitors architecture implements a counter group
29 - CPU cycle counter: increments at the frequency of the CPU.
30 - Constant counter: increments at the fixed frequency of the system
43 Additionally, version 1 implements a counter group of up to 16 auxiliary
72 counter registers. Even if these symptoms are not observed, the values
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| /Documentation/timers/ |
| D | timekeeping.rst | 30 Typically the clock source is a monotonic, atomic counter which will provide
41 the counter register is read in two phases on the bus lowest 16 bits first
42 and the higher 16 bits in a second bus cycle with the counter bits
44 values from the counter.
54 The clock source struct shall provide means to translate the provided counter
72 location, bit width, a parameter telling whether the counter in the
76 Since a 32-bit counter at say 100 MHz will wrap around to zero after some 43
80 code knows when the counter will wrap around and can insert the necessary
115 implementation is not provided, the system jiffy counter will be used as
147 counter to derive a 64-bit nanosecond value, so for example on the ARM
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| /Documentation/hwmon/ |
| D | sl28cpld.rst | 24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
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| /Documentation/devicetree/bindings/watchdog/ |
| D | starfive,jh7100-wdt.yaml | 17 output(WDOGINT) will rise when counter is 0. The counter will reload
18 the timeout value. And then, if counter decreases to 0 again and WDOGINT
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| /Documentation/admin-guide/acpi/ |
| D | cppc_sysfs.rst | 53 * feedback_ctrs : Includes both Reference and delivered performance counter.
54 Reference counter ticks up proportional to processor's reference performance.
55 Delivered counter ticks up proportional to processor's delivered performance.
58 * reference_perf : Performance level at which reference performance counter
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