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/Documentation/userspace-api/media/cec/
Dcec-pin-error-inj.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
9 has low-level support for the CEC bus. Most hardware today will have
10 high-level CEC support where the hardware deals with driving the CEC bus,
19 Currently only the cec-gpio driver (when the CEC line is directly
20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
25 now an ``error-inj`` file.
32 With ``cat error-inj`` you can see both the possible commands and the current
35 $ cat /sys/kernel/debug/cec/cec0/error-inj
36 # Clear error injections:
37 # clear clear all rx and tx error injections
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio-mmio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17 NAND-style parallel busses.
22 - brcm,bcm6345-gpio
[all …]
/Documentation/admin-guide/mm/
Dsoft-dirty.rst2 Soft-Dirty PTEs
5 The soft-dirty is a bit on a PTE which helps to track which pages a task
8 1. Clear soft-dirty bits from the task's PTEs.
15 3. Read soft-dirty bits from the PTEs.
17 This is done by reading from the ``/proc/PID/pagemap``. The bit 55 of the
18 64-bit qword is the soft-dirty one. If set, the respective PTE was
22 Internally, to do this tracking, the writable bit is cleared from PTEs
23 when the soft-dirty bit is cleared. So, after this, when the task tries to
25 the soft-dirty bit on the respective PTE.
28 soft-dirty bits clear, the #PF-s that occur after that are processed fast.
[all …]
/Documentation/ABI/testing/
Dsysfs-bus-acpi72 Bit [0] Set if the device is present.
73 Bit [1] Set if the device is enabled and decoding its
75 Bit [2] Set if the device should be shown in the UI.
76 Bit [3] Set if the device is functioning properly (cleared
78 Bit [4] Set if the battery is present.
82 If bit [0] is clear, then bit 1 must also be clear (a device
85 Bit 0 can be clear (not present) with bit [3] set (device is
95 (RO) Allows users to read the hardware version of non-PCI
97 useful for non-PCI devices because lspci can list the hardware
Dsysfs-firmware-gsmi9 historical reasons this different entry-point has been
15 access to EFI-style variables stored in nvram.
23 See `Documentation/ABI/*/sysfs-firmware-efi-vars`
27 /sys/firmware/gsmi/append_to_eventlog - write-only:
33 platform to platform. The only kernel-enforced
35 32bit host-endian type used as part of the
38 /sys/firmware/gsmi/clear_config - write-only:
46 /sys/firmware/gsmi/clear_eventlog - write-only:
48 This file is used to clear out a portion/the
52 clear. Not all platforms support fractional
Drtc-cdev4 Contact: linux-rtc@vger.kernel.org
6 The ioctl interface to drivers for real-time clocks (RTCs).
37 supported. The value is a bit field of RTC_VL_*, giving the
40 * RTC_VL_CLEAR: Clear the voltage status of the RTC. Some RTCs
42 replaced or charged to be able to clear the status.
48 newer features -- including those enabled by ACPI -- are exposed
Dsysfs-firmware-acpi55 image: The image bitmap. Currently a 32-bit BMP.
93 cause -EINVAL to be returned.
199 Root has permission to clear any of these counters. Eg.::
211 to enable/disable/clear ACPI interrupts in user space, which can be
237 * this is because the status bit is set even if the enable
238 * bit is cleared, and it triggers an ACPI fixed event when
239 * the enable bit is set again
246 # echo clear > ff_pwr_btn /* clear the status bit */
/Documentation/
Datomic_bitops.txt5 While our bitmap_{}() functions are non-atomic, we have a number of operations
10 ---
12 The single bit operations are:
14 Non-RMW ops:
20 {set,clear,change}_bit()
25 test_and_{set,clear,change}_bit()
33 All RMW atomic operations have a '__' prefixed variant which is non-atomic.
37 ---------
39 Non-atomic ops:
47 The test_and_{}_bit() operations return the original value of the bit.
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Darm,versatile-fpga-irq.txt9 - compatible: "arm,versatile-fpga-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
14 - reg: The register bank for the FPGA interrupt controller.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
17 - valid-mask: a u32 number representing a bit mask determining which of
22 The "oxsemi,ox810se-rps-irq" compatible is deprecated.
27 compatible = "arm,versatile-fpga-irq";
28 #interrupt-cells = <1>;
29 interrupt-controller;
[all …]
Darm,vic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
15 be nested or have the outputs wire-OR'd together.
18 - $ref: /schemas/interrupt-controller.yaml#
23 - arm,pl190-vic
24 - arm,pl192-vic
25 - arm,versatile-vic
[all …]
Dbrcm,bcm7120-l2-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
19 - outputs multiple interrupts signals towards its interrupt controller parent
21 - controls how some of the interrupts will be flowing, whether they will
26 - has one 32-bit enable word and one 32-bit status word
[all …]
/Documentation/virt/kvm/x86/
Dmsr.rst1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
16 ---------------
24 4-byte alignment physical address of a memory area which must be
42 An odd version indicates an in-progress update.
53 Note that although MSRs are per-CPU entities, the effect of this
56 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
63 4-byte aligned physical address of a memory area which must be in
64 guest RAM, plus an enable bit in bit 0. This memory is expected to hold
80 updates of this structure is arbitrary and implementation-dependent.
[all …]
/Documentation/arch/powerpc/
Ddexcr.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
11 PowerPC ISA 3.1B (Power10) that allows per-cpu control over several dynamic
13 branch target prediction) and enabling return-oriented programming (ROP)
24 A hypervisor-privileged SPR that can control aspects for the hypervisor and
27 An optional ultravisor-privileged SPR that can control aspects for the ultravisor.
30 provides a non-privileged read-only view of the userspace DEXCR aspects.
31 There is also an SPR that provides a read-only view of the hypervisor enforced
40 -----
52 .. flat-table::
53 :header-rows: 1
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/Documentation/admin-guide/hw-vuln/
Dtsx_async_abort.rst1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
11 -------------------
14 Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)
15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
23 ------------
28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
[all …]
Dprocessor_mmio_stale_data.rst5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
24 read into an architectural, software-visible state or sampled from a buffer or
28 -----------------------------------------
29 Stale data may propagate from fill buffers (FB) into the non-coherent portion
30 of the uncore on some non-coherent writes. Fill buffer propagation by itself
35 -------------------------------------
38 shared by all client cores. For non-coherent reads that go to sideband
45 ------------------------------------
55 Device Register Partial Write (DRPW) (CVE-2022-21166)
56 -----------------------------------------------------
[all …]
Dreg-file-data-sampling.rst6 only affects Intel Atom parts(also branded as E-cores). RFDS may allow
9 ability to choose which data is inferred. CVE-2023-28746 is assigned to RFDS.
42 Intel released a microcode update that enables software to clear sensitive
44 mitigation strategy to force the CPU to clear the affected buffers before an
51 -----------------
54 at C-state transitions.
57 ----------------------------------
62 - Bit 27 - RFDS_NO - When set, processor is not affected by RFDS.
63 - Bit 28 - RFDS_CLEAR - When set, processor is affected by RFDS, and has the
67 ---------------------------------------------
[all …]
/Documentation/arch/parisc/
Ddebugging.rst2 PA-RISC Debugging
5 okay, here are some hints for debugging the lower-level parts of
22 When real-mode code tries to access non-existent memory, you'll get
26 the I/O range); the System Responder address is the address real-mode
31 get translated to a physical address before real-mode code tried to
35 3. Q bit fun
38 Certain, very critical code has to clear the Q bit in the PSW. What
39 happens when the Q bit is cleared is the CPU does not update the
41 was interrupted - so if you get an interruption between the instruction
42 that clears the Q bit and the RFI that sets it again you don't know
[all …]
/Documentation/devicetree/bindings/edac/
Dsocfpga-eccmgr.txt3 The ECC Manager counts and corrects single bit errors and counts/handles
4 double bit errors which are uncorrectable.
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
24 - compatible : Should be "altr,socfpga-ocram-ecc"
[all …]
/Documentation/filesystems/ext4/
Dbigalloc.rst1 .. SPDX-License-Identifier: GPL-2.0
4 --------
7 supported page size on most MMU-capable hardware. This is fortunate, as
15 use clustered allocation, so that each bit in the ext4 block allocation
17 file system is mainly going to be storing large files in the 4-32
19 This means that each bit in the block allocation bitmap now addresses
32 not clear where those patches went-- they eventually morphed into
/Documentation/admin-guide/
Dvga-softcursor.rst9 tricks: you can make your cursor look like a non-blinking red block,
40 on highlight (or sometimes blinking -- it depends on the configuration
46 Bit setting takes place before bit toggling, so you can simply clear a
47 bit by including it in both the set mask and the toggle mask.
50 --------
54 echo -e '\033[?2c'
58 echo -e '\033[?6c'
60 To get red non-blinking block, use::
62 echo -e '\033[?17;0;64c'
/Documentation/devicetree/bindings/reset/
Dbrcm,brcmstb-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB SW_INIT-style reset controller
10 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
11 SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
18 - Florian Fainelli <f.fainelli@gmail.com>
22 const: brcm,brcmstb-reset
27 "#reset-cells":
[all …]
/Documentation/locking/
Drobust-futex-ABI.rst43 consisting of three words. Each word is 32 bits on 32 bit arch's, or 64
44 bits on 64 bit arch's, and local byte order. Each thread should have
47 If a thread is running in 32 bit compatibility mode on a 64 native arch
48 kernel, then it can actually have two such structures - one using 32 bit
49 words for 32 bit compatibility mode, and one using 64 bit words for 64
50 bit native mode. The kernel, if it is a 64 bit kernel supporting 32 bit
63 is always a 32 bit word, unlike the other words above. The 'lock
79 The 'lock word' is always 32 bits, and is intended to be the same 32 bit
89 the kernel will walk this list, mark any such locks with a bit
146 4) clear the 'list_op_pending' word.
[all …]
/Documentation/process/
Dbotching-up-ioctls.rst5 From: https://blog.ffwll.ch/2013/11/botching-up-ioctls.html
9 One clear insight kernel graphics hackers gained in the past few years is that
13 Which is nice, since there's no more insanity in the form of fake-generic, but
14 actually only used once interfaces. But the clear downside is that there's much
19 only cover technicalities and not the big-picture issues like what the command
25 -------------
28 will need to add a 32-bit compat layer:
33 * Align everything to the natural size and use explicit padding. 32-bit
34 platforms don't necessarily align 64-bit values to 64-bit boundaries, but
35 64-bit platforms do. So we always need padding to the natural size to get
[all …]
/Documentation/misc-devices/
Dapds990x.rst1 .. SPDX-License-Identifier: GPL-2.0
17 -----------
23 ALS produces raw measurement values for two channels: Clear channel
25 using clear channel only. Lux value and the threshold level on the HW
41 Proximity side is little bit simpler. There is no need for complex conversions.
48 -----
52 RO - shows detected chip type and version
55 RW - enable / disable chip. Uses counting logic
60 RO - measured lux value
65 RO - lux0_input max value.
[all …]
/Documentation/hwmon/
Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
[all …]

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