Searched +full:cpu +full:- +full:core (Results 1 – 25 of 583) sorted by relevance
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| /Documentation/arch/x86/ |
| D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - topology_num_threads_per_package()
54 - topology_num_cores_per_package()
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
17 The bottom hierarchy level sits at core or thread level depending on whether
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
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| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
20 from simple wfi to power gating) according to OS PM policies. The CPU states
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| /Documentation/devicetree/bindings/regulator/ |
| D | nvidia,tegra-regulators-coupling.txt | 4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
13 and they both shall be higher than the CPU voltage by at least 120mV.
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
20 voltage shall be higher than the CPU by N mV, where N depends on the CPU
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 collection of features that give more granular control over CPU performance.
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
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| D | cpufreq.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 CPU Performance Scaling
15 The Concept of CPU Performance Scaling
20 Operating Performance Points or P-states (in ACPI terminology). As a rule,
22 can be retired by the CPU over a unit of time, but also the higher the clock
24 time (or the more power is drawn) by the CPU in the given P-state. Therefore
25 there is a natural tradeoff between the CPU capacity (the number of instructions
26 that can be executed over a unit of time) and the power drawn by the CPU.
29 as possible and then there is no reason to use any P-states different from the
30 highest one (i.e. the highest-performance frequency/voltage configuration
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| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 .. |cpufreq| replace:: :doc:`CPU Performance Scaling <cpufreq>`
8 CPU Idle Time Management
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
33 CPU idle time management operates on CPUs as seen by the *CPU scheduler* (that
37 software as individual single-core processors. In other words, a CPU is an
43 program) at a time, it is a CPU. In that case, if the hardware is asked to
46 Second, if the processor is multi-core, each core in it is able to follow at
52 enter an idle state, that applies to the core that asked for it in the first
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| D | intel_idle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 ``intel_idle`` CPU Idle Time Management Driver
17 :doc:`CPU idle time management subsystem <cpuidle>` in the Linux kernel
18 (``CPUIdle``). It is the default CPU idle time management driver for the
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
27 logical CPU executing it is idle and so it may be possible to put some of the
28 processor's functional blocks into low-power states. That instruction takes two
29 arguments (passed in the ``EAX`` and ``ECX`` registers of the target CPU), the
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
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| /Documentation/ABI/stable/ |
| D | sysfs-devices-system-cpu | 1 What: /sys/devices/system/cpu/dscr_default
2 Date: 13-May-2014
6 /sys/devices/system/cpu/cpuN/dscr on all CPUs.
9 all per-CPU defaults at the same time.
12 What: /sys/devices/system/cpu/cpu[0-9]+/dscr
13 Date: 13-May-2014
17 a CPU.
22 on any CPU where it executes (overriding the value described
27 What: /sys/devices/system/cpu/cpuX/topology/physical_package_id
33 What: /sys/devices/system/cpu/cpuX/topology/die_id
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| /Documentation/hwmon/ |
| D | peci-cputemp.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
3 Kernel driver peci-cputemp
9 Intel Xeon E5-14xx v3 family
10 Intel Xeon E5-24xx v3 family
11 Intel Xeon E5-16xx v3 family
12 Intel Xeon E5-26xx v3 family
13 Intel Xeon E5-46xx v3 family
14 Intel Xeon E7-48xx v3 family
15 Intel Xeon E7-88xx v3 family
17 Intel Xeon E5-16xx v4 family
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| D | k8temp.rst | 19 -----------
23 from revision F of K8 core, but in fact it seems to be implemented for all
24 revisions of K8 except the first two revisions (SH-B0 and SH-B3).
26 Please note that you will need at least lm-sensors 2.10.1 for proper userspace
29 There can be up to four temperature sensors inside single CPU. The driver
30 will auto-detect the sensors and will display only temperatures from
36 temp1_input temperature of Core 0 and "place" 0
37 temp2_input temperature of Core 0 and "place" 1
38 temp3_input temperature of Core 1 and "place" 0
39 temp4_input temperature of Core 1 and "place" 1
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| D | asus_wmi_sensors.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
7 * PRIME X399-A,
8 * PRIME X470-PRO,
11 * ROG CROSSHAIR VI HERO (WI-FI AC),
13 * ROG CROSSHAIR VII HERO (WI-FI),
14 * ROG STRIX B450-E GAMING,
15 * ROG STRIX B450-F GAMING,
16 * ROG STRIX B450-I GAMING,
17 * ROG STRIX X399-E GAMING,
18 * ROG STRIX X470-F GAMING,
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| /Documentation/devicetree/bindings/x86/ |
| D | ce4100.txt | 2 ---------------------------
4 The CE4100 SoC uses for in core peripherals the following compatible
5 format: <vendor>,<chip>-<device>.
10 The CPU nodes
11 -------------
14 #address-cells = <1>;
15 #size-cells = <0>;
17 cpu@0 {
18 device_type = "cpu";
23 cpu@2 {
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 4 representation of a Nios II Processor Core.
11 - compatible: Compatible property value should be "altr,nios2-1.0".
12 - reg: Contains CPU index.
13 - interrupt-controller: Specifies that the node is an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
17 - dcache-line-size: Contains data cache line size.
18 - icache-line-size: Contains instruction line size.
19 - dcache-size: Contains data cache size.
20 - icache-size: Contains instruction cache size.
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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| /Documentation/devicetree/bindings/mips/img/ |
| D | xilfpga.txt | 4 Under the Imagination University Program, a microAptiv UP core has been
7 As we are dealing with a MIPS core instantiated on an FPGA, specifications
14 the ARTIX-7 FPGA by Xilinx.
18 - microAptiv UP core m14Kc
19 - 50MHz clock speed
20 - 128Mbyte DDR RAM at 0x0000_0000
21 - 8Kbyte RAM at 0x1000_0000
22 - axi_intc at 0x1020_0000
23 - axi_uart16550 at 0x1040_0000
24 - axi_gpio at 0x1060_0000
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | brcm,dpfe-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/brcm,dpfe-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Markus Mayer <mmayer@broadcom.com>
16 - enum:
17 - brcm,bcm7271-dpfe-cpu
18 - brcm,bcm7268-dpfe-cpu
19 - const: brcm,dpfe-cpu
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
9 1 = cpuclk (CPU clock)
16 1 = cpuclk (CPU clock)
22 1 = cpuclk (CPU clock)
28 1 = cpuclk (CPU clock)
36 1 = cpuclk (CPU clock)
52 - compatible : shall be one of the following:
53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,lpass-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,lpass-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc. LPASS CPU dai driver
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Rohit kumar <quic_rohkumar@quicinc.com>
14 Qualcomm Technologies Inc. SOC Low-Power Audio SubSystem (LPASS) that consist
15 of MI2S interface for audio data transfer on external codecs. LPASS cpu driver
16 is a module to configure Low-Power Audio Interface(LPAIF) core registers
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| D | test-component.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/test-component.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 - test-cpu
16 - test-cpu-verbose
17 - test-cpu-verbose-dai
18 - test-cpu-verbose-component
19 - test-codec
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,saw2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 power-controller that transitions a piece of hardware (like a processor or
27 - enum:
28 - qcom,ipq4019-saw2-cpu
29 - qcom,ipq4019-saw2-l2
30 - qcom,ipq8064-saw2-cpu
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| /Documentation/networking/ |
| D | scaling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-cpu-debug.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CoreSight CPU Debug Component
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight CPU debug component are compliant with the ARMv8 architecture
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| /Documentation/scheduler/ |
| D | sched-bwc.rst | 6 This document only discusses CPU bandwidth control for SCHED_NORMAL.
7 The SCHED_RT case is covered in Documentation/scheduler/sched-rt-group.rst
10 specification of the maximum CPU bandwidth available to a group or hierarchy.
14 microseconds of CPU time. That quota is assigned to per-cpu run queues in
22 is transferred to cpu-local "silos" on a demand basis. The amount transferred
26 -------------
30 Traditional (UP-EDF) bandwidth control is something like:
64 there many cgroups or CPU is under utilized, the interference is
66 https://lore.kernel.org/lkml/5371BD36-55AE-4F71-B9D7-B86DC32E3D2B@linux.alibaba.com/
69 ----------
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
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