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/Documentation/devicetree/bindings/net/
Dxlnx,gmii-to-rgmii.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Harini Katakam <harini.katakam@amd.com>
13 The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
17 The Management Data Input/Output (MDIO) interface is used to configure the
24 const: xlnx,gmii-to-rgmii-1.0
31 phy-handle:
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Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
24 IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
34 nvmem-cells:
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Dti,cpsw-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
16 gigabit media independent interface (GMII),reduced gigabit media
17 independent interface (RGMII), reduced media independent interface (RMII),
18 the management data input output (MDIO) for physical layer device (PHY)
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/Documentation/devicetree/bindings/mailbox/
Damlogic,meson-gxbb-mhu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson Message-Handling-Unit Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
15 that has 3 independent channels/links to communicate with remote processor(s).
17 received data. However, there is no specified way of knowing if the sent
18 data has been read by the remote. This driver assumes the sender polls
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Darm,mhu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
14 independent channels/links to communicate with remote processor(s). MHU links
15 are hardwired on a platform. A link raises interrupt for any received data.
16 However, there is no specified way of knowing if the sent data has been read
18 remote clears it after having read the data. The last channel is specified to
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
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/Documentation/devicetree/bindings/mmc/
Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
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/Documentation/bpf/
Dringbuf.rst12 ----------
18 - more efficient memory utilization by sharing ring buffer across CPUs;
19 - preserving ordering of events that happen sequentially in time, even across
22 These two problems are independent, but perf buffer fails to satisfy both.
23 Both are a result of a choice to have per-CPU perf ring buffer. Both can be
25 problem could technically be solved for perf buffer with some in-kernel
30 ------------------
56 The approach chosen has an advantage of re-using existing BPF map
62 combined with ``ARRAY_OF_MAPS`` and ``HASH_OF_MAPS`` map-in-maps to implement
75 - variable-length records;
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/Documentation/driver-api/media/
Ddtv-demux.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ---------------------
9 The Kernel Digital TV Demux kABI defines a driver-internal interface for
10 registering low-level, hardware specific driver to a hardware independent
20 Each demux receives its TS input from a DVB front-end or from memory, as
21 set via this demux kABI. In a system with more than one front-end, the kABI
22 can be used to select one of the DVB front-ends as a TS source for a demux,
25 The demux kABI only controls front-ends regarding to their connections with
26 demuxes; the kABI used to set the other front-end parameters, such as
37 Whenever the functions of the demux API modify shared data, the
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/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
86 Display Data Channel
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
114 DisplayPort Configuration Data
150 Independent Software Vendor
189 Output Data Mapping
216 Scalable Data Port
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Ddcn-overview.rst10 .. kernel-figure:: dc_pipeline_overview.svg
16 Data Port (SDP) and DCN. This component has multiple features, such as memory
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
20 processing such as color space conversion, linearization of pixel data, tone
24 multiple planes, using global or per-pixel alpha.
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
43 the Display Micro-Controller Unit - version B (DMCUB), which is handled via
53 pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see
54 the SDP as the element from our Data Fabric that feeds the display pipe.
66 1. Pixel data interface (red): Represents the pixel data flow;
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/Documentation/admin-guide/perf/
Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
13 is independent of others to service system memory requests. And one DDR5
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
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Dhisi-pmu.rst5 The HiSilicon SoC chip includes various independent system device PMUs
7 independent and have hardware logic to gather statistics and performance
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
16 -------------------------------
27 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
28 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
44 ------------------------------------------
46 ------------------------------------------
48 ------------------------------------------
50 ------------------------------------------
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/Documentation/devicetree/bindings/cpufreq/
Dbrcm,stb-avs-cpu-freq.txt4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
22 Node brcm,avs-cpu-data-mem
23 --------------------------
26 - compatible: must include: brcm,avs-cpu-data-mem and
27 should include: one of brcm,bcm7271-avs-cpu-data-mem or
28 brcm,bcm7268-avs-cpu-data-mem
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/Documentation/crypto/
Ddescore-readme.rst1 .. SPDX-License-Identifier: GPL-2.0
13 ------------------------------------------------------------------------------
15 des - fast & portable DES encryption & decryption.
42 2. PORTABILITY to any byte-addressable host with a 32bit unsigned C type
43 3. Plug-compatible replacement for KERBEROS's low-level routines.
46 register-starved machines. My discussions with Richard Outerbridge,
51 up in a parameterized fashion so it can easily be modified by speed-daemon
58 compile on a SPARCStation 1 (cc -O4, gcc -O2):
60 this code (byte-order independent):
62 - 30us per encryption (options: 64k tables, no IP/FP)
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/Documentation/devicetree/
Dof_unittest.rst1 .. SPDX-License-Identifier: GPL-2.0
12 This document explains how the test data required for executing OF unittest
13 is attached to the live tree dynamically, independent of the machine's
18 (1) Documentation/devicetree/usage-model.rst
23 from the unflattened device tree data structure. This interface is used by
32 kernel code as a result of intentionally bad unittest data. This has led
34 of a test or whether there is a real problem that is independent of unittest.
45 from 'scripts/dtc/of_unittest_expect --help'.
48 3. Test-data
51 The Device Tree Source file (drivers/of/unittest-data/testcases.dts) contains
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/Documentation/driver-api/iio/
Dtriggers.rst6 * :c:func:`devm_iio_trigger_alloc` — Resource-managed iio_trigger_alloc
7 * :c:func:`devm_iio_trigger_register` — Resource-managed iio_trigger_register
12 In many situations it is useful for a driver to be able to capture data based
13 on some external event (trigger) as opposed to periodically polling for data.
15 based on hardware generated events (e.g. data ready or threshold exceeded) or
16 provided by a separate driver from an independent interrupt source (e.g. GPIO
18 a specific file in sysfs). A trigger may initiate data capture for a number of
55 trig = iio_trigger_alloc(dev, "trig-%s-%d", name, idx);
58 trig->ops = &trigger_ops;
76 .. kernel-doc:: include/linux/iio/trigger.h
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/Documentation/filesystems/
Dceph.rst1 .. SPDX-License-Identifier: GPL-2.0
15 * N-way replication of data across storage nodes
17 * Automatic rebalancing of data on node addition/removal
27 separates data and metadata management into independent server
29 storage nodes run entirely as user space daemons. File data is striped
31 facilitate high throughputs. When storage nodes fail, data is
32 re-replicated in a distributed fashion by the storage nodes themselves
37 in-memory cache above the file namespace that is extremely scalable,
39 and can tolerate arbitrary (well, non-Byzantine) node failures. The
46 independent metadata servers, allowing scalable concurrent access.
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/Documentation/driver-api/soundwire/
Derror_handling.rst13 1. Bus clash or parity errors: This mechanism relies on low-level detectors
14 that are independent of the payload and usages, and they cover both control
15 and audio data. The current implementation only logs such errors.
19 data enabled by the SoundWire protocol, the location of the error will also
20 impact its audibility (most-significant bits will be more impacted in PCM),
31 covers transmission of the data between devices. The ACK status indicates
34 be applied. In case of a bad programming (command sent to non-existent
35 Slave or to a non-implemented register) or electrical issue, no response
40 reset and re-enumerate all devices.
47 driver will return a -ETIMEOUT. Such timeouts are symptoms of a faulty
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/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
24 0x2: Source address pointer is incremented after each data transfer
25 0x3: Source address pointer is decremented after each data transfer
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/Documentation/userspace-api/gpio/
Dgpio-get-lineinfo-watch-ioctl.rst1 .. SPDX-License-Identifier: GPL-2.0
11 gpio-v2-get-lineinfo-watch-ioctl.rst.
16 GPIO_GET_LINEINFO_WATCH_IOCTL - Enable watching a line for changes to its
49 The line must be requested using gpio-get-linehandle-ioctl.rst or
50 gpio-get-lineevent-ioctl.rst to access its value, and the line event can
51 monitor a line for events using gpio-lineevent-data-read.rst.
59 gpio-lineinfo-changed-read.rst.
63 Watches are specific to the ``chip_fd`` and are independent of watches
73 On error -1 and the ``errno`` variable is set appropriately.
74 Common error codes are described in error-codes.rst.
/Documentation/devicetree/bindings/input/
Dfsl,mpr121-touchkey.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/fsl,mpr121-touchkey.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Torokhov <dmitry.torokhov@gmail.com>
13 The MPR121 supports up to 12 completely independent electrodes/capacitance
15 https://www.nxp.com/docs/en/data-sheet/MPR121.pdf
18 - $ref: input.yaml#
21 - required: [ interrupts ]
22 - required: [ poll-interval ]
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/Documentation/firmware-guide/acpi/dsd/
Dgraph.rst1 .. SPDX-License-Identifier: GPL-2.0
10 _DSD (Device Specific Data) [dsd-guide] is a predefined ACPI device
14 for graphs: property [dsd-guide] and hierarchical data extensions. The
15 property extension provides generic key-value pairs whereas the
16 hierarchical data extension supports nodes with references to other
19 a tree-like structure with zero or more properties (key-value pairs)
22 The data structure may be accessed at runtime by using the device_*
25 Fwnode represents a generic firmware node object. It is independent on
26 the firmware type. In ACPI, fwnodes are _DSD hierarchical data
30 The data structure may be referenced to elsewhere in the ACPI tables
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/Documentation/devicetree/bindings/dma/
Dst_fdma.txt3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
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/Documentation/power/
Dcharger-manager.rst7 Charger Manager provides in-kernel battery charger management that
8 requires temperature monitoring during suspend-to-RAM state
12 Charger Manager is a platform_driver with power-supply-class entries.
13 An instance of Charger Manager (a platform-device created with Charger-Manager)
14 represents an independent battery with chargers. If there are multiple
26 own power-supply-class and each power-supply-class can provide
28 aggregates charger-related information from multiple sources and
29 shows combined information as a single power-supply-class.
31 * Support for in suspend-to-RAM polling (with suspend_again callback)
32 While the battery is being charged and the system is in suspend-to-RAM,
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/Documentation/devicetree/bindings/media/i2c/
Dadv748x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kieran Bingham <kieran.bingham@ideasonboard.com>
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
15 HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
21 - enum:
22 - adi,adv7481
23 - adi,adv7482
29 The ADV748x has up to twelve 256-byte maps that can be accessed via the
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