| /drivers/gpu/drm/bridge/ |
| D | sil-sii8620.h | 15 /* Vendor ID Low byte, default value: 0x01 */
18 /* Vendor ID High byte, default value: 0x00 */
21 /* Device ID Low byte, default value: 0x60 */
24 /* Device ID High byte, default value: 0x86 */
27 /* Device Revision, default value: 0x10 */
30 /* OTP DBYTE510, default value: 0x00 */
33 /* System Control #1, default value: 0x00 */
44 /* System Control DPD, default value: 0x90 */
54 /* Dual link Control, default value: 0x00 */
65 /* PWD Software Reset, default value: 0x20 */
[all …]
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| /drivers/clk/mediatek/ |
| D | Kconfig | 25 default ARCH_MEDIATEK && ARM
81 default ARCH_MEDIATEK && ARM64
131 default ARCH_MEDIATEK && ARM64
217 default ARCH_MEDIATEK && ARM64
274 default ARCH_MEDIATEK
282 default COMMON_CLK_MT6795
289 default COMMON_CLK_MT6795
296 default COMMON_CLK_MT6795
303 default COMMON_CLK_MT6795
311 default ARCH_MEDIATEK && ARM64
[all …]
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| /drivers/media/dvb-frontends/ |
| D | Kconfig | 18 default m if !MEDIA_SUBDRV_AUTOSELECT
25 default m if !MEDIA_SUBDRV_AUTOSELECT
34 default m if !MEDIA_SUBDRV_AUTOSELECT
42 default m if !MEDIA_SUBDRV_AUTOSELECT
50 default m if !MEDIA_SUBDRV_AUTOSELECT
58 default m if !MEDIA_SUBDRV_AUTOSELECT
67 default m if !MEDIA_SUBDRV_AUTOSELECT
74 default m if !MEDIA_SUBDRV_AUTOSELECT
86 default m if !MEDIA_SUBDRV_AUTOSELECT
96 default m if !MEDIA_SUBDRV_AUTOSELECT
[all …]
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| /drivers/gpu/drm/meson/ |
| D | meson_dw_hdmi.h | 12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
19 * Default 1.
22 * Default 1.
24 * Default 1.
26 * 0=Release from reset. Default 1.
28 * 0=Release from reset. Default 1.
34 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
[all …]
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| D | meson_dw_mipi_dsi.h | 12 /* [31: 4] Reserved. Default 0.
13 * [3] RW timing_rst_n: Default 1.
15 * [2] RW dpi_rst_n: Default 1.
17 * [1] RW intr_rst_n: Default 1.
19 * [0] RW dwc_rst_n: Default 1.
29 /* [31: 5] Reserved. Default 0.
30 * [4] RW manual_edpihalt: Default 0.
32 * [3] RW auto_edpihalt_en: Default 0.
35 * [2] RW clock_freerun: Apply to auto-clock gate only. Default 0.
36 * 0=Default, use auto-clock gating to save power;
[all …]
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| /drivers/media/tuners/ |
| D | Kconfig | 6 default y
30 default m if !MEDIA_SUBDRV_AUTOSELECT
37 default m if !MEDIA_SUBDRV_AUTOSELECT
44 default m if !MEDIA_SUBDRV_AUTOSELECT
51 default m if !MEDIA_SUBDRV_AUTOSELECT
59 default m if !MEDIA_SUBDRV_AUTOSELECT
67 default m if !MEDIA_SUBDRV_AUTOSELECT
75 default m if !MEDIA_SUBDRV_AUTOSELECT
82 default m if !MEDIA_SUBDRV_AUTOSELECT
89 default m if !MEDIA_SUBDRV_AUTOSELECT
[all …]
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| /drivers/pinctrl/mediatek/ |
| D | Kconfig | 10 default y if PINCTRL_MTK || PINCTRL_MTK_MOORE
11 default PINCTRL_MTK_PARIS
54 default SOC_MT7620
61 default SOC_MT7621
68 default SOC_MT7620
75 default SOC_RT288X
82 default SOC_RT305X
89 default SOC_RT3883
97 default MACH_MT2701
104 default MACH_MT7623
[all …]
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| /drivers/pinctrl/sunxi/ |
| D | Kconfig | 16 default MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
21 default MACH_SUN5I
26 default MACH_SUN6I
31 default MACH_SUN6I
36 default MACH_SUN8I
41 default MACH_SUN8I
46 default MACH_SUN8I
51 default MACH_SUN8I
56 default MACH_SUN8I
61 default MACH_SUN8I
[all …]
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| /drivers/gpu/drm/xe/ |
| D | Kconfig.profile | 2 int "Default max job timeout (ms)"
3 default 10000 # milliseconds
5 Configures the default max job timeout after which job will
8 int "Default min job timeout (ms)"
9 default 1 # milliseconds
11 Configures the default min job timeout after which job will
14 int "Default max timeslice duration (us)"
15 default 10000000 # microseconds
17 Configures the default max timeslice duration between multiple
20 int "Default min timeslice duration (us)"
[all …]
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| /drivers/clk/sunxi-ng/ |
| D | Kconfig | 6 default ARCH_SUNXI
12 default y
17 default y
22 default y
27 default y
32 default y
37 default y
42 default y
47 default y
52 default y
[all …]
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| /drivers/staging/media/ipu3/include/uapi/ |
| D | intel-ipu3.h | 49 * Default 2.
125 * @grid: &ipu3_uapi_grid_config, the default grid resolution is 16x16 cells.
127 * The threshold is a saturation measure range [0, 8191], 8191 is default.
175 * @width: Grid horizontal dimensions. Value: [16, 32], default 16.
176 * @height: Grid vertical dimensions. Value: [16, 24], default 16.
179 * default is 3 (cell size 8x8), 4 cell per grid.
185 * @x_start: X value of top left corner of ROI, default 0.
186 * @y_start: Y value of top left corner of ROI, default 0.
238 * @gain_gr: WB gain factor for the gr channels. Default 256.
239 * @gain_r: WB gain factor for the r channel. Default 256.
[all …]
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc.h | 117 default: in DISPC_DEFAULT_COLOR()
134 default: in DISPC_TRANS_COLOR()
152 default: in DISPC_TIMING_H()
170 default: in DISPC_TIMING_V()
188 default: in DISPC_POL_FREQ()
206 default: in DISPC_DIVISORo()
224 default: in DISPC_SIZE_MGR()
242 default: in DISPC_DATA_CYCLE1()
260 default: in DISPC_DATA_CYCLE2()
278 default: in DISPC_DATA_CYCLE3()
[all …]
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | dispc.h | 120 default: in DISPC_DEFAULT_COLOR()
137 default: in DISPC_TRANS_COLOR()
155 default: in DISPC_TIMING_H()
173 default: in DISPC_TIMING_V()
191 default: in DISPC_POL_FREQ()
209 default: in DISPC_DIVISORo()
227 default: in DISPC_SIZE_MGR()
245 default: in DISPC_DATA_CYCLE1()
263 default: in DISPC_DATA_CYCLE2()
281 default: in DISPC_DATA_CYCLE3()
[all …]
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| /drivers/gpu/drm/i915/display/ |
| D | intel_display_params.c | 31 "DMC firmware path to use instead of the default one. "
39 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
43 "(default: auto from VBT)");
47 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
51 "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
55 "Enable display page table (DPT) (default: true)");
58 "Enable display state buffer (DSB) (default: true)");
61 "Enable system agent voltage/frequency scaling (SAGV) (default: true)");
65 "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)");
67 intel_display_param_named_unsafe(enable_ips, bool, 0400, "Enable IPS (default: true)");
[all …]
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| /drivers/irqchip/ |
| D | Kconfig | 22 default 2 if ARCH_REALVIEW
23 default 1
46 default ARM_GIC_V3
52 default ARM_GIC_V3_ITS
65 default 4 if ARCH_S5PV210
66 default 2
122 default ARCH_BRCMSTB || BMIPS_GENERIC
130 default ARCH_BRCMSTB || BMIPS_GENERIC
137 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
199 default y
[all …]
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| /drivers/reset/ |
| D | Kconfig | 7 default y if ARCH_HAS_RESET_CONTROLLER
27 default ATH79
34 default ARC_PLAT_AXS10X
41 default BMIPS_GENERIC
48 default m if ARCH_BERLIN
55 default ARCH_BRCMSTB || ARCH_BCM2835
64 default ARCH_BRCMSTB || ARCH_BCM2835
73 default MACH_EYEQ5 || MACH_EYEQ6H
103 default y if SOC_IMX7D
112 default CLK_IMX8MP
[all …]
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| /drivers/clk/rockchip/ |
| D | Kconfig | 7 default ARCH_ROCKCHIP
15 default y
22 default y
29 default y
36 default y
43 default y
50 default y
57 default y
64 default y
71 default y
[all …]
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| /drivers/char/hw_random/ |
| D | Kconfig | 8 default m
31 the default FPGA bitstream on the TS-7800 has such functionality.
41 default HW_RANDOM
55 default HW_RANDOM
68 default HW_RANDOM
92 default HW_RANDOM
105 default HW_RANDOM
119 default HW_RANDOM
132 default HW_RANDOM
145 default HW_RANDOM
[all …]
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| /drivers/net/ethernet/ibm/emac/ |
| D | Kconfig | 15 default "128"
20 default "64"
25 default "32"
30 default "256"
35 default n
42 default n
46 default n
50 default n
54 default n
58 default n
[all …]
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| /drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_2/ |
| D | ia_css_ynr2_types.h | 33 default 1000, ineffective 0 */
36 default 1000, ineffective 0 */
39 default 1000, ineffective 0 */
42 default 1000, ineffective 0 */
55 default 1, ineffective 0 */
58 default 0(0), ineffective 0 */
61 default 0(0), ineffective 0 */
64 default 0(0), ineffective 0 */
67 default 0(0), ineffective 0 */
70 default 4096(0.5), ineffective 0 */
[all …]
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| /drivers/gpu/drm/i915/ |
| D | Kconfig.debug | 10 default n
23 default n
64 default n
74 bool "Always insert extra checks around mmio access by default"
75 default n
77 By default, always enables the extra sanity checks (extra register
79 down. This sets the default value of i915.mmio_debug to -1 and can
88 default n
100 default n
115 default n
[all …]
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | Kconfig | 22 default n
32 default y
54 default STMMAC_PLATFORM
62 default ARC
71 default MACH_INGENIC
83 default ARCH_QCOM
99 default ARCH_LPC18XX
115 default ARCH_MESON
126 default ARCH_QCOM
136 default ARCH_ROCKCHIP
[all …]
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| /drivers/usb/dwc3/ |
| D | Kconfig | 27 default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET)
28 default USB_DWC3_HOST if (USB && !USB_GADGET)
29 default USB_DWC3_GADGET if (!USB && USB_GADGET)
49 This is the default mode of working of DWC3 controller where
61 default USB_DWC3
71 default USB_DWC3
80 default USB_DWC3
88 default USB_DWC3
96 default USB_DWC3
105 default USB_DWC3
[all …]
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| /drivers/video/console/ |
| D | Kconfig | 14 default y
51 default y
56 default 160 if PARISC
57 default 80
59 On PA-RISC, the default value is 160, which should fit a 1280x1024
61 Select 80 if you use a 640x480 resolution by default.
66 default 64 if PARISC
67 default 30 if ARM
68 default 25
70 On PA-RISC, the default value is 64, which should fit a 1280x1024
[all …]
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| /drivers/video/logo/ |
| D | Kconfig | 19 default y if SPU_BASE
23 default y
27 default y
31 default y
36 default y
41 default y
46 default y
51 default y
56 default y
61 default y
[all …]
|