1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 32config GIC_NON_BANKED 33 bool 34 35config ARM_GIC_V3 36 bool 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 42config ARM_GIC_V3_ITS 43 bool 44 select GENERIC_MSI_IRQ 45 select IRQ_MSI_LIB 46 default ARM_GIC_V3 47 48config ARM_GIC_V3_ITS_FSL_MC 49 bool 50 depends on ARM_GIC_V3_ITS 51 depends on FSL_MC_BUS 52 default ARM_GIC_V3_ITS 53 54config ARM_NVIC 55 bool 56 select IRQ_DOMAIN_HIERARCHY 57 select GENERIC_IRQ_CHIP 58 59config ARM_VIC 60 bool 61 select IRQ_DOMAIN 62 63config ARM_VIC_NR 64 int 65 default 4 if ARCH_S5PV210 66 default 2 67 depends on ARM_VIC 68 help 69 The maximum number of VICs available in the system, for 70 power management. 71 72config IRQ_MSI_LIB 73 bool 74 select GENERIC_MSI_IRQ 75 76config ARMADA_370_XP_IRQ 77 bool 78 select GENERIC_IRQ_CHIP 79 select PCI_MSI if PCI 80 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 81 82config ALPINE_MSI 83 bool 84 depends on PCI 85 select PCI_MSI 86 select GENERIC_IRQ_CHIP 87 88config AL_FIC 89 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 90 depends on OF 91 depends on HAS_IOMEM 92 select GENERIC_IRQ_CHIP 93 select IRQ_DOMAIN 94 help 95 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 96 97config ATMEL_AIC_IRQ 98 bool 99 select GENERIC_IRQ_CHIP 100 select IRQ_DOMAIN 101 select SPARSE_IRQ 102 103config ATMEL_AIC5_IRQ 104 bool 105 select GENERIC_IRQ_CHIP 106 select IRQ_DOMAIN 107 select SPARSE_IRQ 108 109config I8259 110 bool 111 select IRQ_DOMAIN 112 113config BCM6345_L1_IRQ 114 bool 115 select GENERIC_IRQ_CHIP 116 select IRQ_DOMAIN 117 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 118 119config BCM7038_L1_IRQ 120 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 121 depends on ARCH_BRCMSTB || BMIPS_GENERIC 122 default ARCH_BRCMSTB || BMIPS_GENERIC 123 select GENERIC_IRQ_CHIP 124 select IRQ_DOMAIN 125 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 126 127config BCM7120_L2_IRQ 128 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 129 depends on ARCH_BRCMSTB || BMIPS_GENERIC 130 default ARCH_BRCMSTB || BMIPS_GENERIC 131 select GENERIC_IRQ_CHIP 132 select IRQ_DOMAIN 133 134config BRCMSTB_L2_IRQ 135 tristate "Broadcom STB generic L2 interrupt controller driver" 136 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 137 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 138 select GENERIC_IRQ_CHIP 139 select IRQ_DOMAIN 140 141config DAVINCI_CP_INTC 142 bool 143 select GENERIC_IRQ_CHIP 144 select IRQ_DOMAIN 145 146config DW_APB_ICTL 147 bool 148 select GENERIC_IRQ_CHIP 149 select IRQ_DOMAIN_HIERARCHY 150 151config FARADAY_FTINTC010 152 bool 153 select IRQ_DOMAIN 154 select SPARSE_IRQ 155 156config HISILICON_IRQ_MBIGEN 157 bool 158 select ARM_GIC_V3 159 select ARM_GIC_V3_ITS 160 161config IMGPDC_IRQ 162 bool 163 select GENERIC_IRQ_CHIP 164 select IRQ_DOMAIN 165 166config IXP4XX_IRQ 167 bool 168 select IRQ_DOMAIN 169 select SPARSE_IRQ 170 171config LAN966X_OIC 172 tristate "Microchip LAN966x OIC Support" 173 depends on MCHP_LAN966X_PCI || COMPILE_TEST 174 select GENERIC_IRQ_CHIP 175 select IRQ_DOMAIN 176 help 177 Enable support for the LAN966x Outbound Interrupt Controller. 178 This controller is present on the Microchip LAN966x PCI device and 179 maps the internal interrupts sources to PCIe interrupt. 180 181 To compile this driver as a module, choose M here: the module 182 will be called irq-lan966x-oic. 183 184config MADERA_IRQ 185 tristate 186 187config IRQ_MIPS_CPU 188 bool 189 select GENERIC_IRQ_CHIP 190 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 191 select IRQ_DOMAIN 192 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 193 194config CLPS711X_IRQCHIP 195 bool 196 depends on ARCH_CLPS711X 197 select IRQ_DOMAIN 198 select SPARSE_IRQ 199 default y 200 201config OMPIC 202 bool 203 204config OR1K_PIC 205 bool 206 select IRQ_DOMAIN 207 208config OMAP_IRQCHIP 209 bool 210 select GENERIC_IRQ_CHIP 211 select IRQ_DOMAIN 212 213config ORION_IRQCHIP 214 bool 215 select IRQ_DOMAIN 216 217config PIC32_EVIC 218 bool 219 select GENERIC_IRQ_CHIP 220 select IRQ_DOMAIN 221 222config JCORE_AIC 223 bool "J-Core integrated AIC" if COMPILE_TEST 224 depends on OF 225 select IRQ_DOMAIN 226 help 227 Support for the J-Core integrated AIC. 228 229config RDA_INTC 230 bool 231 select IRQ_DOMAIN 232 233config RENESAS_INTC_IRQPIN 234 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 235 select IRQ_DOMAIN 236 help 237 Enable support for the Renesas Interrupt Controller for external 238 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 239 240config RENESAS_IRQC 241 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 242 select GENERIC_IRQ_CHIP 243 select IRQ_DOMAIN 244 help 245 Enable support for the Renesas Interrupt Controller for external 246 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 247 248config RENESAS_RZA1_IRQC 249 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 250 select IRQ_DOMAIN_HIERARCHY 251 help 252 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 253 to 8 external interrupts with configurable sense select. 254 255config RENESAS_RZG2L_IRQC 256 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 257 select GENERIC_IRQ_CHIP 258 select IRQ_DOMAIN_HIERARCHY 259 help 260 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 261 for external devices. 262 263config SL28CPLD_INTC 264 bool "Kontron sl28cpld IRQ controller" 265 depends on MFD_SL28CPLD=y || COMPILE_TEST 266 select REGMAP_IRQ 267 help 268 Interrupt controller driver for the board management controller 269 found on the Kontron sl28 CPLD. 270 271config ST_IRQCHIP 272 bool 273 select REGMAP 274 select MFD_SYSCON 275 help 276 Enables SysCfg Controlled IRQs on STi based platforms. 277 278config SUN4I_INTC 279 bool 280 281config SUN6I_R_INTC 282 bool 283 select IRQ_DOMAIN_HIERARCHY 284 select IRQ_FASTEOI_HIERARCHY_HANDLERS 285 286config SUNXI_NMI_INTC 287 bool 288 select GENERIC_IRQ_CHIP 289 290config TB10X_IRQC 291 bool 292 select IRQ_DOMAIN 293 select GENERIC_IRQ_CHIP 294 295config TS4800_IRQ 296 tristate "TS-4800 IRQ controller" 297 select IRQ_DOMAIN 298 depends on HAS_IOMEM 299 depends on SOC_IMX51 || COMPILE_TEST 300 help 301 Support for the TS-4800 FPGA IRQ controller 302 303config VERSATILE_FPGA_IRQ 304 bool 305 select IRQ_DOMAIN 306 307config VERSATILE_FPGA_IRQ_NR 308 int 309 default 4 310 depends on VERSATILE_FPGA_IRQ 311 312config XTENSA_MX 313 bool 314 select IRQ_DOMAIN 315 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 316 317config XILINX_INTC 318 bool "Xilinx Interrupt Controller IP" 319 depends on OF_ADDRESS 320 select IRQ_DOMAIN 321 help 322 Support for the Xilinx Interrupt Controller IP core. 323 This is used as a primary controller with MicroBlaze and can also 324 be used as a secondary chained controller on other platforms. 325 326config IRQ_CROSSBAR 327 bool 328 help 329 Support for a CROSSBAR ip that precedes the main interrupt controller. 330 The primary irqchip invokes the crossbar's callback which inturn allocates 331 a free irq and configures the IP. Thus the peripheral interrupts are 332 routed to one of the free irqchip interrupt lines. 333 334config KEYSTONE_IRQ 335 tristate "Keystone 2 IRQ controller IP" 336 depends on ARCH_KEYSTONE 337 help 338 Support for Texas Instruments Keystone 2 IRQ controller IP which 339 is part of the Keystone 2 IPC mechanism 340 341config MIPS_GIC 342 bool 343 select GENERIC_IRQ_IPI if SMP 344 select IRQ_DOMAIN_HIERARCHY 345 select MIPS_CM 346 347config INGENIC_IRQ 348 bool 349 depends on MACH_INGENIC 350 default y 351 352config INGENIC_TCU_IRQ 353 bool "Ingenic JZ47xx TCU interrupt controller" 354 default MACH_INGENIC 355 depends on MIPS || COMPILE_TEST 356 select MFD_SYSCON 357 select GENERIC_IRQ_CHIP 358 help 359 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 360 JZ47xx SoCs. 361 362 If unsure, say N. 363 364config IMX_GPCV2 365 bool 366 select IRQ_DOMAIN 367 help 368 Enables the wakeup IRQs for IMX platforms with GPCv2 block 369 370config IRQ_MXS 371 def_bool y if MACH_ASM9260 || ARCH_MXS 372 select IRQ_DOMAIN 373 select STMP_DEVICE 374 375config MSCC_OCELOT_IRQ 376 bool 377 select IRQ_DOMAIN 378 select GENERIC_IRQ_CHIP 379 380config MVEBU_GICP 381 select IRQ_MSI_LIB 382 bool 383 384config MVEBU_ICU 385 bool 386 387config MVEBU_ODMI 388 bool 389 select IRQ_MSI_LIB 390 select GENERIC_MSI_IRQ 391 392config MVEBU_PIC 393 bool 394 395config MVEBU_SEI 396 bool 397 398config LS_EXTIRQ 399 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 400 select MFD_SYSCON 401 402config LS_SCFG_MSI 403 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 404 depends on PCI_MSI 405 406config PARTITION_PERCPU 407 bool 408 409config STM32MP_EXTI 410 tristate "STM32MP extended interrupts and event controller" 411 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 412 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 413 select IRQ_DOMAIN_HIERARCHY 414 select GENERIC_IRQ_CHIP 415 help 416 Support STM32MP EXTI (extended interrupts and event) controller. 417 418config STM32_EXTI 419 bool 420 select IRQ_DOMAIN 421 select GENERIC_IRQ_CHIP 422 423config QCOM_IRQ_COMBINER 424 bool "QCOM IRQ combiner support" 425 depends on ARCH_QCOM && ACPI 426 select IRQ_DOMAIN_HIERARCHY 427 help 428 Say yes here to add support for the IRQ combiner devices embedded 429 in Qualcomm Technologies chips. 430 431config IRQ_UNIPHIER_AIDET 432 bool "UniPhier AIDET support" if COMPILE_TEST 433 depends on ARCH_UNIPHIER || COMPILE_TEST 434 default ARCH_UNIPHIER 435 select IRQ_DOMAIN_HIERARCHY 436 help 437 Support for the UniPhier AIDET (ARM Interrupt Detector). 438 439config MESON_IRQ_GPIO 440 tristate "Meson GPIO Interrupt Multiplexer" 441 depends on ARCH_MESON || COMPILE_TEST 442 default ARCH_MESON 443 select IRQ_DOMAIN_HIERARCHY 444 help 445 Support Meson SoC Family GPIO Interrupt Multiplexer 446 447config GOLDFISH_PIC 448 bool "Goldfish programmable interrupt controller" 449 depends on MIPS && (GOLDFISH || COMPILE_TEST) 450 select GENERIC_IRQ_CHIP 451 select IRQ_DOMAIN 452 help 453 Say yes here to enable Goldfish interrupt controller driver used 454 for Goldfish based virtual platforms. 455 456config QCOM_PDC 457 tristate "QCOM PDC" 458 depends on ARCH_QCOM 459 select IRQ_DOMAIN_HIERARCHY 460 help 461 Power Domain Controller driver to manage and configure wakeup 462 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 463 464config QCOM_MPM 465 tristate "QCOM MPM" 466 depends on ARCH_QCOM 467 depends on MAILBOX 468 select IRQ_DOMAIN_HIERARCHY 469 help 470 MSM Power Manager driver to manage and configure wakeup 471 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 472 473config CSKY_MPINTC 474 bool 475 depends on CSKY 476 help 477 Say yes here to enable C-SKY SMP interrupt controller driver used 478 for C-SKY SMP system. 479 In fact it's not mmio map in hardware and it uses ld/st to visit the 480 controller's register inside CPU. 481 482config CSKY_APB_INTC 483 bool "C-SKY APB Interrupt Controller" 484 depends on CSKY 485 help 486 Say yes here to enable C-SKY APB interrupt controller driver used 487 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 488 the controller's register. 489 490config IMX_IRQSTEER 491 bool "i.MX IRQSTEER support" 492 depends on ARCH_MXC || COMPILE_TEST 493 default ARCH_MXC 494 select IRQ_DOMAIN 495 help 496 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 497 498config IMX_INTMUX 499 bool "i.MX INTMUX support" if COMPILE_TEST 500 default y if ARCH_MXC 501 select IRQ_DOMAIN 502 help 503 Support for the i.MX INTMUX interrupt multiplexer. 504 505config IMX_MU_MSI 506 tristate "i.MX MU used as MSI controller" 507 depends on OF && HAS_IOMEM 508 depends on ARCH_MXC || COMPILE_TEST 509 depends on ARM || ARM64 510 default m if ARCH_MXC 511 select IRQ_DOMAIN 512 select IRQ_DOMAIN_HIERARCHY 513 select GENERIC_MSI_IRQ 514 select IRQ_MSI_LIB 515 help 516 Provide a driver for the i.MX Messaging Unit block used as a 517 CPU-to-CPU MSI controller. This requires a specially crafted DT 518 to make use of this driver. 519 520 If unsure, say N 521 522config LS1X_IRQ 523 bool "Loongson-1 Interrupt Controller" 524 depends on MACH_LOONGSON32 525 default y 526 select IRQ_DOMAIN 527 select GENERIC_IRQ_CHIP 528 help 529 Support for the Loongson-1 platform Interrupt Controller. 530 531config TI_SCI_INTR_IRQCHIP 532 bool 533 depends on TI_SCI_PROTOCOL 534 select IRQ_DOMAIN_HIERARCHY 535 help 536 This enables the irqchip driver support for K3 Interrupt router 537 over TI System Control Interface available on some new TI's SoCs. 538 If you wish to use interrupt router irq resources managed by the 539 TI System Controller, say Y here. Otherwise, say N. 540 541config TI_SCI_INTA_IRQCHIP 542 bool 543 depends on TI_SCI_PROTOCOL 544 select IRQ_DOMAIN_HIERARCHY 545 select TI_SCI_INTA_MSI_DOMAIN 546 help 547 This enables the irqchip driver support for K3 Interrupt aggregator 548 over TI System Control Interface available on some new TI's SoCs. 549 If you wish to use interrupt aggregator irq resources managed by the 550 TI System Controller, say Y here. Otherwise, say N. 551 552config TI_PRUSS_INTC 553 tristate 554 depends on TI_PRUSS 555 default TI_PRUSS 556 select IRQ_DOMAIN 557 help 558 This enables support for the PRU-ICSS Local Interrupt Controller 559 present within a PRU-ICSS subsystem present on various TI SoCs. 560 The PRUSS INTC enables various interrupts to be routed to multiple 561 different processors within the SoC. 562 563config RISCV_INTC 564 bool 565 depends on RISCV 566 select IRQ_DOMAIN_HIERARCHY 567 568config RISCV_APLIC 569 bool 570 depends on RISCV 571 select IRQ_DOMAIN_HIERARCHY 572 573config RISCV_APLIC_MSI 574 bool 575 depends on RISCV_APLIC 576 select GENERIC_MSI_IRQ 577 default RISCV_APLIC 578 579config RISCV_IMSIC 580 bool 581 depends on RISCV 582 select IRQ_DOMAIN_HIERARCHY 583 select GENERIC_IRQ_MATRIX_ALLOCATOR 584 select GENERIC_MSI_IRQ 585 586config RISCV_IMSIC_PCI 587 bool 588 depends on RISCV_IMSIC 589 depends on PCI 590 depends on PCI_MSI 591 default RISCV_IMSIC 592 593config SIFIVE_PLIC 594 bool 595 depends on RISCV 596 select IRQ_DOMAIN_HIERARCHY 597 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 598 599config STARFIVE_JH8100_INTC 600 bool "StarFive JH8100 External Interrupt Controller" 601 depends on ARCH_STARFIVE || COMPILE_TEST 602 default ARCH_STARFIVE 603 select IRQ_DOMAIN_HIERARCHY 604 help 605 This enables support for the INTC chip found in StarFive JH8100 606 SoC. 607 608 If you don't know what to do here, say Y. 609 610config EXYNOS_IRQ_COMBINER 611 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 612 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 613 help 614 Say yes here to add support for the IRQ combiner devices embedded 615 in Samsung Exynos chips. 616 617config IRQ_LOONGARCH_CPU 618 bool 619 select GENERIC_IRQ_CHIP 620 select IRQ_DOMAIN 621 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 622 select LOONGSON_HTVEC 623 select LOONGSON_LIOINTC 624 select LOONGSON_EIOINTC 625 select LOONGSON_PCH_PIC 626 select LOONGSON_PCH_MSI 627 select LOONGSON_PCH_LPC 628 help 629 Support for the LoongArch CPU Interrupt Controller. For details of 630 irq chip hierarchy on LoongArch platforms please read the document 631 Documentation/arch/loongarch/irq-chip-model.rst. 632 633config LOONGSON_LIOINTC 634 bool "Loongson Local I/O Interrupt Controller" 635 depends on MACH_LOONGSON64 636 default y 637 select IRQ_DOMAIN 638 select GENERIC_IRQ_CHIP 639 help 640 Support for the Loongson Local I/O Interrupt Controller. 641 642config LOONGSON_EIOINTC 643 bool "Loongson Extend I/O Interrupt Controller" 644 depends on LOONGARCH 645 depends on MACH_LOONGSON64 646 default MACH_LOONGSON64 647 select IRQ_DOMAIN_HIERARCHY 648 select GENERIC_IRQ_CHIP 649 help 650 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 651 652config LOONGSON_HTPIC 653 bool "Loongson3 HyperTransport PIC Controller" 654 depends on MACH_LOONGSON64 && MIPS 655 default y 656 select IRQ_DOMAIN 657 select GENERIC_IRQ_CHIP 658 help 659 Support for the Loongson-3 HyperTransport PIC Controller. 660 661config LOONGSON_HTVEC 662 bool "Loongson HyperTransport Interrupt Vector Controller" 663 depends on MACH_LOONGSON64 664 default MACH_LOONGSON64 665 select IRQ_DOMAIN_HIERARCHY 666 help 667 Support for the Loongson HyperTransport Interrupt Vector Controller. 668 669config LOONGSON_PCH_PIC 670 bool "Loongson PCH PIC Controller" 671 depends on MACH_LOONGSON64 672 default MACH_LOONGSON64 673 select IRQ_DOMAIN_HIERARCHY 674 select IRQ_FASTEOI_HIERARCHY_HANDLERS 675 help 676 Support for the Loongson PCH PIC Controller. 677 678config LOONGSON_PCH_MSI 679 bool "Loongson PCH MSI Controller" 680 depends on MACH_LOONGSON64 681 depends on PCI 682 default MACH_LOONGSON64 683 select IRQ_DOMAIN_HIERARCHY 684 select IRQ_MSI_LIB 685 select PCI_MSI 686 help 687 Support for the Loongson PCH MSI Controller. 688 689config LOONGSON_PCH_LPC 690 bool "Loongson PCH LPC Controller" 691 depends on LOONGARCH 692 depends on MACH_LOONGSON64 693 default MACH_LOONGSON64 694 select IRQ_DOMAIN_HIERARCHY 695 help 696 Support for the Loongson PCH LPC Controller. 697 698config MST_IRQ 699 bool "MStar Interrupt Controller" 700 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 701 default ARCH_MEDIATEK 702 select IRQ_DOMAIN 703 select IRQ_DOMAIN_HIERARCHY 704 help 705 Support MStar Interrupt Controller. 706 707config MTK_IRQ 708 bool 709 default ARCH_MEDIATEK 710 711config WPCM450_AIC 712 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 713 depends on ARCH_WPCM450 714 help 715 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 716 717config IRQ_IDT3243X 718 bool 719 select GENERIC_IRQ_CHIP 720 select IRQ_DOMAIN 721 722config APPLE_AIC 723 bool "Apple Interrupt Controller (AIC)" 724 depends on ARM64 725 depends on ARCH_APPLE || COMPILE_TEST 726 select GENERIC_IRQ_IPI_MUX 727 help 728 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 729 such as the M1. 730 731config MCHP_EIC 732 bool "Microchip External Interrupt Controller" 733 depends on ARCH_AT91 || COMPILE_TEST 734 select IRQ_DOMAIN 735 select IRQ_DOMAIN_HIERARCHY 736 help 737 Support for Microchip External Interrupt Controller. 738 739config SUNPLUS_SP7021_INTC 740 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 741 default SOC_SP7021 742 help 743 Support for the Sunplus SP7021 Interrupt Controller IP core. 744 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 745 chained controller, routing all interrupt source in P-Chip to 746 the primary controller on C-Chip. 747 748endmenu 749