Searched full:description (Results 1 – 25 of 4806) sorted by relevance
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| /Documentation/devicetree/bindings/ |
| D | vendor-prefixes.yaml | 27 description: Baiwen.com (100ask).
29 description: 70mai Co., Ltd.
31 description: 8devices, UAB
33 description: ABB
35 description: Abilis Systems
37 description: Abracon Corporation
39 description: ShenZhen Asia Better Technology Ltd.
41 description: Acbel Polytech Inc.
43 description: Acelink Technology Co., Ltd.
45 description: Acer Inc.
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| /Documentation/devicetree/bindings/clock/ |
| D | st,stm32mp25-rcc.yaml | 12 description: |
36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
39 - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
40 - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
41 - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
42 - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
43 - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
44 - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
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| D | qcom,mmcc.yaml | 13 description: |
54 description:
58 description:
82 - description: Board PXO source
83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
85 - description: DSI phy instance 1 dsi clock
86 - description: DSI phy instance 1 byte clock
87 - description: DSI phy instance 2 dsi clock
88 - description: DSI phy instance 2 byte clock
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| D | fsl,imx8-acm.yaml | 12 description: |
32 description:
64 - description: power domain of IMX_SC_R_AUDIO_CLK_0
65 - description: power domain of IMX_SC_R_AUDIO_CLK_1
66 - description: power domain of IMX_SC_R_MCLK_OUT_0
67 - description: power domain of IMX_SC_R_MCLK_OUT_1
68 - description: power domain of IMX_SC_R_AUDIO_PLL_0
69 - description: power domain of IMX_SC_R_AUDIO_PLL_1
70 - description: power domain of IMX_SC_R_ASRC_0
71 - description: power domain of IMX_SC_R_ASRC_1
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| D | qcom,gcc-sc8280xp.yaml | 12 description: |
24 - description: XO reference clock
25 - description: Sleep clock
26 - description: UFS memory first RX symbol clock
27 - description: UFS memory second RX symbol clock
28 - description: UFS memory first TX symbol clock
29 - description: UFS card first RX symbol clock
30 - description: UFS card second RX symbol clock
31 - description: UFS card first TX symbol clock
32 - description: Primary USB SuperSpeed pipe clock
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| D | starfive,jh7110-syscrg.yaml | 22 - description: Main Oscillator (24 MHz)
23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
24 - description: External I2S TX bit clock
25 - description: External I2S TX left/right channel clock
26 - description: External I2S RX bit clock
27 - description: External I2S RX left/right channel clock
28 - description: External TDM clock
29 - description: External audio master clock
30 - description: PLL0
31 - description: PLL1
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 13 description: |
26 - description: external memory clock
37 description:
42 description:
46 description:
57 description:
66 description:
73 description:
79 description:
85 description:
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| D | nvidia,tegra30-emc.yaml | 14 description: |
39 description:
44 description:
48 description:
58 description:
66 description:
72 description:
80 description:
85 description:
90 description:
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| D | nvidia,tegra20-emc.yaml | 14 description: |
45 description:
50 description:
54 description:
60 description:
71 description:
78 description:
83 description:
89 - description: EMC_RC
90 - description: EMC_RFC
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| D | ti,gpmc-child.yaml | 13 description:
25 description: Minimum clock period for synchronous mode
30 description: Assertion time
34 description: Read deassertion time
38 description: Write deassertion time
43 description: Assertion time
47 description: Read deassertion time
51 description: Write deassertion time
55 description: Assertion time for AAD
59 description: Read deassertion time for AAD
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| /Documentation/devicetree/bindings/sound/ |
| D | mediatek,mt2701-audio.yaml | 9 description:
23 - description: AFE interrupt
24 - description: ASYS interrupt
36 - description: audio infra sys clock
37 - description: top audio mux 1
38 - description: top audio mux 2
39 - description: top audio sys a1 clock
40 - description: top audio sys a2 clock
41 - description: i2s0 source selection
42 - description: i2s1 source selection
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| /Documentation/devicetree/bindings/arm/ |
| D | sunxi.yaml | 19 - description: Allwinner A100 Perf1 Board
24 - description: Allwinner A23 Evaluation Board
29 - description: Allwinner A31 APP4 Evaluation Board
34 - description: Allwinner A83t Homlet Evaluation Board v2
39 - description: Allwinner GA10H Quad Core Tablet v1.1
44 - description: Allwinner GT90H Tablet v4
49 - description: Allwinner R16 EVB (Parrot)
54 - description: Anbernic RG-Nano
59 - description: Anbernic RG35XX (2024)
64 - description: Anbernic RG35XX H
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| /Documentation/devicetree/bindings/power/ |
| D | rockchip-io-domain.yaml | 12 description: |
97 description: The supply connected to VCCIO1.
99 description: The supply connected to VCCIO2.
101 description: The supply connected to VCCIO3.
103 description: The supply connected to VCCIO4.
105 description: The supply connected to VCCIO5.
107 description: The supply connected to VCCIO6.
109 description: The supply connected to VCCIO_OSCGPI.
121 description: The supply connected to PMUIO1.
123 description: The supply connected to PMUIO2.
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-single.yaml | 12 description:
52 description:
58 description: Optional flag to indicate register controls more than one pin
62 description: Mask of the allowed register bits
66 description: Optional function off mode for disabled state
70 description: Width of pin specific bits in the register
75 description: Optional list of pin base, nr pins & gpio function
79 - description: phandle of a gpio-range node
80 - description: pin base
81 - description: number of pins
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | qcom,ath11k.yaml | 14 description: |
38 description:
47 description:
54 description:
66 description: |
74 description: State bits used by the AP to signal the WLAN Q6.
76 - description: Signal bits used to enable/disable low power mode
80 description: The names of the state bits used for SMP2P output.
105 - description: misc-pulse1 interrupt events
106 - description: misc-latch interrupt events
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| /Documentation/devicetree/bindings/cache/ |
| D | qcom,llcc.yaml | 12 description: |
53 - description: Reference to an nvmem node for multi channel DDR
76 - description: LLCC0 base register region
77 - description: LLCC broadcast base register region
93 - description: LLCC0 base register region
94 - description: LLCC1 base register region
95 - description: LLCC2 base register region
96 - description: LLCC3 base register region
97 - description: LLCC4 base register region
98 - description: LLCC5 base register region
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,sc7280-mss-pil.yaml | 12 description:
23 - description: MSS QDSP6 registers
24 - description: RMB registers
33 - description: MSA Stream 1
34 - description: MSA Stream 2
38 - description: Path leading to system memory
42 - description: Watchdog interrupt
43 - description: Fatal interrupt
44 - description: Ready interrupt
45 - description: Handover interrupt
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| D | qcom,msm8996-mss-pil.yaml | 13 description:
27 - description: MSS QDSP6 registers
28 - description: RMB registers
37 - description: MSA Stream 1
38 - description: MSA Stream 2
42 - description: Watchdog interrupt
43 - description: Fatal interrupt
44 - description: Ready interrupt
45 - description: Handover interrupt
46 - description: Stop acknowledge interrupt
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| D | qcom,sc7180-mss-pil.yaml | 12 description:
23 - description: MSS QDSP6 registers
24 - description: RMB registers
33 - description: MSA Stream 1
34 - description: MSA Stream 2
38 - description: Watchdog interrupt
39 - description: Fatal interrupt
40 - description: Ready interrupt
41 - description: Handover interrupt
42 - description: Stop acknowledge interrupt
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| /Documentation/netlink/ |
| D | genetlink-legacy.yaml | 24 description: Specification of a genetlink protocol
30 description: Name of the genetlink family.
35 description: Schema compatibility level. Default is "genetlink".
38 description: Path to the uAPI header, default is linux/${family-name}.h
42 description: Name of the define for the family name.
45 description: Name of the define for the version of the family.
48 …description: Makes the number of attributes and commands be specified by a define, not an enum val…
51 description: Name of the define for the last operation in the list.
54 … description: The explicit name for constant holding the count of operations (last operation + 1).
59 description: |
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| D | netlink-raw.yaml | 19 description: Specification of a raw netlink protocol
25 description: Name of the netlink family.
30 description: Schema compatibility level.
34 description: Protocol number to use for netlink-raw
38 description: Path to the uAPI header, default is linux/${family-name}.h
42 description: Name of the define for the family name.
45 description: Name of the define for the version of the family.
48 …description: Makes the number of attributes and commands be specified by a define, not an enum val…
51 description: Name of the define for the last operation in the list.
54 … description: The explicit name for constant holding the count of operations (last operation + 1).
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| D | genetlink-c.yaml | 24 description: Specification of a genetlink protocol
30 description: Name of the genetlink family.
35 description: Schema compatibility level. Default is "genetlink".
38 description: Path to the uAPI header, default is linux/${family-name}.h
42 description: Name of the define for the family name.
45 description: Name of the define for the version of the family.
48 …description: Makes the number of attributes and commands be specified by a define, not an enum val…
51 description: Name of the define for the last operation in the list.
54 … description: The explicit name for constant holding the count of operations (last operation + 1).
59 description: List of type and constant definitions (enums, flags, defines).
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| /Documentation/devicetree/bindings/dma/ |
| D | cirrus,ep9301-dma-m2p.yaml | 30 - description: m2p0 channel registers
31 - description: m2p1 channel registers
32 - description: m2p2 channel registers
33 - description: m2p3 channel registers
34 - description: m2p4 channel registers
35 - description: m2p5 channel registers
36 - description: m2p6 channel registers
37 - description: m2p7 channel registers
38 - description: m2p8 channel registers
39 - description: m2p9 channel registers
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| /Documentation/ABI/testing/ |
| D | sysfs-class-hwmon | 2 Description:
13 Description:
21 Description:
31 Description:
39 Description:
51 Description:
59 Description:
71 Description:
93 Description:
101 Description:
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | renesas,rzg2l-irqc.yaml | 13 description: |
36 description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
52 - description: NMI interrupt
53 - description: IRQ0 interrupt
54 - description: IRQ1 interrupt
55 - description: IRQ2 interrupt
56 - description: IRQ3 interrupt
57 - description: IRQ4 interrupt
58 - description: IRQ5 interrupt
59 - description: IRQ6 interrupt
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