Searched +full:entry +full:- +full:latency (Results 1 – 25 of 75) sorted by relevance
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| /Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: domain-idle-states
21 "^(cpu|cluster|domain)-":
29 const: domain-idle-state
31 entry-latency-us:
33 The worst case latency in microseconds required to enter the idle
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| D | power-domain.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
25 \#power-domain-cells property in the PM domain provider node.
29 pattern: "^(power-controller|power-domain|performance-domain)([@-].*)?$"
31 domain-idle-states:
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| /Documentation/devicetree/bindings/cpu/ |
| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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| D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | nvidia,tegra124-cpufreq.txt | 2 ----------------------------------------------
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - cpu_g: Clock mux for the fast CPU cluster.
12 - pll_x: Fast PLL clocksource.
13 - pll_p: Auxiliary PLL used during fast PLL rate changes.
14 - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
17 - clock-latency: Specify the possible maximum transition latency for clock,
21 --------
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| D | nvidia,tegra20-cpufreq.txt | 5 - clocks: Must contain an entry for the CPU clock.
6 See ../clocks/clock-bindings.txt for details.
7 - operating-points-v2: See ../bindings/opp/opp-v2.yaml for details.
8 - #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.
10 For each opp entry in 'operating-points-v2' table:
11 - opp-supported-hw: Two bitfields indicating:
23 - opp-microvolt: CPU voltage triplet.
26 - cpu-supply: Phandle to the CPU power supply.
31 regulator-name = "vdd_cpu";
36 compatible = "operating-points-v2";
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| /Documentation/ABI/testing/ |
| D | debugfs-intel-iommu | 62 Entry SrcID DstID Vct IRTE_high IRTE_low
68 Entry SrcID DstID Vct IRTE_high IRTE_low
77 Entry SrcID PDA_high PDA_low Vct IRTE_high IRTE_low
87 '-1' and other PASID related fields are invalid.
103 -1 0x0000000000000000:0x0000000000000000:0x0000000000000000
166 * 0 - disable sampling all latency data
168 * 1 - enable sampling IOTLB invalidation latency data
170 * 2 - enable sampling devTLB invalidation latency data
172 * 3 - enable sampling intr entry cache invalidation latency data
181 1) Disable sampling all latency data:
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| D | sysfs-class-rtrs-client | 1 What: /sys/class/rtrs-client
5 Description: When a user of RTRS API creates a new session, a directory entry with
6 the name of that session is created under /sys/class/rtrs-client/<session-name>/
8 What: /sys/class/rtrs-client/<session-name>/add_path
18 What: /sys/class/rtrs-client/<session-name>/max_reconnect_attempts
25 What: /sys/class/rtrs-client/<session-name>/mp_policy
31 round-robin (0):
32 select path in per CPU round-robin manner.
34 min-inflight (1):
37 min-latency (2):
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| D | sysfs-driver-ufs | 3 Contact: linux-scsi@vger.kernel.org
5 This file contains the auto-hibernate idle timer setting of a
6 UFS host controller. A value of '0' means auto-hibernate is not
10 expense of increased latency. Note that the hardware supports
11 10-bit values with a power-of-ten multiplier which allows a
147 latency. This is one of the UFS device descriptor parameters.
273 written during the pre-soldering phase of the PSA flow.
307 Description: This file shows the MIPI M-PHY version number in BCD format.
395 Description: This file shows the maximum data-in buffer size. This
406 Description: This file shows the maximum data-out buffer size. This
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| /Documentation/devicetree/bindings/arm/ |
| D | psci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
52 - const: arm,psci-0.2
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| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 1 IBM Power-Management Bindings
6 node @power-mgt in the device-tree by the firmware.
9 ----------------
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
15 extent of state-loss, whether timebase is stopped on this
18 - exit-latency: The latency involved in transitioning the state of the
21 - target-residency: The minimum time that the CPU needs to reside in
22 this idle state in order to accrue power-savings
26 ----------------
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| /Documentation/arch/arm/omap/ |
| D | omap_pm.rst | 6 authors use these functions to communicate minimum latency or
13 - support the range of power management parameters present in the TI SRF;
15 - separate the drivers from the underlying PM parameter
17 latency framework or something else;
19 - specify PM parameters in terms of fundamental units, such as
20 latency and throughput, rather than units which are specific to OMAP
23 - allow drivers which are shared with other architectures (e.g.,
24 DaVinci) to add these constraints in a way which won't affect non-OMAP
27 - can be implemented immediately with minimal disruption of other
34 1. Set the maximum MPU wakeup latency::
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| /Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
37 software as individual single-core processors. In other words, a CPU is an
46 Second, if the processor is multi-core, each core in it is able to follow at
61 Finally, each core in a multi-core processor may be able to follow more than one
66 multiple individual single-core "processors", referred to as *hardware threads*
67 (or hyper-threads specifically on Intel hardware), that each can follow one
78 ---------
107 next wakeup event, or there are strict latency constraints preventing any of the
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| D | intel_idle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
28 processor's functional blocks into low-power states. That instruction takes two
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
50 as C-states (in the ACPI terminology) or idle states. The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
56 subsystem (see :ref:`idle-states-representation` in
57 Documentation/admin-guide/pm/cpuidle.rst),
66 `below <intel-idle-parameters_>`_.]
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| /Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
58 ---------------
70 performance penalty and a fixed latency. Mitigation can be increased
78 |------- -------
81 <------>
82 idle <---------------------->
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| /Documentation/networking/devlink/ |
| D | devlink-dpipe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 ``devlink-dpipe`` provides a standardized way to provide visibility into the
34 Level Path Compression trie (LPC-trie) in hardware.
45 The ``devlink-dpipe`` interface closes this gap. The hardware's pipeline is
50 configuration, but the ``devlink-dpipe`` interface uses it for visibility
52 ``devlink-dpipe`` should change according to the changes done by the
61 in a chain (which may affect the data path latency). In response to a new TC
74 the packet. A ``table`` describes hardware blocks. An ``entry`` describes
84 ``devlink-dpipe`` generally is not intended for configuration. The exception
96 -----
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| /Documentation/trace/ |
| D | ftrace.rst | 2 ftrace - Function Tracer
13 - Written for: 2.6.28-rc2
14 - Updated for: 3.10
15 - Updated for: 4.13 - Copyright 2017 VMware Inc. Steven Rostedt
16 - Converted to rst format - Changbin Du <changbin.du@intel.com>
19 ------------
24 performance issues that take place outside of user-space.
28 There's latency tracing to examine what occurs between interrupts
41 ----------------------
43 See Documentation/trace/ftrace-design.rst for details for arch porters and such.
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| D | histogram.rst | 30 When a matching event is hit, an entry is added to a hash table
33 numeric fields - on an event hit, the value(s) will be added to a
35 in place of an explicit value field - this is simply a count of
43 keyword. Hashing a compound key produces a unique entry in the
45 useful for providing more fine-grained summaries of event data.
66 entry is a simple list of the keys and values comprising the entry;
68 followed by the set of value fields for the entry. By default,
69 numeric fields are displayed as base-10 integers. This can be
76 .sym-offset display an address as a symbol and offset
83 .graph display a bar-graph of a value
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| D | osnoise-tracer.rst | 5 In the context of high-performance computing (HPC), the Operating System
9 system. Moreover, hardware-related jobs can also cause noise, for example,
25 the latency. The hwlat detects the NMI execution by observing
26 the entry and exit of a NMI.
31 of hwlat, osnoise takes note of the entry and exit point of any
32 source of interferences, increasing a per-cpu interference counter. The
35 threads is increased anytime the tool observes these interferences' entry
38 hardware-related noise. In this way, osnoise can account for any
44 -----
59 # _-----=> irqs-off
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | e1000.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
50 -------
54 :Valid Range: 0x01-0x0F, 0x20-0x2F
57 This parameter is a bit-mask that specifies the speed and duplex settings
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| /Documentation/networking/ |
| D | scaling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
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| /Documentation/mm/ |
| D | hmm.rst | 5 Provide infrastructure and helpers to integrate non-conventional memory (device
21 CPU page-table mirroring works and the purpose of HMM in this context. The
52 complex data set needs to re-map all the pointer relations between each of its
64 combinatorial explosion in the library entry points.
90 The final limitation is latency. Access to main memory from the device has an
91 order of magnitude higher latency than when the device accesses its own memory.
95 two-way cache coherency between CPU and device and allow all atomic operations the
115 allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
155 During the ops->invalidate() callback the device driver must perform the
164 It will trigger a page fault on missing or read-only entries if write access is
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| D | page_tables.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 feature of all Unix-like systems as time went by. In 1985 the feature was
34 As you can see, with 4KB pages the page base address uses bits 12-31 of the
42 this single table were referred to as *PTE*:s - page table entries.
55 Additionally, on modern CPUs, a higher level page table entry can point directly
57 megabytes or even gigabytes in a single high-level page table entry, taking
63 +-----+
65 +-----+
67 | +-----+
68 +-->| P4D |
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| D | page_migration.rst | 13 The main intent of page migration is to reduce the latency of memory accesses
38 For example, A NUMA profiler may obtain a log showing frequent off-node
99 this (not yet up-to-date) page immediately block while the move is in progress.
105 or wait for the migration page table entry to be removed.
149 Non-LRU page migration
152 Although migration originally aimed for reducing the latency of memory
153 accesses for NUMA, compaction also uses migration to create high-order
155 non-LRU pages, such as zsmalloc and virtio-balloon pages.
159 page that it may be able to move. This uses the ``page->mapping`` field,
168 page was migrated. If the page was a non-THP and non-hugetlb page, then
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| /Documentation/arch/x86/x86_64/ |
| D | fred.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 latency transitions.
33 The LKGS instruction can be used by 64-bit operating systems that do
46 framework must be implemented to facilitate the event-to-handler
48 once an event is delivered, and employs a two-level dispatch.
59 to handle all the ugly corner cases caused by half baked entry states.
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