Searched +full:instruction +full:- +full:fetch (Results 1 – 13 of 13) sorted by relevance
| /Documentation/devicetree/bindings/watchdog/ |
| D | microchip,pic32-dmt.txt | 4 malfunction. It is a free-running instruction fetch timer, which is clocked
5 whenever an instruction fetch occurs until a count match occurs.
8 - compatible: must be "microchip,pic32mzda-dmt".
9 - reg: physical base address of the controller and length of memory mapped
11 - clocks: phandle of source clk. Should be <&rootclk PB7CLK>.
16 compatible = "microchip,pic32mzda-dmt";
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| /Documentation/arch/loongarch/ |
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
12 instruction set, virtual memory and some other topics of LoongArch.
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
27 link register of the BL instruction.)
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| /Documentation/trace/ |
| D | uprobetracer.rst | 2 Uprobe-tracer: Uprobe-based Event Tracing
9 --------
13 Similar to the kprobe-event tracer, this doesn't need to be activated via
18 However unlike kprobe-event tracer, the uprobe event interface expects the
26 -------------------------
32 -:[GRP/][EVENT] : Clear uprobe or uretprobe event
42 %REG : Fetch register REG
43 @ADDR : Fetch memory at ADDR (ADDR should be in userspace)
44 @+OFFSET : Fetch memory at OFFSET (OFFSET from same file as PATH)
45 $stackN : Fetch Nth entry of stack (N >= 0)
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| /Documentation/bpf/standardization/ |
| D | instruction-set.rst | 5 BPF Instruction Set Architecture (ISA)
11 operating system kernel. This document specifies the BPF instruction
27 BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_
28 `<https://www.rfc-editor.org/info/rfc8174>`_
38 -----
51 .. table:: Meaning of bit-width notation
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
68 ---------
70 The following byteswap functions are direction-agnostic. That is,
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| /Documentation/admin-guide/hw-vuln/ |
| D | multihit.rst | 6 instruction fetch hits multiple entries in the instruction TLB. This can
13 -------------------
18 - non-Intel processors
20 - Some Atoms (Airmont, Bonnell, Goldmont, GoldmontPlus, Saltwell, Silvermont)
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
27 ------------
32 CVE-2018-12207 Machine Check Error Avoidance on Page Size Change
37 -------
48 There are separate TLBs for instruction (iTLB) and data (dTLB).
55 the linear address, a code fetch that happens on the same linear address may
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| /Documentation/core-api/ |
| D | this_cpu_ops.rst | 15 specific per cpu base and encode that operation in the instruction
24 Read-modify-write operations are of particular interest. Frequently
65 ------------------------------------
71 instruction via a segment register prefix.
80 results in a single instruction::
84 instead of a sequence of calculation of the address and then a fetch
94 The above results in the following single instruction (no lock prefix!)::
114 after the this_cpu instruction is executed. In general this means that
128 ------------------
144 is re-enabled this pointer is usually no longer useful since it may
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| /Documentation/arch/x86/ |
| D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
28 CPU page tables. The device must use ATS again in order the fetch the
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
50 ENQCMD is a new instruction on Intel platforms that atomically submits a
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
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| /Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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| /Documentation/virt/kvm/x86/ |
| D | mmu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
31 - dirty tracking:
33 and framebuffer-based displays
34 - footprint:
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| /Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
37 software as individual single-core processors. In other words, a CPU is an
46 Second, if the processor is multi-core, each core in it is able to follow at
61 Finally, each core in a multi-core processor may be able to follow more than one
62 program in the same time frame (that is, each core may be able to fetch
66 multiple individual single-core "processors", referred to as *hardware threads*
67 (or hyper-threads specifically on Intel hardware), that each can follow one
78 ---------
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| /Documentation/driver-api/pm/ |
| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 fetch and execute instructions: hardware threads, if present, or processor
89 code, and that causes the kernel to run the architecture-specific
91 until the ``->enable()`` governor callback is invoked for that CPU
103 It is expected to reverse any changes made by the ``->enable()``
143 selection made by the ``->select()`` callback (when it was invoked last
152 :c:func:`cpuidle_governor_latency_req()`. Then, the governor's ``->select()``
190 state to start executing the first instruction after a wakeup from it,
217 The analogous ``->enter_s2idle()`` callback in struct cpuidle_state is used
218 only for implementing the suspend-to-idle system-wide power management feature.
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| /Documentation/virt/kvm/ |
| D | api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
107 which instruction set architectures provide this ioctl.
122 -----------------------
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| /Documentation/scsi/ |
| D | ncr53c8xx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 95170 DEUIL LA BARRE - FRANCE
64 10.4 PCI configuration fix-up boot option
81 16.1 Synchronous timings for 53C875 and 53C860 Ultra-SCSI controllers
82 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers
97 - Gerard Roudier <groudier@free.fr>
101 - Wolfgang Stanglmeier <wolf@cologne.de>
102 - Stefan Esser <se@mi.Uni-Koeln.de>
106 - ncr53c8xx generic driver that supports all the SYM53C8XX family including
109 - sym53c8xx enhanced driver (a.k.a. 896 drivers) that drops support of oldest
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