| /drivers/gpu/drm/mediatek/ |
| D | mtk_drm_drv.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
13 #include <linux/dma-mapping.h>
32 #define DRIVER_NAME "mediatek"
33 #define DRIVER_DESC "Mediatek SoC DRM"
49 if (info->num_planes != 1) in mtk_drm_mode_fb_create()
50 return ERR_PTR(-EINVAL); in mtk_drm_mode_fb_create()
325 .min_width = 2, /* 2-pixel align when ethdr is bypassed */
330 { .compatible = "mediatek,mt2701-mmsys",
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| D | mtk_disp_color.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 MediaTek Inc.
11 #include <linux/soc/mediatek/mtk-cmdq.h>
22 #define DISP_COLOR_START(comp) ((comp)->data->color_offset)
34 * struct mtk_disp_color - DISP_COLOR driver structure
46 int mtk_color_clk_enable(struct device *dev) in mtk_color_clk_enable()
50 return clk_prepare_enable(color->clk); in mtk_color_clk_enable()
53 void mtk_color_clk_disable(struct device *dev) in mtk_color_clk_disable()
57 clk_disable_unprepare(color->clk); in mtk_color_clk_disable()
60 void mtk_color_config(struct device *dev, unsigned int w, in mtk_color_config()
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| D | mtk_disp_rdma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
14 #include <linux/soc/mediatek/mtk-cmdq.h>
52 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
78 * struct mtk_disp_rdma - DISP_RDMA driver structure
96 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); in mtk_disp_rdma_irq_handler()
98 if (!priv->vblank_cb) in mtk_disp_rdma_irq_handler()
101 priv->vblank_cb(priv->vblank_cb_data); in mtk_disp_rdma_irq_handler()
106 static void rdma_update_bits(struct device *dev, unsigned int reg, in rdma_update_bits()
110 unsigned int tmp = readl(rdma->regs + reg); in rdma_update_bits()
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| D | mtk_disp_aal.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021 MediaTek Inc.
12 #include <linux/soc/mediatek/mtk-cmdq.h>
40 * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure
53 int mtk_aal_clk_enable(struct device *dev) in mtk_aal_clk_enable()
57 return clk_prepare_enable(aal->clk); in mtk_aal_clk_enable()
60 void mtk_aal_clk_disable(struct device *dev) in mtk_aal_clk_disable()
64 clk_disable_unprepare(aal->clk); in mtk_aal_clk_disable()
67 void mtk_aal_config(struct device *dev, unsigned int w, in mtk_aal_config()
77 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
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| D | mtk_disp_ccorr.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021 MediaTek Inc.
11 #include <linux/soc/mediatek/mtk-cmdq.h>
43 int mtk_ccorr_clk_enable(struct device *dev) in mtk_ccorr_clk_enable()
47 return clk_prepare_enable(ccorr->clk); in mtk_ccorr_clk_enable()
50 void mtk_ccorr_clk_disable(struct device *dev) in mtk_ccorr_clk_disable()
54 clk_disable_unprepare(ccorr->clk); in mtk_ccorr_clk_disable()
57 void mtk_ccorr_config(struct device *dev, unsigned int w, in mtk_ccorr_config()
63 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
65 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
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| /drivers/soc/mediatek/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MediaTek SoC drivers
5 menu "MediaTek SoC drivers"
9 tristate "MediaTek CMDQ Support"
15 Say yes here to add support for the MediaTek Command Queue (CMDQ)
21 tristate "Mediatek Device APC Support"
23 Say yes here to enable support for Mediatek Device APC driver.
30 bool "MediaTek INFRACFG Support"
33 Say yes here to add support for the MediaTek INFRACFG controller. The
35 directly associated to any device.
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| D | mtk-mmsys.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
8 #include <linux/device.h>
13 #include <linux/reset-controller.h>
14 #include <linux/soc/mediatek/mtk-mmsys.h>
16 #include "mtk-mmsys.h"
17 #include "mt8167-mmsys.h"
18 #include "mt8173-mmsys.h"
19 #include "mt8183-mmsys.h"
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| /drivers/gpu/drm/ci/ |
| D | test.yml | 1 .test-rules:
3 - if: '$FD_FARM == "offline" && $RUNNER_TAG =~ /^google-freedreno-/'
5 - if: '$COLLABORA_FARM == "offline" && $RUNNER_TAG =~ /^mesa-ci-x86-64-lava-/'
7 - !reference [.no_scheduled_pipelines-rules, rules]
8 - when: on_success
10 .lava-test:
12 - .test-rules
16 - rm -rf install
17 - tar -xf artifacts/install.tar
18 - mv install/* artifacts/.
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| /drivers/memory/ |
| D | mtk-smi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
6 #include <linux/arm-smccc.h>
9 #include <linux/device.h>
18 #include <linux/soc/mediatek/mtk_sip_svc.h>
19 #include <soc/mediatek/smi.h>
20 #include <dt-bindings/memory/mt2701-larb-port.h>
21 #include <dt-bindings/memory/mtk-memory-port.h>
66 * or non-security.
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| /drivers/media/platform/mediatek/mdp/ |
| D | mtk_mdp_core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Houlong Wei <houlong.wei@mediatek.com>
5 * Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
9 #include <linux/device.h>
25 /* MDP debug log level (0-3). 3 shows all the logs. */
33 .compatible = "mediatek,mt8173-mdp-rdma",
36 .compatible = "mediatek,mt8173-mdp-rsz",
39 .compatible = "mediatek,mt8173-mdp-wdma",
42 .compatible = "mediatek,mt8173-mdp-wrot",
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| /drivers/bluetooth/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "Bluetooth device drivers"
71 bool "MediaTek protocol support"
76 The MediaTek protocol support enables firmware download
77 support and chip initialization for MediaTek Bluetooth
80 Say Y here to compile support for MediaTek protocol.
98 This driver is required if you want to use Bluetooth device with
130 device and host. This protocol is required for most Bluetooth devices
145 device and host. This protocol is required for Bluetooth devices
156 between Bluetooth device and host. This protocol is required for non
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| /drivers/clk/mediatek/ |
| D | reset.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022 MediaTek Inc.
9 #include <linux/reset-controller.h>
22 * enum mtk_reset_version - Version of MediaTek clock reset controller.
25 * @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller.
34 * struct mtk_clk_rst_desc - Description of MediaTek clock reset.
51 * struct mtk_clk_rst_data - Data of MediaTek clock reset controller.
53 * @rcdev: Reset controller device.
63 * mtk_register_reset_controller - Register mediatek clock reset controller with device
64 * @np: Pointer to device.
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| /drivers/media/platform/mediatek/vcodec/decoder/ |
| D | mtk_vcodec_dec_drv.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: PC Chen <pc.chen@mediatek.com>
5 * Tiffany Lin <tiffany.lin@mediatek.com>
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-mem2mem.h>
21 #include <media/videobuf2-dma-contig.h>
22 #include <media/v4l2-device.h>
31 switch (dev->vdec_pdata->hw_arch) { in mtk_vcodec_get_hw_count()
37 mtk_v4l2_vdec_err(ctx, "hw arch %d not supported", dev->vdec_pdata->hw_arch); in mtk_vcodec_get_hw_count()
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| /drivers/cpufreq/ |
| D | mediatek-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
30 * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
31 * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
33 * 100mV < Vsram - Vproc < 200mV
41 struct device *cpu_dev;
42 struct device *cci_dev;
71 if (cpumask_test_cpu(cpu, &info->cpus)) in mtk_cpu_dvfs_info_lookup()
81 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; in mtk_cpufreq_voltage_tracking()
82 struct regulator *proc_reg = info->proc_reg; in mtk_cpufreq_voltage_tracking()
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| /drivers/phy/mediatek/ |
| D | phy-mtk-xfi-tphy.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MediaTek 10GE SerDes XFI T-PHY driver
6 * Bc-bocun Chen <bc-bocun.chen@mediatek.com>
7 * based on mtk_usxgmii.c and mtk_sgmii.c found in MediaTek's SDK (GPL-2.0)
8 * Copyright (c) 2022 MediaTek Inc.
9 * Author: Henry Yen <henry.yen@mediatek.com>
13 #include <linux/device.h>
22 #include "phy-mtk-io.h"
60 * struct mtk_xfi_tphy - run-time data of the XFI phy instance
62 * @dev: Kernel device used to output prefixed debug info.
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| D | phy-mtk-xsphy.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek USB3.1 gen2 xsphy Driver
5 * Copyright (c) 2018 MediaTek Inc.
6 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
10 #include <dt-bindings/phy/phy.h>
19 #include "phy-mtk-io.h"
101 struct device *dev;
112 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
118 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
149 tmp = xsphy->src_ref_clk * xsphy->src_coef; in u2_phy_slew_rate_calibrate()
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| /drivers/regulator/ |
| D | mtk-dvfsrc-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 MediaTek Inc.
13 #include <linux/soc/mediatek/dvfsrc.h>
38 static inline struct device *to_dvfs_regulator_dev(struct regulator_dev *rdev) in to_dvfs_regulator_dev()
40 return rdev_get_dev(rdev)->parent; in to_dvfs_regulator_dev()
43 static inline struct device *to_dvfsrc_dev(struct regulator_dev *rdev) in to_dvfsrc_dev()
45 return to_dvfs_regulator_dev(rdev)->parent; in to_dvfsrc_dev()
58 return -EINVAL; in dvfsrc_get_cmd()
67 struct device *dvfsrc_dev = to_dvfsrc_dev(rdev); in dvfsrc_set_voltage_sel()
81 struct device *dvfsrc_dev = to_dvfsrc_dev(rdev); in dvfsrc_get_voltage_sel()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
64 the netlink mechanism. User-space applications can subscribe to these events
65 for real-time updates on various regulator events.
75 They provide two I2C-controlled DC/DC step-down converters with
101 tristate "Active-semi act8865 voltage regulator"
106 This driver controls a active-semi act8865 voltage output
110 tristate "Active-semi ACT8945A voltage regulator"
113 This driver controls a active-semi ACT8945A voltage regulator
114 via I2C bus. The ACT8945A features three step-down DC/DC converters
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| /drivers/media/platform/mediatek/mdp3/ |
| D | mtk-mdp3-core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
10 #include <media/v4l2-device.h>
11 #include <media/v4l2-mem2mem.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
14 #include "mtk-mdp3-comp.h"
15 #include "mtk-mdp3-vpu.h"
17 #define MDP_MODULE_NAME "mtk-mdp3"
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| /drivers/nvmem/ |
| D | mtk-efuse.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
7 #include <linux/device.h>
11 #include <linux/nvmem-provider.h>
27 void __iomem *addr = priv->base + reg; in mtk_reg_read()
51 size_t sz = strlen(cell->name); in mtk_efuse_fixup_dt_cell_info()
55 * a number with range [0-7] (max 3 bits): post process to use in mtk_efuse_fixup_dt_cell_info()
56 * it in OPP tables to describe supported-hw. in mtk_efuse_fixup_dt_cell_info()
58 if (cell->nbits <= 3 && in mtk_efuse_fixup_dt_cell_info()
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| /drivers/video/backlight/ |
| D | mt6370-backlight.c | 1 // SPDX-License-Identifier: GPL-2.0-only
68 struct device *dev;
82 brightness_val[0] = (brightness - 1) & priv->dim2_mask; in mt6370_bl_update_status()
83 brightness_val[1] = (brightness - 1) >> priv->dim2_shift; in mt6370_bl_update_status()
85 ret = regmap_raw_write(priv->regmap, MT6370_REG_BL_DIM2, in mt6370_bl_update_status()
91 gpiod_set_value(priv->enable_gpio, !!brightness); in mt6370_bl_update_status()
94 return regmap_update_bits(priv->regmap, MT6370_REG_BL_EN, in mt6370_bl_update_status()
105 ret = regmap_read(priv->regmap, MT6370_REG_BL_EN, &enable); in mt6370_bl_get_brightness()
112 ret = regmap_raw_read(priv->regmap, MT6370_REG_BL_DIM2, in mt6370_bl_get_brightness()
117 brightness = brightness_val[1] << priv->dim2_shift; in mt6370_bl_get_brightness()
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| /drivers/char/hw_random/ |
| D | mtk-rng.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Mediatek Hardware Random Number Generator
5 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
47 err = clk_prepare_enable(priv->clk); in mtk_rng_init()
51 val = readl(priv->base + RNG_CTRL); in mtk_rng_init()
53 writel(val, priv->base + RNG_CTRL); in mtk_rng_init()
63 val = readl(priv->base + RNG_CTRL); in mtk_rng_cleanup()
65 writel(val, priv->base + RNG_CTRL); in mtk_rng_cleanup()
67 clk_disable_unprepare(priv->clk); in mtk_rng_cleanup()
75 ready = readl(priv->base + RNG_CTRL) & RNG_READY; in mtk_rng_wait_ready()
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| /drivers/ata/ |
| D | ahci_mtk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * MediaTek AHCI SATA driver
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
21 #define DRV_NAME "ahci-mtk"
46 struct device *dev) in mtk_ahci_platform_resets()
48 struct mtk_ahci_plat *plat = hpriv->plat_data; in mtk_ahci_platform_resets()
52 plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi"); in mtk_ahci_platform_resets()
53 if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER) in mtk_ahci_platform_resets()
54 return PTR_ERR(plat->axi_rst); in mtk_ahci_platform_resets()
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| /drivers/watchdog/ |
| D | mtk_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Mediatek Watchdog Driver
12 #include <dt-bindings/reset/mt2712-resets.h>
13 #include <dt-bindings/reset/mediatek,mt6735-wdt.h>
14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
15 #include <dt-bindings/reset/mt7986-resets.h>
16 #include <dt-bindings/reset/mt8183-resets.h>
17 #include <dt-bindings/reset/mt8186-resets.h>
18 #include <dt-bindings/reset/mt8188-resets.h>
19 #include <dt-bindings/reset/mt8192-resets.h>
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| /drivers/iommu/ |
| D | mtk_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
6 #include <linux/arm-smccc.h>
11 #include <linux/device.h>
17 #include <linux/io-pgtable.h>
30 #include <linux/soc/mediatek/infracfg.h>
31 #include <linux/soc/mediatek/mtk_sip_svc.h>
33 #include <soc/mediatek/smi.h>
35 #include <dt-bindings/memory/mtk-memory-port.h>
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