| /drivers/gpu/drm/ci/ |
| D | test.yml | 1 .test-rules:
3 - if: '$FD_FARM == "offline" && $RUNNER_TAG =~ /^google-freedreno-/'
5 - if: '$COLLABORA_FARM == "offline" && $RUNNER_TAG =~ /^mesa-ci-x86-64-lava-/'
7 - !reference [.no_scheduled_pipelines-rules, rules]
8 - when: on_success
10 .lava-test:
12 - .test-rules
16 - rm -rf install
17 - tar -xf artifacts/install.tar
18 - mv install/* artifacts/.
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| /drivers/soc/mediatek/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MediaTek SoC drivers
5 menu "MediaTek SoC drivers"
9 tristate "MediaTek CMDQ Support"
15 Say yes here to add support for the MediaTek Command Queue (CMDQ)
17 time limitation, such as updating display configuration during the
21 tristate "Mediatek Device APC Support"
23 Say yes here to enable support for Mediatek Device APC driver.
30 bool "MediaTek INFRACFG Support"
33 Say yes here to add support for the MediaTek INFRACFG controller. The
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| /drivers/gpu/drm/mediatek/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "DRM Support for Mediatek SoCs"
18 Choose this option if you have a Mediatek SoCs.
19 The module will be called mediatek-drm
24 tristate "DRM DPTX Support for MediaTek SoCs"
30 DRM/KMS Display Port driver for MediaTek SoCs.
33 tristate "DRM HDMI Support for Mediatek SoCs"
37 DRM/KMS HDMI driver for Mediatek SoCs
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| D | mtk_disp_aal.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021 MediaTek Inc.
12 #include <linux/soc/mediatek/mtk-cmdq.h>
40 * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure
57 return clk_prepare_enable(aal->clk); in mtk_aal_clk_enable()
64 clk_disable_unprepare(aal->clk); in mtk_aal_clk_disable()
77 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
78 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config()
82 * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL
91 if (aal->data && aal->data->has_gamma) in mtk_aal_gamma_get_lut_size()
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| D | mtk_disp_gamma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021 MediaTek Inc.
12 #include <linux/soc/mediatek/mtk-cmdq.h>
54 * struct mtk_disp_gamma - Display Gamma driver structure
71 return clk_prepare_enable(gamma->clk); in mtk_gamma_clk_enable()
78 clk_disable_unprepare(gamma->clk); in mtk_gamma_clk_disable()
85 if (gamma && gamma->data) in mtk_gamma_get_lut_size()
86 return gamma->data->lut_size; in mtk_gamma_get_lut_size()
93 int last_entry = lut_size - 1; in mtk_gamma_lut_is_descending()
102 * SoCs supporting 12-bits LUTs are using a new register layout that does
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| D | mtk_dpi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
11 #include <linux/media-bus-format.h>
16 #include <linux/soc/mediatek/mtk-mmsys.h>
120 * struct mtk_dpi_conf - Configuration of mediatek dpi.
163 u32 tmp = readl(dpi->regs + offset) & ~mask; in mtk_dpi_mask()
166 writel(tmp, dpi->regs + offset); in mtk_dpi_mask()
187 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, in mtk_dpi_config_hsync()
188 dpi->conf->dimension_mask << HPW); in mtk_dpi_config_hsync()
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| D | mtk_dp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019-2022 MediaTek Inc.
7 #include <drm/display/drm_dp_aux_bus.h>
8 #include <drm/display/drm_dp.h>
9 #include <drm/display/drm_dp_helper.h>
18 #include <linux/arm-smccc.h>
23 #include <linux/media-bus-format.h>
24 #include <linux/nvmem-consumer.h>
32 #include <linux/soc/mediatek/mtk_sip_svc.h>
33 #include <sound/hdmi-codec.h>
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| D | mtk_crtc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
7 #include <linux/dma-mapping.h>
11 #include <linux/soc/mediatek/mtk-cmdq.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
29 * struct mtk_crtc - MediaTek specific crtc structure.
69 /* lock for display hardware access */
97 struct drm_crtc *crtc = &mtk_crtc->base; in mtk_crtc_finish_page_flip()
100 if (mtk_crtc->event) { in mtk_crtc_finish_page_flip()
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| /drivers/regulator/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
64 the netlink mechanism. User-space applications can subscribe to these events
65 for real-time updates on various regulator events.
75 They provide two I2C-controlled DC/DC step-down converters with
101 tristate "Active-semi act8865 voltage regulator"
106 This driver controls a active-semi act8865 voltage output
110 tristate "Active-semi ACT8945A voltage regulator"
113 This driver controls a active-semi ACT8945A voltage regulator
114 via I2C bus. The ACT8945A features three step-down DC/DC converters
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| /drivers/pwm/ |
| D | pwm-mtk-disp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * MediaTek display pulse-width-modulation controller driver.
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author: YH Huang <yh.huang@mediatek.com>
25 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
60 void __iomem *address = mdp->base + offset; in mtk_disp_pwm_update_bits()
77 if (state->polarity != PWM_POLARITY_NORMAL) in mtk_disp_pwm_apply()
78 return -EINVAL; in mtk_disp_pwm_apply()
80 if (!state->enabled && mdp->enabled) { in mtk_disp_pwm_apply()
82 mdp->data->enable_mask, 0x0); in mtk_disp_pwm_apply()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
12 display backlights.
48 will be called pwm-ab8500.
67 will be called pwm-apple.
77 will be called pwm-atmel.
85 (Atmel High-end LCD Controller). This PWM output is mainly used
89 will be called pwm-atmel-hlcdc.
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| /drivers/media/platform/mediatek/vcodec/decoder/ |
| D | vdec_vpu_if.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: PC Chen <pc.chen@mediatek.com>
13 * struct vdec_vpu_inst - VPU instance for video codec
23 * @signaled : 1 - Host has received ack message from VPU, 0 - not received
49 * vpu_dec_init - init decoder instance and allocate required resource in VPU.
56 * vpu_dec_start - start decoding, basically the function will be invoked once
66 * vpu_dec_end - end decoding, basically the function will be invoked once
69 * and check if there is a new decoded frame available to display.
76 * vpu_dec_deinit - deinit decoder instance and resource freed in VPU.
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| /drivers/gpu/drm/bridge/ |
| D | parade-ps8640.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 MediaTek Inc.
16 #include <drm/display/drm_dp_aux_bus.h>
17 #include <drm/display/drm_dp_helper.h>
160 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; in _ps8640_wait_hpd_asserted()
181 if (!ret && ps_bridge->need_post_hpd_delay) { in _ps8640_wait_hpd_asserted()
182 ps_bridge->need_post_hpd_delay = false; in _ps8640_wait_hpd_asserted()
192 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; in ps8640_wait_hpd_asserted()
212 struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; in ps8640_aux_transfer_msg()
213 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; in ps8640_aux_transfer_msg()
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| /drivers/mailbox/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
37 will be discovered and possibly managed at probe-time.
71 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
88 This driver provides support for inter-processor communication
176 module will be called mailbox-mpfs.
185 providing an interface for invoking the inter-process communication
198 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
201 An implementation of the APM X-Gene Interprocessor Communication
202 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
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| /drivers/video/backlight/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 This framework adds support for low-level control of LCD.
15 Some framebuffer devices connect to platform-specific LCD modules
16 in order to have a platform-specific way to control the flat panel
90 This driver provides a platform-device registered LCD power
118 tristate "Himax HX-8357 LCD Driver"
121 If you have a HX-8357 LCD panel, say Y to enable its LCD control
139 This framework adds support for low-level control of the LCD
148 bool "Atmel LCDC Contrast-as-Backlight control"
154 export this as a PWM-based backlight control.
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| /drivers/media/rc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
80 tristate "Enable IR raw decoder for the RC-5 protocol"
84 Enable this option if you have IR with RC-5 protocol, and
96 tristate "Enable IR raw decoder for the RC-MM protocol"
98 Enable this option when you have IR with RC-MM protocol, and
100 24 and 32 bits RC-MM variants. You can enable or disable the
102 'rc-mm-12', 'rc-mm-24' and 'rc-mm-32'.
105 will be called ir-rcmm-decoder.
172 module will be called fintek-cir.
181 be called gpio-ir-recv.
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| /drivers/iommu/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
40 sizes at both stage-1 and stage-2, as well as address spaces
41 up to 48-bits in size.
47 Enable self-tests for LPAE page table allocator. This performs
48 a series of page-table consistency checks during boot.
57 Enable support for the ARM Short-descriptor pagetable format.
58 This supports 32-bit virtual and physical addresses mapped using
59 2-level tables with 4KB pages/1MB sections, and contiguous entries
66 Enable self-tests for ARMv7s page table allocator. This performs
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| /drivers/media/platform/mediatek/vcodec/encoder/venc/ |
| D | venc_h264_if.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Jungchang Tsao <jungchang.tsao@mediatek.com>
5 * Daniel Hsiao <daniel.hsiao@mediatek.com>
6 * PoChun Lin <pochun.lin@mediatek.com>
27 * enum venc_h264_frame_type - h264 encoder output bitstream frame type
37 * enum venc_h264_vpu_work_buf - h264 encoder buffer index
53 * enum venc_h264_bs_mode - for bs_mode argument in h264_enc_vpu_encode
62 * struct venc_h264_vpu_config - Structure for h264 encoder configuration
63 * AP-W/R : AP is writer/reader on this item
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| D | venc_vp8_if.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Daniel Hsiao <daniel.hsiao@mediatek.com>
5 * PoChun Lin <pochun.lin@mediatek.com>
27 * enum venc_vp8_vpu_work_buf - vp8 encoder buffer index
47 * struct venc_vp8_vpu_config - Structure for vp8 encoder configuration
48 * AP-W/R : AP is writer/reader on this item
49 * VPU-W/R: VPU is write/reader on this item
53 * to be used for display purposes; must be smaller or equal to buffer
62 * support three temporal layers - 0: 7.5fps 1: 7.5fps 2: 15fps.
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| /drivers/media/platform/mediatek/vcodec/decoder/vdec/ |
| D | vdec_vp8_if.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Jungchang Tsao <jungchang.tsao@mediatek.com>
5 * PC Chen <pc.chen@mediatek.com>
52 * struct vdec_vp8_dec_info - decode misc information
59 * @resolution_changed: resolution change flag 1 - changed, 0 - not changed
60 * @show_frame : display this frame or not
76 * struct vdec_vp8_vsi - VPU shared information
92 * struct vdec_vp8_hw_reg_base - HW register base
110 * struct vdec_vp8_vpu_inst - VPU instance for VP8 decode
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| D | vdec_vp9_if.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Daniel Hsiao <daniel.hsiao@mediatek.com>
5 * Kai-Sean Yang <kai-sean.yang@mediatek.com>
6 * Tiffany Lin <tiffany.lin@mediatek.com>
30 * struct vp9_dram_buf - contains buffer info for vpu
44 * struct vp9_fb_info - contains frame buffer info
54 * struct vp9_ref_cnt_buf - contains reference buffer information
65 * struct vp9_ref_buf - contains current frame's reference buffer information
77 * struct vp9_sf_ref_fb - contains frame buffer info
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| /drivers/gpu/drm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
19 # gallium uses SYS_kcmp for os_same_file_description() to de-duplicate
24 Kernel-level support for the Direct Rendering Infrastructure (DRI)
65 Use dynamic-debug to avoid drm_debug_enabled() runtime overheads.
98 Documentation/dev-tools/kunit/.
113 bool "Display a user-friendly message when a kernel panic occurs"
118 Enable a drm panic handler, which will display a user-friendly message
119 when a kernel panic occurs. It's useful when using a user-space
122 To support Hi-DPI Display, you can enable bigger fonts like
151 the user to reboot the system, or "kmsg" which will display the last
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
6 CFLAGS-$(CONFIG_DRM_USE_DYNAMIC_DEBUG) += -DDYNAMIC_DEBUG_MODULE
9 # --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
10 subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
11 subdir-ccflags-y += $(call cc-option, -Wrestrict)
12 subdir-ccflags-y += -Wmissing-format-attribute
13 subdir-ccflags-y += -Wold-style-definition
14 subdir-ccflags-y += -Wmissing-include-dirs
15 subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
16 subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
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| /drivers/mfd/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
57 tristate "Active-semi ACT8945A"
62 Support for the ACT8945A PMIC from Active-semi. This device
63 features three step-down DC/DC converters and four low-dropout
79 sun4i-gpadc-iio and the hwmon driver iio_hwmon.
82 called sun4i-gpadc.
113 tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down
144 over at91-usart-serial driver and usart-spi-driver. Only one function
160 tristate "Atmel HLCDC (High-end LCD Controller)"
197 tristate "X-Powers AC100"
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| /drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
285 clock. These multi-function devices have two (S2MPS14) or three
286 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
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