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/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-qcom-hw.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
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Dcpufreq-dt.txt11 - None
14 - operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for
17 - clock-latency: Specify the possible maximum transition latency for clock,
19 - voltage-tolerance: Specify the CPU voltage tolerance in percentage.
20 - #cooling-cells:
22 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
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Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
28 - qcom,apq8064
29 - qcom,apq8096
30 - qcom,ipq5332
31 - qcom,ipq6018
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/Documentation/devicetree/bindings/cache/
Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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Dsifive,ccache0.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Composable Cache Controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 The SiFive Composable Cache Controller is used to provide access to fast copies
15 of memory for masters in a Core Complex. The Composable Cache Controller also
16 acts as directory-based coherency manager.
24 - sifive,ccache0
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Dandestech,ax45mp-cache.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Andestech AX45MP L2 Cache Controller
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 A level-2 cache (L2C) is used to improve the system performance by providing
15 a large amount of cache line entries and reasonable access delays. The L2C
16 is shared between cores, and a non-inclusive non-exclusive policy is used.
23 - andestech,ax45mp-cache
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/Documentation/devicetree/bindings/opp/
Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
25 operating-points-v2 table when it is parsed by the OPP framework.
30 - operating-points-v2-krait-cpu
31 - operating-points-v2-kryo-cpu
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Dopp-v1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
19 This binding only supports voltage-frequency pairs.
24 operating-points:
25 $ref: /schemas/types.yaml#/definitions/uint32-matrix
28 - description: Frequency in kHz
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/Documentation/devicetree/bindings/thermal/
Dthermal-cooling-devices.yaml1 # SPDX-License-Identifier: (GPL-2.0)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-cooling-devices.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Amit Kucheria <amitk@kernel.org>
20 - thermal-sensor: device that measures temperature, has SoC-specific bindings
21 - cooling-device: device used to dissipate heat either passively or actively
22 - thermal-zones: a container of the following node types used to describe all
28 - Passive cooling: by means of regulating device performance. A typical
31 - Active cooling: by means of activating devices in order to remove the
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/Documentation/admin-guide/mm/
Dnumaperf.rst10 as CPU cache coherence, but may have different performance. For example,
21 +------------------+ +------------------+
22 | Compute Node 0 +-----+ Compute Node 1 |
24 +--------+---------+ +--------+---------+
26 +--------+---------+ +--------+---------+
28 +------------------+ +--------+---------+
36 performance when accessing a given memory target. Each initiator-target
48 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
49 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
51 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
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Dconcepts.rst7 systems from MMU-less microcontrollers to supercomputers. The memory
52 The tables at the lowest level of the hierarchy contain physical
55 levels. The pointer to the top level page table resides in a
57 register to access the top level page table. The high bits of the
58 virtual address are used to index an entry in the top level page
59 table. That entry is then used to access the next level in the
60 hierarchy with the next bits of the virtual address as the index to
61 that level page table. The lowest bits in the virtual address define
69 processor cycles on the address translation, CPUs maintain a cache of
78 and the third level page tables. In Linux such pages are called
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/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
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Dmarvell,berlin-smp2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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/Documentation/devicetree/bindings/cpu/
Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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/Documentation/scheduler/
Dsched-stats.rst16 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel
17 release). Some counters make more sense to be per-runqueue; other to be
18 per-domain. Note that domains (and their associated information) will only
21 In version 14 of schedstat, there is at least one level of domain
38 Note that any such script will necessarily be version-specific, as the main
43 --------------
50 Next three are schedule() statistics:
57 Next two are try_to_wake_up() statistics:
62 Next three are statistics describing scheduling latency:
71 -----------------
[all …]
/Documentation/ABI/stable/
Dsysfs-devices-node3 Contact: Linux Memory Management list <linux-mm@kvack.org>
9 Contact: Linux Memory Management list <linux-mm@kvack.org>
15 Contact: Linux Memory Management list <linux-mm@kvack.org>
21 Contact: Linux Memory Management list <linux-mm@kvack.org>
27 Contact: Linux Memory Management list <linux-mm@kvack.org>
34 Contact: Linux Memory Management list <linux-mm@kvack.org>
38 node. Each file is detailed next.
42 Contact: Linux Memory Management list <linux-mm@kvack.org>
48 Contact: Linux Memory Management list <linux-mm@kvack.org>
54 Contact: Linux Memory Management list <linux-mm@kvack.org>
[all …]
/Documentation/admin-guide/device-mapper/
Dvdo.rst1 .. SPDX-License-Identifier: GPL-2.0-only
3 dm-vdo
6 The dm-vdo (virtual data optimizer) device mapper target provides
7 block-level deduplication, compression, and thin provisioning. As a device
20 https://github.com/dm-vdo/vdo/
23 next time it is started. In cases where it encountered an unrecoverable
25 enter or come up in read-only mode. Because read-only mode is indicative of
26 data-loss, a positive action must be taken to bring vdo out of read-only
28 prepare a read-only vdo to exit read-only mode. After running this tool,
29 the vdo target will rebuild its metadata the next time it is
[all …]
/Documentation/arch/arm/
Dcluster-pm-race-avoidance.rst2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
[all …]
/Documentation/core-api/
Dcachetlb.rst2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
78 address space is available via vma->vm_mm. Also, one may
[all …]
Ddma-attributes.rst6 defined in linux/dma-mapping.h.
9 ----------------------
19 ----------------------
29 --------------------------
33 such mapping is non-trivial task and consumes very limited resources
47 ----------------------
57 (usually it means that the cache has been flushed or invalidated
58 depending on the dma direction). However, next calls to
60 same synchronization operation on the CPU cache. CPU cache synchronization
64 the CPU cache for the given buffer assuming that it has been already
[all …]
/Documentation/filesystems/
Dcoda.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Coda Kernel-Venus Interface
10 Coda -- this document describes the client kernel-Venus interface.
16 For user level software needed to run Coda:
20 To run Coda you need to get a user level cache manager for the client,
25 The server needs a user level server and at present does not depend on
35 level filesystem code needed for the operation of the Coda file sys-
49 4. The interface at the call level
98 A key component in the Coda Distributed File System is the cache
105 client cache and makes remote procedure calls to Coda file servers and
[all …]
D9p.rst1 .. SPDX-License-Identifier: GPL-2.0
26 http://xcpu.org/papers/xcpu-talk.pdf
30 http://xcpu.org/papers/cellfs-talk.pdf
33 * VirtFS: A Virtualization Aware File System pass-through
34 https://kernel.org/doc/ols/2010/ols2010-pages-109-120.pdf
41 mount -t 9p 10.10.1.2 /mnt/9
45 mount -t 9p `namespace`/acme /mnt/9 -o trans=unix,uname=$USER
49 mount -t 9p -o trans=virtio <mount_tag> /mnt/9
61 mount -t 9p -o trans=usbg,aname=/path/to/fs <device> /mnt/9
65 …root=<device> rootfstype=9p rootflags=trans=usbg,cache=loose,uname=root,access=0,dfltuid=0,dfltgid…
[all …]
/Documentation/arch/x86/
Dresctrl.rst1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
22 CAT (Cache Allocation Technology) "cat_l3", "cat_l2"
24 CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc"
38 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrl
43 Enable code/data prioritization in L3 cache allocations.
45 Enable code/data prioritization in L2 cache allocations.
56 monitoring, only control, or both monitoring and control. Cache
[all …]
/Documentation/kernel-hacking/
Dlocking.rst37 +------------------------------------+------------------------------------+
41 +------------------------------------+------------------------------------+
43 +------------------------------------+------------------------------------+
45 +------------------------------------+------------------------------------+
47 +------------------------------------+------------------------------------+
49 +------------------------------------+------------------------------------+
51 +------------------------------------+------------------------------------+
57 +------------------------------------+------------------------------------+
61 +------------------------------------+------------------------------------+
63 +------------------------------------+------------------------------------+
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