Searched +full:non +full:- +full:configurable (Results 1 – 25 of 66) sorted by relevance
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| /Documentation/hwmon/ |
| D | shtc1.rst | 41 -----------
48 address 0x70. See Documentation/i2c/instantiating-devices.rst for methods to
51 There are two options configurable by means of shtc1_platform_data:
54 non-blocking mode. Blocking mode will guarantee the fastest result but
55 the I2C bus will be busy during that time. By default, non-blocking mode
56 is used. Make sure clock-stretching works properly on your device if you
61 sysfs-Interface
62 ---------------
65 - temperature input
67 - humidity input
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| D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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| D | bt1-pvt.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
3 Kernel driver bt1-pvt
8 * Baikal-T1 PVT sensor (in SoC)
10 Prefix: 'bt1-pvt'
12 Addresses scanned: -
21 -----------
24 embedded into Baikal-T1 process, voltage and temperature sensors. PVT IP-core
29 compile-time configurable due to the hardware interface implementation
40 in alarm-less configuration the data conversion is performed by the driver
41 on demand when read operation is requested via corresponding _input-file.
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| /Documentation/userspace-api/media/mediactl/ |
| D | media-ioc-setup-link.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 MEDIA_IOC_SETUP_LINK - Modify the properties of a link
40 The only configurable property is the ``ENABLED`` link flag to
50 non-dynamic link will return an ``EBUSY`` error code.
58 On success 0 is returned, on error -1 and the ``errno`` variable is set
60 :ref:`Generic Error Codes <gen-errors>` chapter.
64 non-existing link, or the link is immutable and an attempt to modify
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | microchip,pic32-evic.txt | 9 External interrupts have a software configurable edge polarity. Non external
14 -------------------
16 - compatible: Should be "microchip,pic32mzda-evic"
17 - reg: Specifies physical base address and size of register range.
18 - interrupt-controller: Identifies the node as an interrupt controller.
19 - #interrupt cells: Specifies the number of cells used to encode an interrupt
25 hw_irq - represents the hardware interrupt number as in the data sheet.
26 irq_type - is used to describe the type and polarity of an interrupt. For
27 internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
32 -------------------
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| D | msi.txt | 14 - The doorbell (the MMIO address written to).
19 - The payload (the value written to the doorbell).
24 - Sideband information accompanying the write.
26 Typically this is neither configurable nor probeable, and depends on the path
38 --------------------
40 - msi-controller: Identifies the node as an MSI controller.
43 --------------------
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
50 The meaning of the msi-specifier is defined by the device tree binding of
59 information may not be configurable.
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| /Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
47 In fiber mode, auto-negotiation is disabled and the PHY can only work in
48 100base-fx (full and half duplex) modes.
50 - coma-mode-gpios: If present the given gpio will be deasserted when the
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-static-funnel.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
23 The Coresight static funnel merges 2-8 trace sources into a single trace
28 const: arm,coresight-static-funnel
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| D | arm,coresight-static-replicator.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
28 const: arm,coresight-static-replicator
30 power-domains:
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| /Documentation/PCI/endpoint/ |
| D | pci-ntb-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-ntb function driver
12 configuration and internals of NTB using configurable endpoints see
13 Documentation/PCI/endpoint/pci-ntb-function.rst
19 ---------------------------
27 2900000.pcie-ep 2910000.pcie-ep
32 2900000.pcie-ep 2910000.pcie-ep
36 -------------------------
40 # ls /sys/bus/pci-epf/drivers
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| D | pci-vntb-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-vntb function driver
12 configuration and internals of NTB using configurable endpoints see
13 Documentation/PCI/endpoint/pci-vntb-function.rst
19 ---------------------------
32 -------------------------
36 # ls /sys/bus/pci-epf/drivers
45 Creating pci-epf-vntb Device
46 ----------------------------
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| /Documentation/driver-api/gpio/ |
| D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
44 input de-glitch/debounce logic, sometimes with software controls.
46 - Inputs can often be used as IRQ signals, often edge triggered but
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| /Documentation/dev-tools/ |
| D | gpio-sloppy-logic-analyzer.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 This document briefly describes how to run the GPIO based in-kernel sloppy
22 Another feature is to snoop on on-chip peripherals if the I/O cells of these
26 control subsystem such pin controllers are called "non-strict": a certain pin
31 non-deterministic code paths and non-maskable interrupts. It is called 'sloppy'
47 i2c-analyzer {
48 compatible = "gpio-sloppy-logic-analyzer";
49 probe-gpios = <&gpio6 21 GPIO_OPEN_DRAIN>, <&gpio6 4 GPIO_OPEN_DRAIN>;
50 probe-names = "SCL", "SDA";
60 The logic analyzer is configurable via files in debugfs. However, it is
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| D | kfence.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Kernel Electric-Fence (KFENCE)
7 Kernel Electric-Fence (KFENCE) is a low-overhead sampling-based memory safety
8 error detector. KFENCE detects heap out-of-bounds access, use-after-free, and
9 invalid-free errors.
15 non-production test workloads. One way to quickly achieve a large enough total
19 -----
26 ``kfence.sample_interval`` to non-zero value), configure the kernel with::
40 guarded by KFENCE. The default is configurable via the Kconfig option
46 causes CPU wake-ups when the system is completely idle. This may be undesirable
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| /Documentation/devicetree/bindings/leds/ |
| D | common.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
25 led-sources:
30 $ref: /schemas/types.yaml#/definitions/uint32-array
35 from the header include/dt-bindings/leds/common.h. If there is no
42 the header include/dt-bindings/leds/common.h. If there is no matching
48 function-enumerator:
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| /Documentation/ABI/obsolete/ |
| D | sysfs-bus-iio | 3 Contact: linux-iio@vger.kernel.org
14 Contact: linux-iio@vger.kernel.org
26 Contact: linux-iio@vger.kernel.org
32 the bufferY directory, to be configurable per buffer.
50 What: /sys/.../iio:deviceX/scan_elements/in_voltageY-voltageZ_en
62 Contact: linux-iio@vger.kernel.org
67 the bufferY directory, to be configurable per buffer.
86 Contact: linux-iio@vger.kernel.org
89 and hence the form in which it is read from user-space.
109 the bufferY directory, to be configurable per buffer.
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| /Documentation/driver-api/media/ |
| D | camera-sensor.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 This document covers the in-kernel APIs only. For the best practices on
12 CSI-2, parallel and BT.656 buses
13 --------------------------------
15 Please see :ref:`transmitter-receiver`.
18 ---------------
29 elsewhere. Therefore only the pre-determined frequencies are configurable by the
35 Read the ``clock-frequency`` _DSD property to denote the frequency. The driver
41 The preferred way to achieve this is using ``assigned-clocks``,
42 ``assigned-clock-parents`` and ``assigned-clock-rates`` properties. See the
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| /Documentation/admin-guide/ |
| D | lockup-watchdogs.rst | 14 "softlockup_panic" (see "Documentation/admin-guide/kernel-parameters.rst" for
26 (see "Documentation/admin-guide/kernel-parameters.rst" for details).
43 (compile-time initialized to 10 and configurable through sysctl of the
64 event. The right value for a particular environment is a trade-off
77 to continue to run on the housekeeping (non-tickless) cores means
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| /Documentation/arch/powerpc/ |
| D | pci_iov_resource_on_powernv.rst | 57 - For DMA we then provide an entire address space for each PE that can
60 translation table), which has various configurable characteristics
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
70 - Error messages just use the RTT.
77 First what they have in common: they forward a configurable portion of
81 - The M32 window:
86 them with a configurable value. This is typically used to generate
87 32-bit PCIe accesses. We configure that window at boot from FW and
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | ramoops.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/ramoops.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 recovered after a reboot. This is a child-node of "/reserved-memory", and
16 as kernel log messages, or for optional ECC error-correction data. The total
20 records. These records have a configurable size, with a size of 0 indicating
23 At least one of "record-size", "console-size", "ftrace-size", or "pmsg-size"
24 must be set non-zero, but are otherwise optional as listed below.
27 - Kees Cook <keescook@chromium.org>
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| /Documentation/admin-guide/pm/ |
| D | intel_pstate.rst | 1 .. SPDX-License-Identifier: GPL-2.0
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
66 -----------
69 hardware-managed P-states (HWP) support. If it works in this mode, the
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| /Documentation/networking/device_drivers/ethernet/marvell/ |
| D | octeontx2.rst | 1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
12 - `Overview`_
13 - `Drivers`_
14 - `Basic packet flow`_
15 - `Devlink health reporters`_
16 - `Quality of service`_
23 PCI-compatible physical and virtual functions. Each functional block
31 - Network pool or buffer allocator (NPA)
32 - Network interface controller (NIX)
33 - Network parser CAM (NPC)
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| /Documentation/admin-guide/mm/ |
| D | nommu-mmap.rst | 2 No-MMU memory mapping support
5 The kernel has limited support for memory mapping under no-MMU conditions, such
16 The behaviour is similar between the MMU and no-MMU cases, but not identical;
21 In the MMU case: VM regions backed by arbitrary pages; copy-on-write
24 In the no-MMU case: VM regions backed by arbitrary contiguous runs of
31 the no-MMU case doesn't support these, behaviour is identical to
39 In the no-MMU case:
41 - If one exists, the kernel will re-use an existing mapping to the
45 - If possible, the file mapping will be directly on the backing device
50 - If the backing device can't or won't permit direct sharing,
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| /Documentation/scheduler/ |
| D | sched-rt-group.rst | 2 Real-Time group scheduling
12 2.1 System-wide settings
33 are real-time processes).
40 ---------------
42 Real-time scheduling is all about determinism, a group has to be able to rely on
44 multiple groups of real-time tasks, each group must be assigned a fixed portion
45 of the CPU time available. Without a minimum guarantee a real-time group can
50 ----------------
53 in a given period. We allocate this "run time" for each real-time group which
54 the other real-time groups will not be permitted to use.
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| /Documentation/userspace-api/ |
| D | spec_ctrl.rst | 5 Quite some CPUs have speculation-related misfeatures which are in
10 forms. Some of these mitigations are compile-time configurable and some
25 -----------------------
28 which is selected with arg2 of prctl(2). The return value uses bits 0-3 with
48 If PR_SPEC_PRCTL is set, then the per-task control of the mitigation is
55 -----------------------
63 ------------------
74 -----------------------------------
91 -------------------------------
92 - PR_SPEC_STORE_BYPASS: Speculative Store Bypass
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