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/Documentation/core-api/
Dthis_cpu_ops.rst8 this_cpu operations are a way of optimizing access to per cpu
9 variables associated with the *currently* executing processor. This is
11 the cpu permanently stored the beginning of the per cpu area for a
12 specific processor).
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
21 processor is not changed between the calculation of the address and
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
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/Documentation/devicetree/bindings/remoteproc/
Dti,keystone-rproc.txt5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
15 Each DSP Core sub-system is represented as a single DT node, and should also
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
22 --------------------
25 - compatible: Should be one of the following,
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Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
19 controller, a dedicated local power/sleep controller etc. The DSP processor
20 cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
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Damlogic,meson-mx-ao-arc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/amlogic,meson-mx-ao-arc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson AO ARC Remote Processor
11 controller for always-on operations, typically used for managing
17 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
22 - enum:
23 - amlogic,meson8-ao-arc
24 - amlogic,meson8b-ao-arc
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Dti,davinci-rproc.txt4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5 is used to offload some of the processor-intensive tasks or algorithms, for
8 The processor cores in the sub-system usually contain additional sub-modules
10 controller, a dedicated local power/sleep controller etc. The DSP processor
15 Each DSP Core sub-system is represented as a single DT node.
18 --------------------
21 - compatible: Should be one of the following,
22 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
24 - reg: Should contain an entry for each value in 'reg-names'.
27 the parent node's '#address-cells' and '#size-cells' values.
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Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx R5F processor subsystem
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
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/Documentation/devicetree/bindings/timer/
Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - enum:
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Darm,twd-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
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Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/Documentation/admin-guide/pm/
Dintel_pstate.rst1 .. SPDX-License-Identifier: GPL-2.0
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
63 the processor.
66 -----------
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Dintel_idle.rst1 .. SPDX-License-Identifier: GPL-2.0
20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
47 Each ``MWAIT`` hint value is interpreted by the processor as a license to
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/Documentation/devicetree/bindings/watchdog/
Dzii,rave-sp-wdt.txt1 Zodiac Inflight Innovations RAVE Supervisory Processor Watchdog Bindings
4 watchdog functionality of RAVE Supervisory Processor. It is expected
7 Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
11 - compatible: Depending on wire protocol implemented by RAVE SP
13 - "zii,rave-sp-watchdog"
14 - "zii,rave-sp-watchdog-legacy"
18 - wdt-timeout: Two byte nvmem cell specified as per
23 rave-sp {
24 compatible = "zii,rave-sp-rdu1";
25 current-speed = <38400>;
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Darm,twd-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
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/Documentation/arch/x86/
Dintel-hfi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Hardware-Feedback Interface for scheduling on Intel Hardware
8 --------
11 IA-32 Architectures Software Developer's Manual (Intel SDM) Volume 3 Section
19 -------------------------------
23 capability is given as a unit-less quantity in the range [0-255]. Higher values
30 at which these capabilities are updated is specific to each processor model. On
39 capabilities of a given logical processor becomes zero, it is an indication that
41 that processor for performance or energy efficiency reasons, respectively.
44 --------------------------------
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/Documentation/translations/zh_CN/
Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - 在翻译过程中遇到陌生词汇，且尚无翻译先例的；
11 - 在审阅过程中，针对某词条出现了不同的翻译意见；
12 - 使用频率不高的词条和首字母缩写类型的词条；
13 - 已经存在且有歧义的词条翻译。
26 * MIPS: 每秒百万指令。（Millions of Instructions Per Second）,注意与mips指令集区分开。
29 * OpenCAPI: 开放相干加速器处理器接口。（Open Coherent Accelerator Processor Interface）
32 * PELT: 实体负载跟踪。（Per-Entity Load Tracking）
/Documentation/admin-guide/acpi/
Dcppc_sysfs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Collaborative Processor Performance Control (CPPC)
13 performance of a logical processor on a contiguous and abstract performance
15 to request performance levels and to measure per-cpu delivered performance.
27 $ ls -lR /sys/devices/system/cpu/cpu0/acpi_cppc/
30 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
33 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
34 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf
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/Documentation/devicetree/bindings/nvmem/
Dfsl,layerscape-sfp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/fsl,layerscape-sfp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape Security Fuse Processor
10 - Michael Walle <michael@walle.cc>
13 SFP is the security fuse processor which among other things provides a
14 unique identifier per part.
17 - $ref: nvmem.yaml#
18 - $ref: nvmem-deprecated-cells.yaml
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/Documentation/userspace-api/accelerators/
Docxl.rst2 OpenCAPI (Open Coherent Accelerator Processor Interface)
6 at being low-latency and high-bandwidth. The specification is
14 OpenCAPI is known in linux as 'ocxl', as the open, processor-agnostic
20 High-level view
24 be implemented on top of a physical link. Any processor or device
29 +-----------+ +-------------+
32 | Processor | | Function |
33 | | +--------+ | Unit | +--------+
34 | |--| Memory | | (AFU) |--| Memory |
35 | | +--------+ | | +--------+
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/Documentation/trace/rv/
Dmonitor_wwnr.rst4 - Name: wwrn - wakeup while not running
5 - Type: per-task deterministic automaton
6 - Author: Daniel Bristot de Oliveira <bristot@kernel.org>
9 -----------
11 This is a per-task sample monitor, with the following
17 wakeup +-------------+
18 +--------- | |
20 +--------> | | <+
21 +-------------+ |
25 +-------------+ |
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/Documentation/admin-guide/perf/
Darm-ccn.rst5 CCN-504 is a ring-bus interconnect consisting of 11 crosspoints
11 -----------------
29 Crosspoint watchpoint-based events (special "event" value 0xfe)
43 a single CPU ID, of the processor which will be used to handle all
45 request the events on this processor (if not, the perf_event->cpu value
46 will be overwritten anyway). In case of this processor being offlined,
57 / # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \
61 not work. Per-task (without "-a") perf sessions are not supported.
Dthunderx2-pmu.rst5 The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
7 Cavium Coherent Processor Interconnect (CCPI2).
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
17 The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
28 work. Per-task perf sessions are also not supported.
32 # perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
34 # perf stat -a -e \
40 # perf stat -a -e \
/Documentation/devicetree/bindings/interrupt-controller/
Dopenrisc,ompic.txt1 Open Multi-Processor Interrupt Controller
5 - compatible : This should be "openrisc,ompic"
6 - reg : Specifies base physical address and size of the register space. The
8 to handle, this should be set to 8 bytes per cpu core.
9 - interrupt-controller : Identifies the node as an interrupt controller.
10 - #interrupt-cells : This should be set to 0 as this will not be an irq
12 - interrupts : Specifies the interrupt line to which the ompic is wired.
16 ompic: interrupt-controller@98000000 {
19 interrupt-controller;
20 #interrupt-cells = <0>;
/Documentation/devicetree/bindings/media/
Dcoda.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Chips&Media Coda multi-standard codec IP
10 - Philipp Zabel <p.zabel@pengutronix.de>
12 description: |-
19 - items:
20 - const: fsl,imx27-vpu
21 - const: cnm,codadx6
22 - items:
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/Documentation/hwmon/
Dcoretemp.rst11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
13 - 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
14 - 0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
15 - 0x36 (Cedar Trail Atom)
19 Intel 64 and IA-32 Architectures Software Developer's Manual
27 -----------
30 inside Intel CPUs. This driver can read both the per-core and per-package
31 temperature using the appropriate sensors. The per-package sensor is new;
40 Temperature known as TjMax is the maximum junction temperature of processor,
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