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/drivers/phy/rockchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
[all …]
/drivers/gpu/drm/ci/
Dtest.yml1 .test-rules:
3 - if: '$FD_FARM == "offline" && $RUNNER_TAG =~ /^google-freedreno-/'
5 - if: '$COLLABORA_FARM == "offline" && $RUNNER_TAG =~ /^mesa-ci-x86-64-lava-/'
7 - !reference [.no_scheduled_pipelines-rules, rules]
8 - when: on_success
10 .lava-test:
12 - .test-rules
16 - rm -rf install
17 - tar -xf artifacts/install.tar
18 - mv install/* artifacts/.
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/drivers/gpu/drm/rockchip/
Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip SoC DP (Display Port) interface driver.
5 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
24 #include <drm/display/drm_dp_helper.h>
45 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
89 reset_control_assert(dp->rst); in rockchip_dp_pre_init()
91 reset_control_deassert(dp->rst); in rockchip_dp_pre_init()
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Drockchip_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
9 #include <linux/dma-mapping.h>
28 #include <asm/dma-iommu.h>
39 #define DRIVER_NAME "rockchip"
40 #define DRIVER_DESC "RockChip Soc DRM"
55 struct rockchip_drm_private *private = drm_dev->dev_private; in rockchip_drm_dma_attach_device()
58 if (!private->domain) in rockchip_drm_dma_attach_device()
70 ret = iommu_attach_device(private->domain, dev); in rockchip_drm_dma_attach_device()
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Drockchip_drm_drv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
25 * display output interface supported by rockchip lcdc
61 * Rockchip drm private structure.
65 * @mm_lock: protect drm_mm on multi-threads.
Ddw_hdmi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
60 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
211 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
214 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
215 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
216 drm_err(hdmi, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
217 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
220 hdmi->ref_clk = devm_clk_get_optional_enabled(hdmi->dev, "ref"); in rockchip_hdmi_parse_dt()
221 if (!hdmi->ref_clk) in rockchip_hdmi_parse_dt()
[all …]
Drk3066_hdmi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Zheng Yang <zhengyang@rock-chips.com>
25 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
74 return readl_relaxed(hdmi->regs + offset); in hdmi_readb()
79 writel_relaxed(val, hdmi->regs + offset); in hdmi_writeb()
95 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE; in rk3066_hdmi_i2c_init()
117 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode); in rk3066_hdmi_set_power_mode()
118 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode); in rk3066_hdmi_set_power_mode()
133 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode); in rk3066_hdmi_set_power_mode()
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Dinno_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Zheng Yang <zhengyang@rock-chips.com>
5 * Yakir Yang <ykk@rock-chips.com>
25 #include <drm/display/drm_hdmi_helper.h>
26 #include <drm/display/drm_hdmi_state_helper.h>
100 * Cb = -0.291G - 0.148R + 0.439B + 128
102 * Cr = -0.368G + 0.439R - 0.071B + 128
111 * Cb = - 0.338G - 0.101R + 0.439B + 128
113 * Cr = - 0.399G + 0.439R - 0.040B + 128
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Dcdn-dp-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
4 * Copyright (C) 2016 ROCKCHIP, Inc.
10 #include <drm/display/drm_dp_helper.h>
13 #include <sound/hdmi-codec.h>
Drockchip_lvds.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
5 * Mark Yao <mark.yao@rock-chips.com>
6 * Sandy Huang <hjc@rock-chips.com>
38 * struct rockchip_lvds_soc_data - rockchip lvds Soc private data
79 writel_relaxed(val, lvds->regs + offset); in rk3288_writel()
80 if (lvds->output == DISPLAY_OUTPUT_LVDS) in rk3288_writel()
82 writel_relaxed(val, lvds->regs + offset + RK3288_LVDS_CH1_OFFSET); in rk3288_writel()
87 if (strncmp(s, "jeida-18", 8) == 0) in rockchip_lvds_name_to_format()
89 else if (strncmp(s, "jeida-24", 8) == 0) in rockchip_lvds_name_to_format()
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Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
274 /* dual-channel */
365 return -EINVAL; in max_mbps_to_parameter()
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Drockchip_rgb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
5 * Sandy Huang <hjc@rock-chips.com>
9 #include <linux/media-bus-format.h>
12 #include <drm/display/drm_dp_helper.h>
39 struct drm_connector *connector = conn_state->connector; in rockchip_rgb_encoder_atomic_check()
40 struct drm_display_info *info = &connector->display_info; in rockchip_rgb_encoder_atomic_check()
43 if (info->num_bus_formats) in rockchip_rgb_encoder_atomic_check()
44 bus_format = info->bus_formats[0]; in rockchip_rgb_encoder_atomic_check()
50 s->output_mode = ROCKCHIP_OUT_MODE_P666; in rockchip_rgb_encoder_atomic_check()
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Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author: Chris Zhong <zyw@rock-chips.com>
16 #include <sound/hdmi-codec.h>
18 #include <drm/display/drm_dp_helper.h>
25 #include "cdn-dp-core.h"
26 #include "cdn-dp-reg.h"
49 #define CDN_DP_FIRMWARE "rockchip/dptx.bin"
61 { .compatible = "rockchip,rk3399-cdn-dp",
73 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
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/drivers/gpu/drm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 # gallium uses SYS_kcmp for os_same_file_description() to de-duplicate
24 Kernel-level support for the Direct Rendering Infrastructure (DRI)
65 Use dynamic-debug to avoid drm_debug_enabled() runtime overheads.
98 Documentation/dev-tools/kunit/.
113 bool "Display a user-friendly message when a kernel panic occurs"
118 Enable a drm panic handler, which will display a user-friendly message
119 when a kernel panic occurs. It's useful when using a user-space
122 To support Hi-DPI Display, you can enable bigger fonts like
151 the user to reboot the system, or "kmsg" which will display the last
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 CFLAGS-$(CONFIG_DRM_USE_DYNAMIC_DEBUG) += -DDYNAMIC_DEBUG_MODULE
9 # --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
10 subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
11 subdir-ccflags-y += $(call cc-option, -Wrestrict)
12 subdir-ccflags-y += -Wmissing-format-attribute
13 subdir-ccflags-y += -Wold-style-definition
14 subdir-ccflags-y += -Wmissing-include-dirs
15 subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
16 subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
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/drivers/mailbox/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
37 will be discovered and possibly managed at probe-time.
71 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
85 bool "Rockchip Soc Integrated Mailbox Support"
88 This driver provides support for inter-processor communication
89 between CPU cores and MCU processor on Some Rockchip SOCs.
91 Say Y here if you want to use the Rockchip Mailbox support.
176 module will be called mailbox-mpfs.
185 providing an interface for invoking the inter-process communication
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/drivers/iommu/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
40 sizes at both stage-1 and stage-2, as well as address spaces
41 up to 48-bits in size.
47 Enable self-tests for LPAE page table allocator. This performs
48 a series of page-table consistency checks during boot.
57 Enable support for the ARM Short-descriptor pagetable format.
58 This supports 32-bit virtual and physical addresses mapped using
59 2-level tables with 4KB pages/1MB sections, and contiguous entries
66 Enable self-tests for ARMv7s page table allocator. This performs
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/drivers/pwm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
12 display backlights.
48 will be called pwm-ab8500.
67 will be called pwm-apple.
77 will be called pwm-atmel.
85 (Atmel High-end LCD Controller). This PWM output is mainly used
89 will be called pwm-atmel-hlcdc.
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/drivers/media/platform/rockchip/rkisp1/
Drkisp1-dev.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip ISP1 Driver - Base driver
7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-mc.h>
23 #include "rkisp1-common.h"
24 #include "rkisp1-csi.h"
28 * -----------
36 * RBG display ready image
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/drivers/power/supply/
Drk817_charger.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Charger Driver for Rockchip rk817
12 #include <linux/devm-helpers.h>
68 * soc - state of charge - like the BSP this is stored as a percentage,
69 * to the thousandth. BSP has a display state of charge (dsoc) and a
98 /* Values updated periodically by driver for display. */
143 return -EINVAL; in rk817_chg_cur_to_reg()
166 return -EINVAL; in rk817_chg_cur_from_reg()
177 regmap_bulk_read(charger->rk808->regmap, RK817_GAS_GAUGE_VCALIB0_H, in rk817_bat_calib_vol()
181 regmap_bulk_read(charger->rk808->regmap, RK817_GAS_GAUGE_VCALIB1_H, in rk817_bat_calib_vol()
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/drivers/gpu/drm/panel/
Dpanel-kingdisplay-kd097d04.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
185 err = mipi_dsi_dcs_set_display_off(kingdisplay->link); in kingdisplay_panel_disable()
187 dev_err(panel->dev, "failed to set display off: %d\n", err); in kingdisplay_panel_disable()
197 err = mipi_dsi_dcs_enter_sleep_mode(kingdisplay->link); in kingdisplay_panel_unprepare()
199 dev_err(panel->dev, "failed to enter sleep mode: %d\n", err); in kingdisplay_panel_unprepare()
206 gpiod_set_value_cansleep(kingdisplay->enable_gpio, 0); in kingdisplay_panel_unprepare()
208 err = regulator_disable(kingdisplay->supply); in kingdisplay_panel_unprepare()
221 gpiod_set_value_cansleep(kingdisplay->enable_gpio, 0); in kingdisplay_panel_prepare()
223 err = regulator_enable(kingdisplay->supply); in kingdisplay_panel_prepare()
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Dpanel-innolux-p079zca.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
59 err = mipi_dsi_dcs_set_display_off(innolux->link); in innolux_panel_unprepare()
61 dev_err(panel->dev, "failed to set display off: %d\n", err); in innolux_panel_unprepare()
63 err = mipi_dsi_dcs_enter_sleep_mode(innolux->link); in innolux_panel_unprepare()
65 dev_err(panel->dev, "failed to enter sleep mode: %d\n", err); in innolux_panel_unprepare()
69 if (innolux->desc->sleep_mode_delay) in innolux_panel_unprepare()
70 msleep(innolux->desc->sleep_mode_delay); in innolux_panel_unprepare()
72 gpiod_set_value_cansleep(innolux->enable_gpio, 0); in innolux_panel_unprepare()
74 if (innolux->desc->power_down_delay) in innolux_panel_unprepare()
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/drivers/clk/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
285 clock. These multi-function devices have two (S2MPS14) or three
286 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
[all …]
/drivers/regulator/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
64 the netlink mechanism. User-space applications can subscribe to these events
65 for real-time updates on various regulator events.
75 They provide two I2C-controlled DC/DC step-down converters with
101 tristate "Active-semi act8865 voltage regulator"
106 This driver controls a active-semi act8865 voltage output
110 tristate "Active-semi ACT8945A voltage regulator"
113 This driver controls a active-semi ACT8945A voltage regulator
114 via I2C bus. The ACT8945A features three step-down DC/DC converters
[all …]
/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_reg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Analogix DP (Display port) core register interface driver.
31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
61 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
69 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
[all …]

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