Searched +full:system +full:- +full:cache +full:- +full:controller (Results 1 – 25 of 67) sorted by relevance
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| /Documentation/devicetree/bindings/cache/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
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| D | andestech,ax45mp-cache.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Andestech AX45MP L2 Cache Controller
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 A level-2 cache (L2C) is used to improve the system performance by providing
15 a large amount of cache line entries and reasonable access delays. The L2C
16 is shared between cores, and a non-inclusive non-exclusive policy is used.
23 - andestech,ax45mp-cache
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| D | baikal,bt1-l2-ctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
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| D | qcom,llcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Bjorn Andersson <andersson@kernel.org>
13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
16 common pool of memory. Cache memory is divided into partitions called slices
23 - qcom,qdu1000-llcc
24 - qcom,sa8775p-llcc
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| /Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
20 provides the number of bits that the memory controller expects:
37 A memory controller channel, responsible to communicate with a group of
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
44 controller. Typically, it contains two channels. Two channels at the
52 * Single-channel
54 The data accessed by the memory controller is contained into one dimm
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
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| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| /Documentation/devicetree/bindings/mtd/ |
| D | flctl-nand.txt | 1 FLCTL NAND controller
4 - compatible : "renesas,shmobile-flctl-sh7372"
5 - reg : Address range of the FLCTL
6 - interrupts : flste IRQ number
7 - nand-bus-width : bus width to NAND chip
10 - dmas: DMA specifier(s)
11 - dma-names: name for each DMA specifier. Valid names are
17 The device tree may optionally contain sub-nodes describing partitions of the
23 #address-cells = <1>;
24 #size-cells = <1>;
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| D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
17 registers and for its data input/output buffer. On some SoCs, this controller
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| /Documentation/arch/x86/ |
| D | resctrl.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
22 CAT (Cache Allocation Technology) "cat_l3", "cat_l2"
24 CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc"
36 To use the feature mount the file system::
38 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrl
43 Enable code/data prioritization in L3 cache allocations.
45 Enable code/data prioritization in L2 cache allocations.
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| D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
23 code which needs to know/query/use the structure of the running system wrt
33 The topology of a system is described in the units of:
35 - packages
36 - cores
37 - threads
42 controller, shared caches etc.
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| D | sgx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 * Privileged (ring-0) ENCLS functions orchestrate the construction of the
15 * Unprivileged (ring-3) ENCLU functions allow an application to enter and
30 appears to be unsupported on a system which has hardware support, ensure
34 Enclave Page Cache
37 SGX utilizes an *Enclave Page Cache (EPC)* to store pages that are associated
38 with an enclave. It is contained in a BIOS-reserved region of physical memory.
49 ------------------
66 Enclave Page Cache Map
67 ----------------------
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| /Documentation/devicetree/bindings/thermal/ |
| D | thermal-cooling-devices.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-cooling-devices.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Amit Kucheria <amitk@kernel.org>
19 system in devicetree:
20 - thermal-sensor: device that measures temperature, has SoC-specific bindings
21 - cooling-device: device used to dissipate heat either passively or actively
22 - thermal-zones: a container of the following node types used to describe all
28 - Passive cooling: by means of regulating device performance. A typical
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 7 Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
11 - compatible: Compatible property value should be "altr,nios2-1.0".
12 - reg: Contains CPU index.
13 - interrupt-controller: Specifies that the node is an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
17 - dcache-line-size: Contains data cache line size.
18 - icache-line-size: Contains instruction line size.
19 - dcache-size: Contains data cache size.
20 - icache-size: Contains instruction cache size.
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| /Documentation/admin-guide/cgroup-v1/ |
| D | memory.rst | 2 Memory Resource Controller
12 The Memory Resource Controller has generically been referred to as the
13 memory controller in this document. Do not confuse memory controller
14 used here with the memory controller that is used in hardware.
17 When we mention a cgroup (cgroupfs's directory) with memory controller,
18 we call it "memory cgroup". When you see git-log and source code, you'll
22 Benefits and Purpose of the memory controller
25 The memory controller isolates the memory behaviour of a group of tasks
26 from the rest of the system. The article on LWN [12]_ mentions some probable
27 uses of the memory controller. The memory controller can be used to
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| D | memcg_test.rst | 2 Memory Resource Controller(Memcg) Implementation Memo
7 Base Kernel Version: based on 2.6.33-rc7-mm(candidate for 34).
13 (*) Topics on API should be in Documentation/admin-guide/cgroup-v1/memory.rst)
29 occurs. swap_cgroup is used only when a charged page is swapped-out.
41 a page/swp_entry may be uncharged (usage -= PAGE_SIZE) by
50 3. charge-commit-cancel
55 - mem_cgroup_try_charge()
56 - mem_cgroup_commit_charge() or mem_cgroup_cancel_charge()
63 At cancel(), simply usage -= PAGE_SIZE.
71 - page fault into MAP_ANONYMOUS mapping.
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| /Documentation/admin-guide/mm/ |
| D | concepts.rst | 5 The memory management in Linux is a complex system that evolved over the
7 systems from MMU-less microcontrollers to supercomputers. The memory
19 The physical memory in a computer system is a limited resource and
37 writes) from (or to) the system memory, it translates the `virtual`
39 memory controller can understand.
41 The physical system memory is divided into page frames, or pages. The
69 processor cycles on the address translation, CPUs maintain a cache of
80 improves TLB hit-rate and thus improves overall system performance.
87 Documentation/admin-guide/mm/hugetlbpage.rst.
91 requires users and/or system administrators to configure what parts of
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | st,stih407-irq-syscfg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STi System Configuration Controlled IRQs
10 - Patrice Chotard <patrice.chotard@foss.st.com>
14 Management), and PL310 L2 Cache IRQs are controlled using System
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
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| /Documentation/admin-guide/perf/ |
| D | xgene-pmu.rst | 2 APM X-Gene SoC Performance Monitoring Unit (PMU)
5 X-Gene SoC PMU consists of various independent system device PMUs such as
6 L3 cache(s), I/O bridge(s), memory controller bridge(s) and memory
7 controller(s). These PMU devices are loosely architected to follow the
12 -----------------
14 The xgene-pmu driver registers several perf PMU drivers. Each of the perf
21 can be used with perf tool. For example, "l3c0/bank-fifo-full/" is an
25 performance of a specific datapath. For example, agents of a L3 cache can be
32 each PMU, please refer to APM X-Gene User Manual.
39 / # perf list | grep -e l3c -e iob -e mcb -e mc
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| D | thunderx2-pmu.rst | 5 The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
17 The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
28 work. Per-task perf sessions are also not supported.
32 # perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
34 # perf stat -a -e \
40 # perf stat -a -e \
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| /Documentation/arch/arm64/ |
| D | booting.rst | 13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
33 ---------------------------
38 kernel will use for volatile data storage in the system. It performs
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
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| /Documentation/filesystems/ |
| D | affs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 DOS\1 The original Fast File System. Supported read/write.
19 in file names are case-insensitive, as they ought to be.
22 DOS\3 The "international" Fast File System. Supported read/write.
24 DOS\4 The original filesystem with directory cache. The directory
25 cache speeds up directory accesses on floppies considerably,
29 DOS\5 The Fast File System with directory cache. Supported read only.
38 The muFS (multi user File System) equivalents of the above file systems
49 system to uid or the uid of the current user, respectively.
62 The file system will return an error when filename exceeds
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| /Documentation/driver-api/firmware/ |
| D | fallback-mechanisms.rst | 40 * Races upon resume from suspend. This is resolved by the firmware cache, but
41 the firmware cache is only supported if you use uevents, and its not
97 important to re-iterate that no device is created if a direct filesystem lookup
113 -----------------------
114 .. kernel-doc:: drivers/base/firmware_loader/fallback.c
171 in non-traditional paths -- paths outside of the listing documented in the
179 also setup the firmware cache for firmware requests. As documented above,
180 the firmware cache is only set up if uevent is enabled for an API call.
181 Although this can disable the firmware cache for request_firmware_nowait()
183 the cache as that was not the original purpose of the flag. Not setting
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-nfit | 10 (RO) Serial number of the NVDIMM (non-volatile dual in-line
44 (RO) Handle (i.e., instance number) for the SMBIOS (system
54 (RO) The flags in the NFIT memory device sub-structure indicate
74 mapped directly into system physical address space and / or a
80 only expect one code per-dimm as they will ignore
113 http://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf
114 https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/
132 (RO) Sub-system vendor id of the NVDIMM non-volatile memory
133 subsystem controller.
141 (RO) Sub-system revision id of the NVDIMM non-volatile memory subsystem
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
17 system control is required:
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
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