Searched +full:timebase +full:- +full:frequency (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>11 - Srinivas Neeli <srinivas.neeli@amd.com>14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.15 WDT uses a dual-expiration architecture. After one expiration of22 - $ref: watchdog.yaml#27 - xlnx,xps-timebase-wdt-1.01.a[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Palmer Dabbelt <palmer@dabbelt.com>11 - Anup Patel <anup.patel@wdc.com>14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor16 interrupts. It directly connects to the timer and inter-processor interrupt17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local19 The clock frequency of CLINT is specified via "timebase-frequency" DT[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V timer10 - Anup Patel <anup@brainfault.org>13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode14 based on the time CSR defined by the RISC-V privileged specification. The15 timer interrupts of this device are configured using the RISC-V SBI Time16 extension or the RISC-V Sstc extension.18 The clock frequency of RISC-V timer device is specified via the[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V CPUs10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>15 This document uses some terminology common to the RISC-V community19 mandated by the RISC-V ISA: a PC and some registers. This27 - $ref: /schemas/cpu.yaml#[all …]
24 IRIG adjustments from external IRIG-B signal42 IRIG signal is sent to the IRIG-B module44 FREQ1 signal is sent to frequency counter 145 FREQ2 signal is sent to frequency counter 246 FREQ3 signal is sent to frequency counter 347 FREQ4 signal is sent to frequency counter 462 IRIG output is from the PHC, in IRIG-B format64 GEN1 output is from frequency generator 165 GEN2 output is from frequency generator 266 GEN3 output is from frequency generator 3[all …]