Searched +full:valid +full:- +full:mask (Results 1 – 25 of 123) sorted by relevance
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,vic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
15 be nested or have the outputs wire-OR'd together.
18 - $ref: /schemas/interrupt-controller.yaml#
23 - arm,pl190-vic
24 - arm,pl192-vic
25 - arm,versatile-vic
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| D | arm,versatile-fpga-irq.txt | 9 - compatible: "arm,versatile-fpga-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
14 - reg: The register bank for the FPGA interrupt controller.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
17 - valid-mask: a u32 number representing a bit mask determining which of
18 the interrupts are valid. Unconnected/unused lines are set to 0, and
22 The "oxsemi,ox810se-rps-irq" compatible is deprecated.
27 compatible = "arm,versatile-fpga-irq";
28 #interrupt-cells = <1>;
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| D | brcm,bcm7038-l1-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
23 - Atomic mask/unmask operations
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| /Documentation/devicetree/bindings/hwmon/ |
| D | max6697.txt | 4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
23 - extended-range-enable
24 Only valid for MAX6581. Set to enable extended temperature range.
26 - beta-compensation-enable
27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on
30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
34 - over-temperature-mask
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| /Documentation/devicetree/bindings/mtd/ |
| D | davinci-nand.txt | 7 Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
8 Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
15 - reg: Contains 2 offset/length values:
16 - offset and length for the access window.
17 - offset and length for accessing the AEMIF
20 - ti,davinci-chipselect: number of chipselect. Indicates on the
23 Can be in the range [0-3].
27 - ti,davinci-mask-ale: mask for ALE. Needed for executing address
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| /Documentation/ABI/testing/ |
| D | ima_policy | 8 loaded into the run-time of this system. At runtime,
25 base: [[func=] [mask=] [fsmagic=] [fsuuid=] [fsname=]
39 mask:= [[^]MAY_READ] [[^]MAY_WRITE] [[^]MAY_APPEND]
42 fsuuid:= file system UUID (e.g 8bcbe394-4f13-4144-be8e-5aa9ea2ce2f6)
64 Require fs-verity's file digest instead of the
67 (eg, .builtin_trusted_keys|.ima). Only valid
70 (eg, ima-ng). Only valid when action is "measure".
75 appraise_algos:= comma-separated list of hash algorithms
115 measure func=FILE_MMAP mask=MAY_EXEC
116 measure func=FILE_CHECK mask=MAY_READ uid=0
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| D | sysfs-class-rc | 6 The rc/ class sub-directory belongs to the Remote Controller
33 Writing "-proto" will remove a protocol from the list of enabled
51 expected value of the bits set in the filter mask.
63 Sets the scancode filter mask of bits to compare.
66 value. A value of 0 disables the filter to allow all valid
83 "rc-5 nec nec-x rc-6-0 rc-6-6a-24 [rc-6-6a-32] rc-6-mce"
86 "rc-5", "rc-6" have their different bit length encodings
109 set the expected value of the bits set in the wakeup filter mask
125 Sets the scancode wakeup filter mask of bits to compare.
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| /Documentation/arch/arm/ |
| D | interrupts.rst | 5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
36 IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and
37 SMC9196 interrupts until it has finished transferring its multi-sector
51 GPIO0-10, and another for all the rest. It is just a container for
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| /Documentation/devicetree/bindings/thermal/ |
| D | brcm,sr-thermal.txt | 6 - compatible : Must be "brcm,sr-thermal"
7 - reg : Memory where tmon data will be available.
8 - brcm,tmon-mask: A one cell bit mask of valid TMON sources.
10 - #thermal-sensor-cells : Thermal sensor phandler
11 - polling-delay: Max number of milliseconds to wait between polls.
12 - thermal-sensors: A list of thermal sensor phandles and specifier.
14 in correspond with brcm,tmon-mask.
15 - temperature: trip temperature threshold in millicelsius.
19 compatible = "simple-bus";
20 #address-cells = <1>;
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| /Documentation/devicetree/bindings/bus/ |
| D | brcm,gisb-arb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
15 - items:
16 - enum:
17 - brcm,bcm7445-gisb-arb # for other 28nm chips
18 - const: brcm,gisb-arb
19 - items:
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| /Documentation/devicetree/bindings/regulator/ |
| D | ti-abb-regulator.txt | 4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
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| /Documentation/firmware-guide/acpi/apei/ |
| D | einj.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 which shows that the BIOS is exposing an EINJ table - it is the
43 - available_error_type
51 0x00000002 Processor Uncorrectable non-fatal
54 0x00000010 Memory Uncorrectable non-fatal
57 0x00000080 PCI Express Uncorrectable non-fatal
60 0x00000400 Platform Uncorrectable non-fatal
67 - error_type
72 - error_inject
78 - flags
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| /Documentation/firmware-guide/acpi/ |
| D | debug.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 Compile-time configuration
16 Boot- and run-time configuration
20 you're interested in. At boot-time, use the acpi.debug_layer and
28 The "debug_layer" is a mask that selects components of interest, e.g., a
32 You can set the debug_layer mask at boot-time using the acpi.debug_layer
38 Reading /sys/module/acpi/parameters/debug_layer shows the supported mask values::
58 The "debug_level" is a mask that selects different types of messages, e.g.,
66 You can set the debug_level mask at boot-time using the acpi.debug_level
71 /sys/module/acpi/parameters/debug_level shows the supported mask values,
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| /Documentation/devicetree/bindings/sound/ |
| D | amlogic,axg-sound-card.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/amlogic,axg-sound-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jerome Brunet <jbrunet@baylibre.com>
13 - $ref: sound-card-common.yaml#
17 const: amlogic,axg-sound-card
19 audio-aux-devs:
20 $ref: /schemas/types.yaml#/definitions/phandle-array
23 audio-widgets:
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| /Documentation/arch/arm64/ |
| D | asymmetric-32bit.rst | 2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
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| D | tagged-address-abi.rst | 14 ---------------
17 userspace (EL0) to perform memory accesses through 64-bit pointers with
18 a non-zero top byte. This document describes the relaxation of the
23 -----------------------------
26 this document, a "valid tagged pointer" is a pointer with a potentially
27 non-zero top-byte that references an address in the user process address
30 - ``mmap()`` syscall where either:
32 - flags have the ``MAP_ANONYMOUS`` bit set or
33 - the file descriptor refers to a regular file (including those
36 - ``brk()`` syscall (i.e. the heap area between the initial location of
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| /Documentation/arch/riscv/ |
| D | vector.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
11 ---------------------
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
33 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
34 enablement status on execve(). The system-wide default setting can be
43 arg: The control argument is a 5-bit value consisting of 3 parts, and
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | divider.txt | 4 register-mapped adjustable clock rate divider that does not gate and has
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
28 Additionally an array of valid dividers may be supplied like so:
39 Any zero value in this array means the corresponding bit-value is invalid
44 the number of bits to shift that mask, if necessary. If the shift value
50 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
54 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
55 - #clock-cells : from common clock binding; shall be set to 0.
56 - clocks : link to phandle of parent clock
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| /Documentation/devicetree/bindings/dma/ |
| D | intel,ldma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
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| /Documentation/userspace-api/media/rc/ |
| D | rc-sysfs-nodes.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
9 As defined at ``Documentation/ABI/testing/sysfs-class-rc``, those are
18 The ``/sys/class/rc/`` class sub-directory belongs to the Remote
45 Writing "-proto" will remove a protocol from the list of enabled
64 expected value of the bits set in the filter mask. If the hardware
76 Sets the scancode filter mask of bits to compare. Use in combination
79 filter to allow all valid scancodes to be processed.
95 rc-5 nec nec-x rc-6-0 rc-6-6a-24 [rc-6-6a-32] rc-6-mce
97 Note that protocol variants are listed, so ``nec``, ``sony``, ``rc-5``, ``rc-6``
121 the bits set in the wakeup filter mask to trigger a system wake event.
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| /Documentation/arch/s390/ |
| D | vfio-ap.rst | 13 The AP adapter cards are exposed via the AP bus. The motivation for vfio-ap
45 sub-directory::
75 /sys/bus/ap/ap_control_domain_mask. The bits in the mask, from most to least
76 significant bit, correspond to domains 0-255.
111 * NQAP: to enqueue an AP command-request message to a queue
112 * DQAP: to dequeue an AP command-reply message from a queue
130 * The AP Mask (APM) field is a bit mask that identifies the AP adapters assigned
131 to the KVM guest. Each bit in the mask, from left to right, corresponds to
132 an APID from 0-255. If a bit is set, the corresponding adapter is valid for
135 * The AP Queue Mask (AQM) field is a bit mask identifying the AP usage domains
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| /Documentation/PCI/ |
| D | boot-interrupts.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 :Author: - Sean V Kelley <sean.v.kelley@linux.intel.com>
13 interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a
15 MSI interrupts. If the IO-APIC is disabled (via the mask bits in the
16 IO-APIC table entries), the messages are routed to the legacy PCH. This
17 in-band interrupt mechanism was traditionally necessary for systems that
18 did not support the IO-APIC and for boot. Intel in the past has used the
20 protocol describes this in-band legacy wire-interrupt INTx mechanism for
21 I/O devices to signal PCI-style level interrupts. The subsequent paragraphs
29 When in-band legacy INTx messages are forwarded to the PCH, they in turn
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-mcp23s08.txt | 2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
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| /Documentation/filesystems/spufs/ |
| D | spu_run.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 spu_run - execute an spu context
25 Cell Broadband Engine Architecture in order to access Synergistic Pro-
26 cessor Units (SPUs). It uses the fd that was returned from spu_cre-
27 ate(2) to address a specific SPU context. When the context gets sched-
32 not return while the SPU is still running. If there is a need to exe-
42 gets filled when spu_run returns. It can be one of the following con-
59 spu_run returns the value of the spu_status register or -1 to indicate
61 spu_status register value contains a bit mask of status codes and
62 optionally a 14 bit code returned from the stop-and-signal instruction
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| /Documentation/devicetree/bindings/mailbox/ |
| D | nvidia,tegra186-hsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
30 - bits 15..8:
31 A bit mask of flags that further specifies the type of shared
33 specified then, 32-bit shared mailbox is used.
34 - bits 7..0:
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