| /drivers/net/wireless/zydas/zd1211rw/ |
| D | zd_rf_rf2959.c | 32 static int bits(u32 rw, int from, int to)
41 return bits(rw, bit, bit);
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
54 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
63 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
67 bits(rw, 6, 17), bits(rw, 0, 5));
70 PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
74 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
82 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
[all …]
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| /drivers/video/fbdev/core/ |
| D | syscopyarea.c | 29 const unsigned long *src, unsigned src_idx, int bits, unsigned n) in bitcpy() argument
36 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitcpy()
40 if (dst_idx+n <= bits) { in bitcpy()
52 n -= bits - dst_idx; in bitcpy()
56 n /= bits; in bitcpy()
80 right = shift & (bits - 1); in bitcpy()
81 left = -shift & (bits - 1); in bitcpy()
83 if (dst_idx+n <= bits) { in bitcpy()
90 } else if (src_idx+n <= bits) { in bitcpy()
114 n -= bits - dst_idx; in bitcpy()
[all …]
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| D | cfbcopyarea.c | 47 const unsigned long __iomem *src, unsigned src_idx, int bits, in bitcpy() argument
58 memmove((char *)dst + ((dst_idx & (bits - 1))) / 8, in bitcpy()
59 (char *)src + ((src_idx & (bits - 1))) / 8, n / 8); in bitcpy()
64 last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask); in bitcpy()
69 if (dst_idx+n <= bits) { in bitcpy()
82 n -= bits - dst_idx; in bitcpy()
86 n /= bits; in bitcpy()
110 int const left = shift & (bits - 1); in bitcpy()
111 int const right = -shift & (bits - 1); in bitcpy()
113 if (dst_idx+n <= bits) { in bitcpy()
[all …]
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| D | sysfillrect.c | 26 unsigned long pat, unsigned n, int bits) in bitfill_aligned() argument
34 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_aligned()
36 if (dst_idx+n <= bits) { in bitfill_aligned()
48 n -= bits - dst_idx; in bitfill_aligned()
52 n /= bits; in bitfill_aligned()
72 unsigned long pat, int left, int right, unsigned n, int bits) in bitfill_unaligned() argument
80 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_unaligned()
82 if (dst_idx+n <= bits) { in bitfill_unaligned()
94 n -= bits - dst_idx; in bitfill_unaligned()
98 n /= bits; in bitfill_unaligned()
[all …]
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| D | cfbfillrect.c | 36 unsigned long pat, unsigned n, int bits, u32 bswapmask) in bitfill_aligned() argument
44 last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask); in bitfill_aligned()
46 if (dst_idx+n <= bits) { in bitfill_aligned()
58 n -= bits - dst_idx; in bitfill_aligned()
62 n /= bits; in bitfill_aligned()
93 unsigned long pat, int left, int right, unsigned n, int bits) in bitfill_unaligned() argument
101 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); in bitfill_unaligned()
103 if (dst_idx+n <= bits) { in bitfill_unaligned()
115 n -= bits - dst_idx; in bitfill_unaligned()
119 n /= bits; in bitfill_unaligned()
[all …]
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| /drivers/comedi/drivers/ |
| D | c6xdigio.c | 70 unsigned int *bits, in c6xdigio_get_encoder_bits() argument
80 *bits = val; in c6xdigio_get_encoder_bits()
89 unsigned int bits; in c6xdigio_pwm_write() local
96 bits = (val >> 0) & 0x03; in c6xdigio_pwm_write()
97 c6xdigio_write_data(dev, cmd | bits | (0 << 2), 0x00); in c6xdigio_pwm_write()
98 bits = (val >> 2) & 0x03; in c6xdigio_pwm_write()
99 c6xdigio_write_data(dev, cmd | bits | (1 << 2), 0x80); in c6xdigio_pwm_write()
100 bits = (val >> 4) & 0x03; in c6xdigio_pwm_write()
101 c6xdigio_write_data(dev, cmd | bits | (0 << 2), 0x00); in c6xdigio_pwm_write()
102 bits = (val >> 6) & 0x03; in c6xdigio_pwm_write()
[all …]
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| /drivers/block/drbd/ |
| D | drbd_vli.h | 207 static inline void bitstream_cursor_advance(struct bitstream_cursor *cur, unsigned int bits) in bitstream_cursor_advance() argument
209 bits += cur->bit; in bitstream_cursor_advance()
210 cur->b = cur->b + (bits >> 3); in bitstream_cursor_advance()
211 cur->bit = bits & 7; in bitstream_cursor_advance()
248 static inline int bitstream_put_bits(struct bitstream *bs, u64 val, const unsigned int bits) in bitstream_put_bits() argument
253 if (bits == 0) in bitstream_put_bits()
256 if ((bs->cur.b + ((bs->cur.bit + bits -1) >> 3)) - bs->buf >= bs->buf_len) in bitstream_put_bits()
260 if (bits < 64) in bitstream_put_bits()
261 val &= ~0ULL >> (64 - bits); in bitstream_put_bits()
265 for (tmp = 8 - bs->cur.bit; tmp < bits; tmp += 8) in bitstream_put_bits()
[all …]
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| /drivers/staging/media/atomisp/pci/runtime/isys/src/ |
| D | rx.c | 25 hrt_data bits = receiver_port_reg_load(RX0_ID, in ia_css_isys_rx_enable_all_interrupts() local
29 bits |= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT) | in ia_css_isys_rx_enable_all_interrupts()
49 _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits); in ia_css_isys_rx_enable_all_interrupts()
103 unsigned int bits; in ia_css_isys_rx_get_irq_info() local
106 bits = ia_css_isys_rx_get_interrupt_reg(port); in ia_css_isys_rx_get_irq_info()
107 *irq_infos = ia_css_isys_rx_translate_irq_infos(bits); in ia_css_isys_rx_get_irq_info()
111 unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits) in ia_css_isys_rx_translate_irq_infos() argument
115 if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT)) in ia_css_isys_rx_translate_irq_infos()
117 if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT)) in ia_css_isys_rx_translate_irq_infos()
119 if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT)) in ia_css_isys_rx_translate_irq_infos()
[all …]
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| /drivers/iio/adc/ |
| D | max1363.c | 141 u8 bits; member
389 if (st->chip_info->bits != 8) { in max1363_read_single_chan()
396 ((1 << st->chip_info->bits) - 1); in max1363_read_single_chan()
429 *val2 = st->chip_info->bits; in max1363_read_raw()
459 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \ argument
470 .realbits = bits, \
471 .storagebits = (bits > 8) ? 16 : 8, \
480 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \ argument
493 .realbits = bits, \
494 .storagebits = (bits > 8) ? 16 : 8, \
[all …]
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| D | ti-ads7950.c | 53 #define TI_ADS7950_EXTRACT(val, dec, bits) \ argument
54 (((val) >> (dec)) & ((1 << (bits)) - 1))
136 #define TI_ADS7950_V_CHAN(index, bits) \ argument
148 .realbits = bits, \
150 .shift = 12 - (bits), \
155 #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \ argument
157 TI_ADS7950_V_CHAN(0, bits), \
158 TI_ADS7950_V_CHAN(1, bits), \
159 TI_ADS7950_V_CHAN(2, bits), \
160 TI_ADS7950_V_CHAN(3, bits), \
[all …]
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| D | ad7923.c | 47 #define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1)) argument
84 #define AD7923_V_CHAN(index, bits) \ argument
95 .realbits = (bits), \
97 .shift = 12 - (bits), \
102 #define DECLARE_AD7923_CHANNELS(name, bits) \ argument
104 AD7923_V_CHAN(0, bits), \
105 AD7923_V_CHAN(1, bits), \
106 AD7923_V_CHAN(2, bits), \
107 AD7923_V_CHAN(3, bits), \
111 #define DECLARE_AD7908_CHANNELS(name, bits) \ argument
[all …]
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| /drivers/spi/ |
| D | spi-bitbang-txrx.h | 51 u32 word, u8 bits) in bitbang_txrx_be_cpha0() argument
55 u32 oldbit = (!(word & (1<<(bits-1)))) << 31; in bitbang_txrx_be_cpha0()
57 for (word <<= (32 - bits); likely(bits); bits--) { in bitbang_txrx_be_cpha0()
83 u32 word, u8 bits) in bitbang_txrx_be_cpha1() argument
87 u32 oldbit = (!(word & (1<<(bits-1)))) << 31; in bitbang_txrx_be_cpha1()
89 for (word <<= (32 - bits); likely(bits); bits--) { in bitbang_txrx_be_cpha1()
115 u32 word, u8 bits) in bitbang_txrx_le_cpha0() argument
119 u8 rxbit = bits - 1; in bitbang_txrx_le_cpha0()
122 for (; likely(bits); bits--) { in bitbang_txrx_le_cpha0()
148 u32 word, u8 bits) in bitbang_txrx_le_cpha1() argument
[all …]
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| D | spi-gpio.c | 135 unsigned nsecs, u32 word, u8 bits, unsigned flags) in spi_gpio_txrx_word_mode0() argument
138 return bitbang_txrx_le_cpha0(spi, nsecs, 0, flags, word, bits); in spi_gpio_txrx_word_mode0()
140 return bitbang_txrx_be_cpha0(spi, nsecs, 0, flags, word, bits); in spi_gpio_txrx_word_mode0()
144 unsigned nsecs, u32 word, u8 bits, unsigned flags) in spi_gpio_txrx_word_mode1() argument
147 return bitbang_txrx_le_cpha1(spi, nsecs, 0, flags, word, bits); in spi_gpio_txrx_word_mode1()
149 return bitbang_txrx_be_cpha1(spi, nsecs, 0, flags, word, bits); in spi_gpio_txrx_word_mode1()
153 unsigned nsecs, u32 word, u8 bits, unsigned flags) in spi_gpio_txrx_word_mode2() argument
156 return bitbang_txrx_le_cpha0(spi, nsecs, 1, flags, word, bits); in spi_gpio_txrx_word_mode2()
158 return bitbang_txrx_be_cpha0(spi, nsecs, 1, flags, word, bits); in spi_gpio_txrx_word_mode2()
162 unsigned nsecs, u32 word, u8 bits, unsigned flags) in spi_gpio_txrx_word_mode3() argument
[all …]
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| /drivers/iio/dac/ |
| D | ad5686.c | 191 #define AD5868_CHANNEL(chan, addr, bits, _shift) { \ argument
201 .realbits = (bits), \
208 #define DECLARE_AD5693_CHANNELS(name, bits, _shift) \ argument
210 AD5868_CHANNEL(0, 0, bits, _shift), \
213 #define DECLARE_AD5338_CHANNELS(name, bits, _shift) \ argument
215 AD5868_CHANNEL(0, 1, bits, _shift), \
216 AD5868_CHANNEL(1, 8, bits, _shift), \
219 #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \ argument
221 AD5868_CHANNEL(0, 1, bits, _shift), \
222 AD5868_CHANNEL(1, 2, bits, _shift), \
[all …]
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_dp_types.h | 202 } bits; member
210 } bits; member
220 } bits; member
230 } bits; member
238 } bits; member
248 } bits; member
262 } bits; member
276 } bits; member
285 } bits; member
299 } bits; member
[all …]
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| /drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_dp_irq_handler.c | 73 if (!lane_status.bits.CHANNEL_EQ_DONE_0 || in dp_parse_link_loss_status()
74 !lane_status.bits.CR_DONE_0 || in dp_parse_link_loss_status()
75 !lane_status.bits.SYMBOL_LOCKED_0) { in dp_parse_link_loss_status()
88 (!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b || in dp_parse_link_loss_status()
89 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b)) { in dp_parse_link_loss_status()
91 } else if (!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) { in dp_parse_link_loss_status()
135 if (psr_configuration.bits.ENABLE) { in handle_hpd_irq_psr_sink()
152 if (psr_error_status.bits.LINK_CRC_ERROR || in handle_hpd_irq_psr_sink()
153 psr_error_status.bits.RFB_STORAGE_ERROR || in handle_hpd_irq_psr_sink()
154 psr_error_status.bits.VSC_SDP_ERROR) { in handle_hpd_irq_psr_sink()
[all …]
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| /drivers/net/wireguard/ |
| D | allowedips.c | 13 static void swap_endian(u8 *dst, const u8 *src, u8 bits) in swap_endian() argument
15 if (bits == 32) { in swap_endian()
17 } else if (bits == 128) { in swap_endian()
24 u8 cidr, u8 bits) in copy_and_assign_cidr() argument
29 node->bit_at_a ^= (bits / 8U - 1U) % 8U; in copy_and_assign_cidr()
32 node->bitlen = bits; in copy_and_assign_cidr()
33 memcpy(node->bits, src, bits / 8U); in copy_and_assign_cidr()
88 u8 bits) in common_bits() argument
90 if (bits == 32) in common_bits()
91 return 32U - fls(*(const u32 *)node->bits ^ *(const u32 *)key); in common_bits()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | uconn.c | 34 nvkm_uconn_uevent_gsp(struct nvkm_object *object, u64 token, u32 bits) in nvkm_uconn_uevent_gsp() argument
40 if (bits & NVKM_DPYID_PLUG) in nvkm_uconn_uevent_gsp()
42 if (bits & NVKM_DPYID_UNPLUG) in nvkm_uconn_uevent_gsp()
44 if (bits & NVKM_DPYID_IRQ) in nvkm_uconn_uevent_gsp()
51 nvkm_uconn_uevent_aux(struct nvkm_object *object, u64 token, u32 bits) in nvkm_uconn_uevent_aux() argument
57 if (bits & NVKM_I2C_PLUG) in nvkm_uconn_uevent_aux()
59 if (bits & NVKM_I2C_UNPLUG) in nvkm_uconn_uevent_aux()
61 if (bits & NVKM_I2C_IRQ) in nvkm_uconn_uevent_aux()
68 nvkm_uconn_uevent_gpio(struct nvkm_object *object, u64 token, u32 bits) in nvkm_uconn_uevent_gpio() argument
74 if (bits & NVKM_GPIO_HI) in nvkm_uconn_uevent_gpio()
[all …]
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| /drivers/pmdomain/imx/ |
| D | gpcv2.c | 293 } bits; member
350 if (domain->bits.pxx) { in imx_pgc_power_up()
353 domain->bits.pxx, domain->bits.pxx); in imx_pgc_power_up()
360 !(reg_val & domain->bits.pxx), in imx_pgc_power_up()
380 if (domain->bits.hskreq) { in imx_pgc_power_up()
382 domain->bits.hskreq, domain->bits.hskreq); in imx_pgc_power_up()
442 if (domain->bits.hskreq) { in imx_pgc_power_down()
444 domain->bits.hskreq); in imx_pgc_power_down()
448 !(reg_val & domain->bits.hskack), in imx_pgc_power_down()
456 if (domain->bits.pxx) { in imx_pgc_power_down()
[all …]
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| /drivers/clk/at91/ |
| D | sckc.c | 32 const struct clk_slow_bits *bits; member
41 const struct clk_slow_bits *bits; member
51 const struct clk_slow_bits *bits; member
62 const struct clk_slow_bits *bits; member
74 if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) in clk_slow_osc_prepare()
77 writel(tmp | osc->bits->cr_osc32en, sckcr); in clk_slow_osc_prepare()
93 if (tmp & osc->bits->cr_osc32byp) in clk_slow_osc_unprepare()
96 writel(tmp & ~osc->bits->cr_osc32en, sckcr); in clk_slow_osc_unprepare()
105 if (tmp & osc->bits->cr_osc32byp) in clk_slow_osc_is_prepared()
108 return !!(tmp & osc->bits->cr_osc32en); in clk_slow_osc_is_prepared()
[all …]
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| /drivers/gpu/drm/tegra/ |
| D | hda.c | 14 unsigned int mul, div, bits, channels; in tegra_hda_parse_format() local
33 fmt->bits = 8; in tegra_hda_parse_format()
37 fmt->bits = 16; in tegra_hda_parse_format()
41 fmt->bits = 20; in tegra_hda_parse_format()
45 fmt->bits = 24; in tegra_hda_parse_format()
49 fmt->bits = 32; in tegra_hda_parse_format()
53 bits = (format & AC_FMT_BITS_MASK) >> AC_FMT_BITS_SHIFT; in tegra_hda_parse_format()
54 WARN(1, "invalid number of bits: %#x\n", bits); in tegra_hda_parse_format()
55 fmt->bits = 8; in tegra_hda_parse_format()
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| /drivers/net/ethernet/brocade/bna/ |
| D | bna_hw_defs.h | 88 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 | \
90 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 | \
92 (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK); \
93 (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK); \
94 (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT; \
95 (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT; \
108 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
110 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
112 (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2); \
113 (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2); \
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/core/ |
| D | event.c | 70 nvkm_event_put(ntfy->event, ntfy->bits, ntfy->id); in nvkm_event_ntfy_state()
73 nvkm_event_get(ntfy->event, ntfy->bits, ntfy->id); in nvkm_event_ntfy_state()
102 nvkm_trace(subdev, "event: ntfy block %08x on %d wait:%d\n", ntfy->bits, ntfy->id, wait); in nvkm_event_ntfy_block_()
121 nvkm_trace(ntfy->event->subdev, "event: ntfy allow %08x on %d\n", ntfy->bits, ntfy->id); in nvkm_event_ntfy_allow()
138 nvkm_trace(event->subdev, "event: ntfy del %08x on %d\n", ntfy->bits, ntfy->id); in nvkm_event_ntfy_del()
146 nvkm_event_ntfy_add(struct nvkm_event *event, int id, u32 bits, bool wait, nvkm_event_func func, in nvkm_event_ntfy_add() argument
149 nvkm_trace(event->subdev, "event: ntfy add %08x on %d wait:%d\n", id, bits, wait); in nvkm_event_ntfy_add()
153 ntfy->bits = bits; in nvkm_event_ntfy_add()
164 nvkm_event_ntfy_valid(struct nvkm_event *event, int id, u32 bits) in nvkm_event_ntfy_valid() argument
170 nvkm_event_ntfy(struct nvkm_event *event, int id, u32 bits) in nvkm_event_ntfy() argument
[all …]
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| /drivers/media/rc/ |
| D | ir-imon-decoder.c | 43 if (imon->bits == 0x299115b7) in ir_imon_decode_scancode()
46 if ((imon->bits & 0xfc0000ff) == 0x680000b7) { in ir_imon_decode_scancode()
50 buf = imon->bits >> 16; in ir_imon_decode_scancode()
53 if (imon->bits & 0x02000000) in ir_imon_decode_scancode()
55 buf = imon->bits >> 8; in ir_imon_decode_scancode()
58 if (imon->bits & 0x01000000) in ir_imon_decode_scancode()
63 imon->bits = rel_y > 0 ? in ir_imon_decode_scancode()
67 imon->bits = rel_x > 0 ? in ir_imon_decode_scancode()
77 (imon->bits & 0x00010000) != 0); in ir_imon_decode_scancode()
79 (imon->bits & 0x00040000) != 0); in ir_imon_decode_scancode()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| D | dcn401_dccg.c | 282 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()
289 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()
299 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()
306 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()
316 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()
323 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()
333 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()
340 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()
391 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) in dccg401_enable_symclk32_le()
400 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) in dccg401_enable_symclk32_le()
[all …]
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