1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * iio/adc/max1363.c
4 * Copyright (C) 2008-2010 Jonathan Cameron
5 *
6 * based on linux/drivers/i2c/chips/max123x
7 * Copyright (C) 2002-2004 Stefan Eletzhofer
8 *
9 * based on linux/drivers/acron/char/pcf8583.c
10 * Copyright (C) 2000 Russell King
11 *
12 * Driver for max1363 and similar chips.
13 */
14
15 #include <linux/interrupt.h>
16 #include <linux/cleanup.h>
17 #include <linux/device.h>
18 #include <linux/kernel.h>
19 #include <linux/sysfs.h>
20 #include <linux/list.h>
21 #include <linux/i2c.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/property.h>
28
29 #include <linux/iio/iio.h>
30 #include <linux/iio/sysfs.h>
31 #include <linux/iio/events.h>
32 #include <linux/iio/buffer.h>
33 #include <linux/iio/kfifo_buf.h>
34 #include <linux/iio/trigger_consumer.h>
35 #include <linux/iio/triggered_buffer.h>
36
37 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
38
39 /* There is a fair bit more defined here than currently
40 * used, but the intention is to support everything these
41 * chips do in the long run */
42
43 /* see data sheets */
44 /* max1363 and max1236, max1237, max1238, max1239 */
45 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
46 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
47 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
48 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
49 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10
50 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
51
52 /* think about including max11600 etc - more settings */
53 #define MAX1363_SETUP_EXT_CLOCK 0x08
54 #define MAX1363_SETUP_INT_CLOCK 0x00
55 #define MAX1363_SETUP_UNIPOLAR 0x00
56 #define MAX1363_SETUP_BIPOLAR 0x04
57 #define MAX1363_SETUP_RESET 0x00
58 #define MAX1363_SETUP_NORESET 0x02
59 /* max1363 only - though don't care on others.
60 * For now monitor modes are not implemented as the relevant
61 * line is not connected on my test board.
62 * The definitions are here as I intend to add this soon.
63 */
64 #define MAX1363_SETUP_MONITOR_SETUP 0x01
65
66 /* Specific to the max1363 */
67 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
68 #define MAX1363_MON_INT_ENABLE 0x01
69
70 /* defined for readability reasons */
71 /* All chips */
72 #define MAX1363_CONFIG_BYTE(a) ((a))
73
74 #define MAX1363_CONFIG_SE 0x01
75 #define MAX1363_CONFIG_DE 0x00
76 #define MAX1363_CONFIG_SCAN_TO_CS 0x00
77 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
78 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
79 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
80 /* max123{6-9} only */
81 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40
82
83 /* max1363 only - merely part of channel selects or don't care for others */
84 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
85
86 #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
87
88 /* max1363 strictly 0x06 - but doesn't matter */
89 #define MAX1363_CHANNEL_SEL_MASK 0x1E
90 #define MAX1363_SCAN_MASK 0x60
91 #define MAX1363_SE_DE_MASK 0x01
92
93 #define MAX1363_MAX_CHANNELS 25
94 /**
95 * struct max1363_mode - scan mode information
96 * @conf: The corresponding value of the configuration register
97 * @modemask: Bit mask corresponding to channels enabled in this mode
98 */
99 struct max1363_mode {
100 int8_t conf;
101 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
102 };
103
104 /* This must be maintained along side the max1363_mode_table in max1363_core */
105 enum max1363_modes {
106 /* Single read of a single channel */
107 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
108 /* Differential single read */
109 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
110 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
111 /* Scan to channel and mid to channel where overlapping */
112 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
113 s6to7, s0to7, s6to8, s0to8, s6to9,
114 s0to9, s6to10, s0to10, s6to11, s0to11,
115 /* Differential scan to channel and mid to channel where overlapping */
116 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
117 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
118 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
119 d7m6to11m10, d1m0to11m10,
120 };
121
122 /**
123 * struct max1363_chip_info - chip specifc information
124 * @info: iio core function callbacks structure
125 * @channels: channel specification
126 * @num_channels: number of channels
127 * @mode_list: array of available scan modes
128 * @default_mode: the scan mode in which the chip starts up
129 * @int_vref_mv: the internal reference voltage
130 * @num_modes: number of modes
131 * @bits: accuracy of the adc in bits
132 */
133 struct max1363_chip_info {
134 const struct iio_info *info;
135 const struct iio_chan_spec *channels;
136 int num_channels;
137 const enum max1363_modes *mode_list;
138 enum max1363_modes default_mode;
139 u16 int_vref_mv;
140 u8 num_modes;
141 u8 bits;
142 };
143
144 /**
145 * struct max1363_state - driver instance specific data
146 * @client: i2c_client
147 * @setupbyte: cache of current device setup byte
148 * @configbyte: cache of current device config byte
149 * @chip_info: chip model specific constants, available modes, etc.
150 * @current_mode: the scan mode of this chip
151 * @requestedmask: a valid requested set of channels
152 * @lock: lock to ensure state is consistent
153 * @monitor_on: whether monitor mode is enabled
154 * @monitor_speed: parameter corresponding to device monitor speed setting
155 * @mask_high: bitmask for enabled high thresholds
156 * @mask_low: bitmask for enabled low thresholds
157 * @thresh_high: high threshold values
158 * @thresh_low: low threshold values
159 * @vref: Reference voltage regulator
160 * @vref_uv: Actual (external or internal) reference voltage
161 * @send: function used to send data to the chip
162 * @recv: function used to receive data from the chip
163 */
164 struct max1363_state {
165 struct i2c_client *client;
166 u8 setupbyte;
167 u8 configbyte;
168 const struct max1363_chip_info *chip_info;
169 const struct max1363_mode *current_mode;
170 u32 requestedmask;
171 struct mutex lock;
172
173 /* Using monitor modes and buffer at the same time is
174 currently not supported */
175 bool monitor_on;
176 unsigned int monitor_speed:3;
177 u8 mask_high;
178 u8 mask_low;
179 /* 4x unipolar first then the fours bipolar ones */
180 s16 thresh_high[8];
181 s16 thresh_low[8];
182 struct regulator *vref;
183 u32 vref_uv;
184 int (*send)(const struct i2c_client *client,
185 const char *buf, int count);
186 int (*recv)(const struct i2c_client *client,
187 char *buf, int count);
188 };
189
190 #define MAX1363_MODE_SINGLE(_num, _mask) { \
191 .conf = MAX1363_CHANNEL_SEL(_num) \
192 | MAX1363_CONFIG_SCAN_SINGLE_1 \
193 | MAX1363_CONFIG_SE, \
194 .modemask[0] = _mask, \
195 }
196
197 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
198 .conf = MAX1363_CHANNEL_SEL(_num) \
199 | MAX1363_CONFIG_SCAN_TO_CS \
200 | MAX1363_CONFIG_SE, \
201 .modemask[0] = _mask, \
202 }
203
204 /* note not available for max1363 hence naming */
205 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
206 .conf = MAX1363_CHANNEL_SEL(_num) \
207 | MAX1236_SCAN_MID_TO_CHANNEL \
208 | MAX1363_CONFIG_SE, \
209 .modemask[0] = _mask \
210 }
211
212 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
213 .conf = MAX1363_CHANNEL_SEL(_nump) \
214 | MAX1363_CONFIG_SCAN_SINGLE_1 \
215 | MAX1363_CONFIG_DE, \
216 .modemask[0] = _mask \
217 }
218
219 /* Can't think how to automate naming so specify for now */
220 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
221 .conf = MAX1363_CHANNEL_SEL(_num) \
222 | MAX1363_CONFIG_SCAN_TO_CS \
223 | MAX1363_CONFIG_DE, \
224 .modemask[0] = _mask \
225 }
226
227 /* note only available for max1363 hence naming */
228 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
229 .conf = MAX1363_CHANNEL_SEL(_num) \
230 | MAX1236_SCAN_MID_TO_CHANNEL \
231 | MAX1363_CONFIG_SE, \
232 .modemask[0] = _mask \
233 }
234
235 static const struct max1363_mode max1363_mode_table[] = {
236 /* All of the single channel options first */
237 MAX1363_MODE_SINGLE(0, 1 << 0),
238 MAX1363_MODE_SINGLE(1, 1 << 1),
239 MAX1363_MODE_SINGLE(2, 1 << 2),
240 MAX1363_MODE_SINGLE(3, 1 << 3),
241 MAX1363_MODE_SINGLE(4, 1 << 4),
242 MAX1363_MODE_SINGLE(5, 1 << 5),
243 MAX1363_MODE_SINGLE(6, 1 << 6),
244 MAX1363_MODE_SINGLE(7, 1 << 7),
245 MAX1363_MODE_SINGLE(8, 1 << 8),
246 MAX1363_MODE_SINGLE(9, 1 << 9),
247 MAX1363_MODE_SINGLE(10, 1 << 10),
248 MAX1363_MODE_SINGLE(11, 1 << 11),
249
250 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
251 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
252 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
253 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
254 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
255 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
256 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
257 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
258 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
259 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
260 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
261 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
262
263 /* The multichannel scans next */
264 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
265 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
266 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
267 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
268 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
269 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
270 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
271 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
272 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
273 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
274 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
275 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
276 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
277 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
278 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
279 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
280 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
281
282 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
285 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
286 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
287 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
288 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
292 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
293 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
294 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
295 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
296 };
297
298 static const struct max1363_mode
max1363_match_mode(const unsigned long * mask,const struct max1363_chip_info * ci)299 *max1363_match_mode(const unsigned long *mask,
300 const struct max1363_chip_info *ci)
301 {
302 int i;
303 if (mask)
304 for (i = 0; i < ci->num_modes; i++)
305 if (bitmap_subset(mask,
306 max1363_mode_table[ci->mode_list[i]].
307 modemask,
308 MAX1363_MAX_CHANNELS))
309 return &max1363_mode_table[ci->mode_list[i]];
310 return NULL;
311 }
312
max1363_smbus_send(const struct i2c_client * client,const char * buf,int count)313 static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
314 int count)
315 {
316 int i, err;
317
318 for (i = err = 0; err == 0 && i < count; ++i)
319 err = i2c_smbus_write_byte(client, buf[i]);
320
321 return err ? err : count;
322 }
323
max1363_smbus_recv(const struct i2c_client * client,char * buf,int count)324 static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
325 int count)
326 {
327 int i, ret;
328
329 for (i = 0; i < count; ++i) {
330 ret = i2c_smbus_read_byte(client);
331 if (ret < 0)
332 return ret;
333 buf[i] = ret;
334 }
335
336 return count;
337 }
338
max1363_write_basic_config(struct max1363_state * st)339 static int max1363_write_basic_config(struct max1363_state *st)
340 {
341 u8 tx_buf[2] = { st->setupbyte, st->configbyte };
342
343 return st->send(st->client, tx_buf, 2);
344 }
345
max1363_set_scan_mode(struct max1363_state * st)346 static int max1363_set_scan_mode(struct max1363_state *st)
347 {
348 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
349 | MAX1363_SCAN_MASK
350 | MAX1363_SE_DE_MASK);
351 st->configbyte |= st->current_mode->conf;
352
353 return max1363_write_basic_config(st);
354 }
355
max1363_read_single_chan(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,long m)356 static int max1363_read_single_chan(struct iio_dev *indio_dev,
357 struct iio_chan_spec const *chan,
358 int *val,
359 long m)
360 {
361 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
362 s32 data;
363 u8 rxbuf[2];
364 struct max1363_state *st = iio_priv(indio_dev);
365 struct i2c_client *client = st->client;
366
367 guard(mutex)(&st->lock);
368
369 /*
370 * If monitor mode is enabled, the method for reading a single
371 * channel will have to be rather different and has not yet
372 * been implemented.
373 *
374 * Also, cannot read directly if buffered capture enabled.
375 */
376 if (st->monitor_on)
377 return -EBUSY;
378
379 /* Check to see if current scan mode is correct */
380 if (st->current_mode != &max1363_mode_table[chan->address]) {
381 int ret;
382
383 /* Update scan mode if needed */
384 st->current_mode = &max1363_mode_table[chan->address];
385 ret = max1363_set_scan_mode(st);
386 if (ret < 0)
387 return ret;
388 }
389 if (st->chip_info->bits != 8) {
390 /* Get reading */
391 data = st->recv(client, rxbuf, 2);
392 if (data < 0)
393 return data;
394
395 data = (rxbuf[1] | rxbuf[0] << 8) &
396 ((1 << st->chip_info->bits) - 1);
397 } else {
398 /* Get reading */
399 data = st->recv(client, rxbuf, 1);
400 if (data < 0)
401 return data;
402
403 data = rxbuf[0];
404 }
405 *val = data;
406
407 return 0;
408 }
409 unreachable();
410 }
411
max1363_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)412 static int max1363_read_raw(struct iio_dev *indio_dev,
413 struct iio_chan_spec const *chan,
414 int *val,
415 int *val2,
416 long m)
417 {
418 struct max1363_state *st = iio_priv(indio_dev);
419 int ret;
420
421 switch (m) {
422 case IIO_CHAN_INFO_RAW:
423 ret = max1363_read_single_chan(indio_dev, chan, val, m);
424 if (ret < 0)
425 return ret;
426 return IIO_VAL_INT;
427 case IIO_CHAN_INFO_SCALE:
428 *val = st->vref_uv / 1000;
429 *val2 = st->chip_info->bits;
430 return IIO_VAL_FRACTIONAL_LOG2;
431 default:
432 return -EINVAL;
433 }
434 return 0;
435 }
436
437 /* Applies to max1363 */
438 static const enum max1363_modes max1363_mode_list[] = {
439 _s0, _s1, _s2, _s3,
440 s0to1, s0to2, s0to3,
441 d0m1, d2m3, d1m0, d3m2,
442 d0m1to2m3, d1m0to3m2,
443 };
444
445 static const struct iio_event_spec max1363_events[] = {
446 {
447 .type = IIO_EV_TYPE_THRESH,
448 .dir = IIO_EV_DIR_RISING,
449 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
450 BIT(IIO_EV_INFO_ENABLE),
451 }, {
452 .type = IIO_EV_TYPE_THRESH,
453 .dir = IIO_EV_DIR_FALLING,
454 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
455 BIT(IIO_EV_INFO_ENABLE),
456 },
457 };
458
459 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
460 { \
461 .type = IIO_VOLTAGE, \
462 .indexed = 1, \
463 .channel = num, \
464 .address = addr, \
465 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
466 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
467 .datasheet_name = "AIN"#num, \
468 .scan_type = { \
469 .sign = 'u', \
470 .realbits = bits, \
471 .storagebits = (bits > 8) ? 16 : 8, \
472 .endianness = IIO_BE, \
473 }, \
474 .scan_index = si, \
475 .event_spec = ev_spec, \
476 .num_event_specs = num_ev_spec, \
477 }
478
479 /* bipolar channel */
480 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
481 { \
482 .type = IIO_VOLTAGE, \
483 .differential = 1, \
484 .indexed = 1, \
485 .channel = num, \
486 .channel2 = num2, \
487 .address = addr, \
488 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
489 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
490 .datasheet_name = "AIN"#num"-AIN"#num2, \
491 .scan_type = { \
492 .sign = 's', \
493 .realbits = bits, \
494 .storagebits = (bits > 8) ? 16 : 8, \
495 .endianness = IIO_BE, \
496 }, \
497 .scan_index = si, \
498 .event_spec = ev_spec, \
499 .num_event_specs = num_ev_spec, \
500 }
501
502 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
503 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
504 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
505 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
506 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
507 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, ev_spec, num_ev_spec), \
508 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, ev_spec, num_ev_spec), \
509 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, ev_spec, num_ev_spec), \
511 IIO_CHAN_SOFT_TIMESTAMP(8) \
512 }
513
514 static const struct iio_chan_spec max1036_channels[] =
515 MAX1363_4X_CHANS(8, NULL, 0);
516 static const struct iio_chan_spec max1136_channels[] =
517 MAX1363_4X_CHANS(10, NULL, 0);
518 static const struct iio_chan_spec max1236_channels[] =
519 MAX1363_4X_CHANS(12, NULL, 0);
520 static const struct iio_chan_spec max1361_channels[] =
521 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
522 static const struct iio_chan_spec max1363_channels[] =
523 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
524
525 /* Applies to max1236, max1237 */
526 static const enum max1363_modes max1236_mode_list[] = {
527 _s0, _s1, _s2, _s3,
528 s0to1, s0to2, s2to3, s0to3,
529 d0m1, d2m3, d1m0, d3m2,
530 d0m1to2m3, d1m0to3m2,
531 };
532
533 /* Applies to max1238, max1239 */
534 static const enum max1363_modes max1238_mode_list[] = {
535 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
536 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
537 s6to7, s6to8, s6to9, s6to10, s6to11,
538 s0to7, s0to8, s0to9, s0to10, s0to11,
539 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
540 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
541 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
542 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
543 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
544 d7m6to11m10, d1m0to11m10,
545 };
546
547 #define MAX1363_12X_CHANS(bits) { \
548 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
549 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
550 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
551 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
552 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
553 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
554 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
555 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
556 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
557 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
558 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
559 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
560 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
561 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
562 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
563 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
564 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
565 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
566 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
567 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
568 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
569 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
570 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
571 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
572 IIO_CHAN_SOFT_TIMESTAMP(24) \
573 }
574 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
575 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
576 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
577
578 static const enum max1363_modes max11607_mode_list[] = {
579 _s0, _s1, _s2, _s3,
580 s0to1, s0to2, s2to3,
581 s0to3,
582 d0m1, d2m3, d1m0, d3m2,
583 d0m1to2m3, d1m0to3m2,
584 };
585
586 static const enum max1363_modes max11608_mode_list[] = {
587 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
588 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s6to7, s0to7,
589 d0m1, d2m3, d4m5, d6m7,
590 d1m0, d3m2, d5m4, d7m6,
591 d0m1to2m3, d0m1to4m5, d0m1to6m7,
592 d1m0to3m2, d1m0to5m4, d1m0to7m6,
593 };
594
595 #define MAX1363_8X_CHANS(bits) { \
596 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
597 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
598 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
599 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
600 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
601 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
602 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
603 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
604 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
605 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
606 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
607 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
608 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
609 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
610 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
611 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
612 IIO_CHAN_SOFT_TIMESTAMP(16) \
613 }
614 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
615 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
616 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
617
618 static const enum max1363_modes max11644_mode_list[] = {
619 _s0, _s1, s0to1, d0m1, d1m0,
620 };
621
622 #define MAX1363_2X_CHANS(bits) { \
623 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
624 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
625 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
626 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
627 IIO_CHAN_SOFT_TIMESTAMP(4) \
628 }
629
630 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
631 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
632
633 enum { max1361,
634 max1362,
635 max1363,
636 max1364,
637 max1036,
638 max1037,
639 max1038,
640 max1039,
641 max1136,
642 max1137,
643 max1138,
644 max1139,
645 max1236,
646 max1237,
647 max1238,
648 max1239,
649 max11600,
650 max11601,
651 max11602,
652 max11603,
653 max11604,
654 max11605,
655 max11606,
656 max11607,
657 max11608,
658 max11609,
659 max11610,
660 max11611,
661 max11612,
662 max11613,
663 max11614,
664 max11615,
665 max11616,
666 max11617,
667 max11644,
668 max11645,
669 max11646,
670 max11647
671 };
672
673 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
674 8300, 4200, 2000, 1000 };
675
max1363_monitor_show_freq(struct device * dev,struct device_attribute * attr,char * buf)676 static ssize_t max1363_monitor_show_freq(struct device *dev,
677 struct device_attribute *attr,
678 char *buf)
679 {
680 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
681 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
682 }
683
max1363_monitor_store_freq(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)684 static ssize_t max1363_monitor_store_freq(struct device *dev,
685 struct device_attribute *attr,
686 const char *buf,
687 size_t len)
688 {
689 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
690 struct max1363_state *st = iio_priv(indio_dev);
691 int i, ret;
692 unsigned long val;
693 bool found = false;
694
695 ret = kstrtoul(buf, 10, &val);
696 if (ret)
697 return -EINVAL;
698 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
699 if (val == max1363_monitor_speeds[i]) {
700 found = true;
701 break;
702 }
703 if (!found)
704 return -EINVAL;
705
706 scoped_guard(mutex, &st->lock)
707 st->monitor_speed = i;
708
709 return 0;
710 }
711
712 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
713 max1363_monitor_show_freq,
714 max1363_monitor_store_freq);
715
716 static IIO_CONST_ATTR(sampling_frequency_available,
717 "133000 665000 33300 16600 8300 4200 2000 1000");
718
max1363_read_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)719 static int max1363_read_thresh(struct iio_dev *indio_dev,
720 const struct iio_chan_spec *chan, enum iio_event_type type,
721 enum iio_event_direction dir, enum iio_event_info info, int *val,
722 int *val2)
723 {
724 struct max1363_state *st = iio_priv(indio_dev);
725 if (dir == IIO_EV_DIR_FALLING)
726 *val = st->thresh_low[chan->channel];
727 else
728 *val = st->thresh_high[chan->channel];
729 return IIO_VAL_INT;
730 }
731
max1363_write_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)732 static int max1363_write_thresh(struct iio_dev *indio_dev,
733 const struct iio_chan_spec *chan, enum iio_event_type type,
734 enum iio_event_direction dir, enum iio_event_info info, int val,
735 int val2)
736 {
737 struct max1363_state *st = iio_priv(indio_dev);
738 /* make it handle signed correctly as well */
739 switch (st->chip_info->bits) {
740 case 10:
741 if (val > 0x3FF)
742 return -EINVAL;
743 break;
744 case 12:
745 if (val > 0xFFF)
746 return -EINVAL;
747 break;
748 }
749
750 switch (dir) {
751 case IIO_EV_DIR_FALLING:
752 st->thresh_low[chan->channel] = val;
753 break;
754 case IIO_EV_DIR_RISING:
755 st->thresh_high[chan->channel] = val;
756 break;
757 default:
758 return -EINVAL;
759 }
760
761 return 0;
762 }
763
764 static const u64 max1363_event_codes[] = {
765 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
766 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
767 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
768 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
769 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
770 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
771 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
772 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
773 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
774 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
781 };
782
max1363_event_handler(int irq,void * private)783 static irqreturn_t max1363_event_handler(int irq, void *private)
784 {
785 struct iio_dev *indio_dev = private;
786 struct max1363_state *st = iio_priv(indio_dev);
787 s64 timestamp = iio_get_time_ns(indio_dev);
788 unsigned long mask, loc;
789 u8 rx;
790 u8 tx[2] = { st->setupbyte,
791 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
792
793 st->recv(st->client, &rx, 1);
794 mask = rx;
795 for_each_set_bit(loc, &mask, 8)
796 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
797 st->send(st->client, tx, 2);
798
799 return IRQ_HANDLED;
800 }
801
max1363_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)802 static int max1363_read_event_config(struct iio_dev *indio_dev,
803 const struct iio_chan_spec *chan, enum iio_event_type type,
804 enum iio_event_direction dir)
805 {
806 struct max1363_state *st = iio_priv(indio_dev);
807 int val;
808 int number = chan->channel;
809
810 guard(mutex)(&st->lock);
811 if (dir == IIO_EV_DIR_FALLING)
812 val = (1 << number) & st->mask_low;
813 else
814 val = (1 << number) & st->mask_high;
815
816 return val;
817 }
818
max1363_monitor_mode_update(struct max1363_state * st,int enabled)819 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
820 {
821 int ret, i = 3, j;
822 unsigned long numelements;
823 int len;
824 const long *modemask;
825
826 if (!enabled) {
827 /* transition to buffered capture is not currently supported */
828 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
829 st->configbyte &= ~MAX1363_SCAN_MASK;
830 st->monitor_on = false;
831 return max1363_write_basic_config(st);
832 }
833
834 /* Ensure we are in the relevant mode */
835 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
836 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
837 | MAX1363_SCAN_MASK
838 | MAX1363_SE_DE_MASK);
839 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
840 if ((st->mask_low | st->mask_high) & 0x0F) {
841 st->configbyte |= max1363_mode_table[s0to3].conf;
842 modemask = max1363_mode_table[s0to3].modemask;
843 } else if ((st->mask_low | st->mask_high) & 0x30) {
844 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
845 modemask = max1363_mode_table[d0m1to2m3].modemask;
846 } else {
847 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
848 modemask = max1363_mode_table[d1m0to3m2].modemask;
849 }
850 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
851 len = 3 * numelements + 3;
852 u8 *tx_buf __free(kfree) = kmalloc(len, GFP_KERNEL);
853 if (!tx_buf)
854 return -ENOMEM;
855
856 tx_buf[0] = st->configbyte;
857 tx_buf[1] = st->setupbyte;
858 tx_buf[2] = (st->monitor_speed << 1);
859
860 /*
861 * So we need to do yet another bit of nefarious scan mode
862 * setup to match what we need.
863 */
864 for (j = 0; j < 8; j++)
865 if (test_bit(j, modemask)) {
866 /* Establish the mode is in the scan */
867 if (st->mask_low & (1 << j)) {
868 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
869 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
870 } else if (j < 4) {
871 tx_buf[i] = 0;
872 tx_buf[i + 1] = 0;
873 } else {
874 tx_buf[i] = 0x80;
875 tx_buf[i + 1] = 0;
876 }
877 if (st->mask_high & (1 << j)) {
878 tx_buf[i + 1] |=
879 (st->thresh_high[j] >> 8) & 0x0F;
880 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
881 } else if (j < 4) {
882 tx_buf[i + 1] |= 0x0F;
883 tx_buf[i + 2] = 0xFF;
884 } else {
885 tx_buf[i + 1] |= 0x07;
886 tx_buf[i + 2] = 0xFF;
887 }
888 i += 3;
889 }
890
891
892 ret = st->send(st->client, tx_buf, len);
893 if (ret < 0)
894 return ret;
895 if (ret != len)
896 return -EIO;
897
898 /*
899 * Now that we hopefully have sensible thresholds in place it is
900 * time to turn the interrupts on.
901 * It is unclear from the data sheet if this should be necessary
902 * (i.e. whether monitor mode setup is atomic) but it appears to
903 * be in practice.
904 */
905 tx_buf[0] = st->setupbyte;
906 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
907 ret = st->send(st->client, tx_buf, 2);
908 if (ret < 0)
909 return ret;
910 if (ret != 2)
911 return -EIO;
912
913 st->monitor_on = true;
914
915 return 0;
916 }
917
918 /*
919 * To keep this manageable we always use one of 3 scan modes.
920 * Scan 0...3, 0-1,2-3 and 1-0,3-2
921 */
922
__max1363_check_event_mask(int thismask,int checkmask)923 static inline int __max1363_check_event_mask(int thismask, int checkmask)
924 {
925 int ret = 0;
926 /* Is it unipolar */
927 if (thismask < 4) {
928 if (checkmask & ~0x0F) {
929 ret = -EBUSY;
930 goto error_ret;
931 }
932 } else if (thismask < 6) {
933 if (checkmask & ~0x30) {
934 ret = -EBUSY;
935 goto error_ret;
936 }
937 } else if (checkmask & ~0xC0)
938 ret = -EBUSY;
939 error_ret:
940 return ret;
941 }
942
max1363_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)943 static int max1363_write_event_config(struct iio_dev *indio_dev,
944 const struct iio_chan_spec *chan, enum iio_event_type type,
945 enum iio_event_direction dir, int state)
946 {
947 struct max1363_state *st = iio_priv(indio_dev);
948
949 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
950 int number = chan->channel;
951 u16 unifiedmask;
952 int ret;
953
954 guard(mutex)(&st->lock);
955
956 unifiedmask = st->mask_low | st->mask_high;
957 if (dir == IIO_EV_DIR_FALLING) {
958
959 if (state == 0)
960 st->mask_low &= ~(1 << number);
961 else {
962 ret = __max1363_check_event_mask((1 << number),
963 unifiedmask);
964 if (ret)
965 return ret;
966 st->mask_low |= (1 << number);
967 }
968 } else {
969 if (state == 0)
970 st->mask_high &= ~(1 << number);
971 else {
972 ret = __max1363_check_event_mask((1 << number),
973 unifiedmask);
974 if (ret)
975 return ret;
976 st->mask_high |= (1 << number);
977 }
978 }
979 }
980 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
981
982 return 0;
983 }
984
985 /*
986 * As with scan_elements, only certain sets of these can
987 * be combined.
988 */
989 static struct attribute *max1363_event_attributes[] = {
990 &iio_dev_attr_sampling_frequency.dev_attr.attr,
991 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
992 NULL,
993 };
994
995 static const struct attribute_group max1363_event_attribute_group = {
996 .attrs = max1363_event_attributes,
997 };
998
max1363_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)999 static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1000 const unsigned long *scan_mask)
1001 {
1002 struct max1363_state *st = iio_priv(indio_dev);
1003
1004 /*
1005 * Need to figure out the current mode based upon the requested
1006 * scan mask in iio_dev
1007 */
1008 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1009 if (!st->current_mode)
1010 return -EINVAL;
1011 max1363_set_scan_mode(st);
1012 return 0;
1013 }
1014
1015 static const struct iio_info max1238_info = {
1016 .read_raw = &max1363_read_raw,
1017 .update_scan_mode = &max1363_update_scan_mode,
1018 };
1019
1020 static const struct iio_info max1363_info = {
1021 .read_event_value = &max1363_read_thresh,
1022 .write_event_value = &max1363_write_thresh,
1023 .read_event_config = &max1363_read_event_config,
1024 .write_event_config = &max1363_write_event_config,
1025 .read_raw = &max1363_read_raw,
1026 .update_scan_mode = &max1363_update_scan_mode,
1027 .event_attrs = &max1363_event_attribute_group,
1028 };
1029
1030 /* max1363 and max1368 tested - rest from data sheet */
1031 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1032 [max1361] = {
1033 .bits = 10,
1034 .int_vref_mv = 2048,
1035 .mode_list = max1363_mode_list,
1036 .num_modes = ARRAY_SIZE(max1363_mode_list),
1037 .default_mode = s0to3,
1038 .channels = max1361_channels,
1039 .num_channels = ARRAY_SIZE(max1361_channels),
1040 .info = &max1363_info,
1041 },
1042 [max1362] = {
1043 .bits = 10,
1044 .int_vref_mv = 4096,
1045 .mode_list = max1363_mode_list,
1046 .num_modes = ARRAY_SIZE(max1363_mode_list),
1047 .default_mode = s0to3,
1048 .channels = max1361_channels,
1049 .num_channels = ARRAY_SIZE(max1361_channels),
1050 .info = &max1363_info,
1051 },
1052 [max1363] = {
1053 .bits = 12,
1054 .int_vref_mv = 2048,
1055 .mode_list = max1363_mode_list,
1056 .num_modes = ARRAY_SIZE(max1363_mode_list),
1057 .default_mode = s0to3,
1058 .channels = max1363_channels,
1059 .num_channels = ARRAY_SIZE(max1363_channels),
1060 .info = &max1363_info,
1061 },
1062 [max1364] = {
1063 .bits = 12,
1064 .int_vref_mv = 4096,
1065 .mode_list = max1363_mode_list,
1066 .num_modes = ARRAY_SIZE(max1363_mode_list),
1067 .default_mode = s0to3,
1068 .channels = max1363_channels,
1069 .num_channels = ARRAY_SIZE(max1363_channels),
1070 .info = &max1363_info,
1071 },
1072 [max1036] = {
1073 .bits = 8,
1074 .int_vref_mv = 4096,
1075 .mode_list = max1236_mode_list,
1076 .num_modes = ARRAY_SIZE(max1236_mode_list),
1077 .default_mode = s0to3,
1078 .info = &max1238_info,
1079 .channels = max1036_channels,
1080 .num_channels = ARRAY_SIZE(max1036_channels),
1081 },
1082 [max1037] = {
1083 .bits = 8,
1084 .int_vref_mv = 2048,
1085 .mode_list = max1236_mode_list,
1086 .num_modes = ARRAY_SIZE(max1236_mode_list),
1087 .default_mode = s0to3,
1088 .info = &max1238_info,
1089 .channels = max1036_channels,
1090 .num_channels = ARRAY_SIZE(max1036_channels),
1091 },
1092 [max1038] = {
1093 .bits = 8,
1094 .int_vref_mv = 4096,
1095 .mode_list = max1238_mode_list,
1096 .num_modes = ARRAY_SIZE(max1238_mode_list),
1097 .default_mode = s0to11,
1098 .info = &max1238_info,
1099 .channels = max1038_channels,
1100 .num_channels = ARRAY_SIZE(max1038_channels),
1101 },
1102 [max1039] = {
1103 .bits = 8,
1104 .int_vref_mv = 2048,
1105 .mode_list = max1238_mode_list,
1106 .num_modes = ARRAY_SIZE(max1238_mode_list),
1107 .default_mode = s0to11,
1108 .info = &max1238_info,
1109 .channels = max1038_channels,
1110 .num_channels = ARRAY_SIZE(max1038_channels),
1111 },
1112 [max1136] = {
1113 .bits = 10,
1114 .int_vref_mv = 4096,
1115 .mode_list = max1236_mode_list,
1116 .num_modes = ARRAY_SIZE(max1236_mode_list),
1117 .default_mode = s0to3,
1118 .info = &max1238_info,
1119 .channels = max1136_channels,
1120 .num_channels = ARRAY_SIZE(max1136_channels),
1121 },
1122 [max1137] = {
1123 .bits = 10,
1124 .int_vref_mv = 2048,
1125 .mode_list = max1236_mode_list,
1126 .num_modes = ARRAY_SIZE(max1236_mode_list),
1127 .default_mode = s0to3,
1128 .info = &max1238_info,
1129 .channels = max1136_channels,
1130 .num_channels = ARRAY_SIZE(max1136_channels),
1131 },
1132 [max1138] = {
1133 .bits = 10,
1134 .int_vref_mv = 4096,
1135 .mode_list = max1238_mode_list,
1136 .num_modes = ARRAY_SIZE(max1238_mode_list),
1137 .default_mode = s0to11,
1138 .info = &max1238_info,
1139 .channels = max1138_channels,
1140 .num_channels = ARRAY_SIZE(max1138_channels),
1141 },
1142 [max1139] = {
1143 .bits = 10,
1144 .int_vref_mv = 2048,
1145 .mode_list = max1238_mode_list,
1146 .num_modes = ARRAY_SIZE(max1238_mode_list),
1147 .default_mode = s0to11,
1148 .info = &max1238_info,
1149 .channels = max1138_channels,
1150 .num_channels = ARRAY_SIZE(max1138_channels),
1151 },
1152 [max1236] = {
1153 .bits = 12,
1154 .int_vref_mv = 4096,
1155 .mode_list = max1236_mode_list,
1156 .num_modes = ARRAY_SIZE(max1236_mode_list),
1157 .default_mode = s0to3,
1158 .info = &max1238_info,
1159 .channels = max1236_channels,
1160 .num_channels = ARRAY_SIZE(max1236_channels),
1161 },
1162 [max1237] = {
1163 .bits = 12,
1164 .int_vref_mv = 2048,
1165 .mode_list = max1236_mode_list,
1166 .num_modes = ARRAY_SIZE(max1236_mode_list),
1167 .default_mode = s0to3,
1168 .info = &max1238_info,
1169 .channels = max1236_channels,
1170 .num_channels = ARRAY_SIZE(max1236_channels),
1171 },
1172 [max1238] = {
1173 .bits = 12,
1174 .int_vref_mv = 4096,
1175 .mode_list = max1238_mode_list,
1176 .num_modes = ARRAY_SIZE(max1238_mode_list),
1177 .default_mode = s0to11,
1178 .info = &max1238_info,
1179 .channels = max1238_channels,
1180 .num_channels = ARRAY_SIZE(max1238_channels),
1181 },
1182 [max1239] = {
1183 .bits = 12,
1184 .int_vref_mv = 2048,
1185 .mode_list = max1238_mode_list,
1186 .num_modes = ARRAY_SIZE(max1238_mode_list),
1187 .default_mode = s0to11,
1188 .info = &max1238_info,
1189 .channels = max1238_channels,
1190 .num_channels = ARRAY_SIZE(max1238_channels),
1191 },
1192 [max11600] = {
1193 .bits = 8,
1194 .int_vref_mv = 4096,
1195 .mode_list = max11607_mode_list,
1196 .num_modes = ARRAY_SIZE(max11607_mode_list),
1197 .default_mode = s0to3,
1198 .info = &max1238_info,
1199 .channels = max1036_channels,
1200 .num_channels = ARRAY_SIZE(max1036_channels),
1201 },
1202 [max11601] = {
1203 .bits = 8,
1204 .int_vref_mv = 2048,
1205 .mode_list = max11607_mode_list,
1206 .num_modes = ARRAY_SIZE(max11607_mode_list),
1207 .default_mode = s0to3,
1208 .info = &max1238_info,
1209 .channels = max1036_channels,
1210 .num_channels = ARRAY_SIZE(max1036_channels),
1211 },
1212 [max11602] = {
1213 .bits = 8,
1214 .int_vref_mv = 4096,
1215 .mode_list = max11608_mode_list,
1216 .num_modes = ARRAY_SIZE(max11608_mode_list),
1217 .default_mode = s0to7,
1218 .info = &max1238_info,
1219 .channels = max11602_channels,
1220 .num_channels = ARRAY_SIZE(max11602_channels),
1221 },
1222 [max11603] = {
1223 .bits = 8,
1224 .int_vref_mv = 2048,
1225 .mode_list = max11608_mode_list,
1226 .num_modes = ARRAY_SIZE(max11608_mode_list),
1227 .default_mode = s0to7,
1228 .info = &max1238_info,
1229 .channels = max11602_channels,
1230 .num_channels = ARRAY_SIZE(max11602_channels),
1231 },
1232 [max11604] = {
1233 .bits = 8,
1234 .int_vref_mv = 4096,
1235 .mode_list = max1238_mode_list,
1236 .num_modes = ARRAY_SIZE(max1238_mode_list),
1237 .default_mode = s0to11,
1238 .info = &max1238_info,
1239 .channels = max1038_channels,
1240 .num_channels = ARRAY_SIZE(max1038_channels),
1241 },
1242 [max11605] = {
1243 .bits = 8,
1244 .int_vref_mv = 2048,
1245 .mode_list = max1238_mode_list,
1246 .num_modes = ARRAY_SIZE(max1238_mode_list),
1247 .default_mode = s0to11,
1248 .info = &max1238_info,
1249 .channels = max1038_channels,
1250 .num_channels = ARRAY_SIZE(max1038_channels),
1251 },
1252 [max11606] = {
1253 .bits = 10,
1254 .int_vref_mv = 4096,
1255 .mode_list = max11607_mode_list,
1256 .num_modes = ARRAY_SIZE(max11607_mode_list),
1257 .default_mode = s0to3,
1258 .info = &max1238_info,
1259 .channels = max1136_channels,
1260 .num_channels = ARRAY_SIZE(max1136_channels),
1261 },
1262 [max11607] = {
1263 .bits = 10,
1264 .int_vref_mv = 2048,
1265 .mode_list = max11607_mode_list,
1266 .num_modes = ARRAY_SIZE(max11607_mode_list),
1267 .default_mode = s0to3,
1268 .info = &max1238_info,
1269 .channels = max1136_channels,
1270 .num_channels = ARRAY_SIZE(max1136_channels),
1271 },
1272 [max11608] = {
1273 .bits = 10,
1274 .int_vref_mv = 4096,
1275 .mode_list = max11608_mode_list,
1276 .num_modes = ARRAY_SIZE(max11608_mode_list),
1277 .default_mode = s0to7,
1278 .info = &max1238_info,
1279 .channels = max11608_channels,
1280 .num_channels = ARRAY_SIZE(max11608_channels),
1281 },
1282 [max11609] = {
1283 .bits = 10,
1284 .int_vref_mv = 2048,
1285 .mode_list = max11608_mode_list,
1286 .num_modes = ARRAY_SIZE(max11608_mode_list),
1287 .default_mode = s0to7,
1288 .info = &max1238_info,
1289 .channels = max11608_channels,
1290 .num_channels = ARRAY_SIZE(max11608_channels),
1291 },
1292 [max11610] = {
1293 .bits = 10,
1294 .int_vref_mv = 4096,
1295 .mode_list = max1238_mode_list,
1296 .num_modes = ARRAY_SIZE(max1238_mode_list),
1297 .default_mode = s0to11,
1298 .info = &max1238_info,
1299 .channels = max1138_channels,
1300 .num_channels = ARRAY_SIZE(max1138_channels),
1301 },
1302 [max11611] = {
1303 .bits = 10,
1304 .int_vref_mv = 2048,
1305 .mode_list = max1238_mode_list,
1306 .num_modes = ARRAY_SIZE(max1238_mode_list),
1307 .default_mode = s0to11,
1308 .info = &max1238_info,
1309 .channels = max1138_channels,
1310 .num_channels = ARRAY_SIZE(max1138_channels),
1311 },
1312 [max11612] = {
1313 .bits = 12,
1314 .int_vref_mv = 4096,
1315 .mode_list = max11607_mode_list,
1316 .num_modes = ARRAY_SIZE(max11607_mode_list),
1317 .default_mode = s0to3,
1318 .info = &max1238_info,
1319 .channels = max1363_channels,
1320 .num_channels = ARRAY_SIZE(max1363_channels),
1321 },
1322 [max11613] = {
1323 .bits = 12,
1324 .int_vref_mv = 2048,
1325 .mode_list = max11607_mode_list,
1326 .num_modes = ARRAY_SIZE(max11607_mode_list),
1327 .default_mode = s0to3,
1328 .info = &max1238_info,
1329 .channels = max1363_channels,
1330 .num_channels = ARRAY_SIZE(max1363_channels),
1331 },
1332 [max11614] = {
1333 .bits = 12,
1334 .int_vref_mv = 4096,
1335 .mode_list = max11608_mode_list,
1336 .num_modes = ARRAY_SIZE(max11608_mode_list),
1337 .default_mode = s0to7,
1338 .info = &max1238_info,
1339 .channels = max11614_channels,
1340 .num_channels = ARRAY_SIZE(max11614_channels),
1341 },
1342 [max11615] = {
1343 .bits = 12,
1344 .int_vref_mv = 2048,
1345 .mode_list = max11608_mode_list,
1346 .num_modes = ARRAY_SIZE(max11608_mode_list),
1347 .default_mode = s0to7,
1348 .info = &max1238_info,
1349 .channels = max11614_channels,
1350 .num_channels = ARRAY_SIZE(max11614_channels),
1351 },
1352 [max11616] = {
1353 .bits = 12,
1354 .int_vref_mv = 4096,
1355 .mode_list = max1238_mode_list,
1356 .num_modes = ARRAY_SIZE(max1238_mode_list),
1357 .default_mode = s0to11,
1358 .info = &max1238_info,
1359 .channels = max1238_channels,
1360 .num_channels = ARRAY_SIZE(max1238_channels),
1361 },
1362 [max11617] = {
1363 .bits = 12,
1364 .int_vref_mv = 2048,
1365 .mode_list = max1238_mode_list,
1366 .num_modes = ARRAY_SIZE(max1238_mode_list),
1367 .default_mode = s0to11,
1368 .info = &max1238_info,
1369 .channels = max1238_channels,
1370 .num_channels = ARRAY_SIZE(max1238_channels),
1371 },
1372 [max11644] = {
1373 .bits = 12,
1374 .int_vref_mv = 4096,
1375 .mode_list = max11644_mode_list,
1376 .num_modes = ARRAY_SIZE(max11644_mode_list),
1377 .default_mode = s0to1,
1378 .info = &max1238_info,
1379 .channels = max11644_channels,
1380 .num_channels = ARRAY_SIZE(max11644_channels),
1381 },
1382 [max11645] = {
1383 .bits = 12,
1384 .int_vref_mv = 2048,
1385 .mode_list = max11644_mode_list,
1386 .num_modes = ARRAY_SIZE(max11644_mode_list),
1387 .default_mode = s0to1,
1388 .info = &max1238_info,
1389 .channels = max11644_channels,
1390 .num_channels = ARRAY_SIZE(max11644_channels),
1391 },
1392 [max11646] = {
1393 .bits = 10,
1394 .int_vref_mv = 4096,
1395 .mode_list = max11644_mode_list,
1396 .num_modes = ARRAY_SIZE(max11644_mode_list),
1397 .default_mode = s0to1,
1398 .info = &max1238_info,
1399 .channels = max11646_channels,
1400 .num_channels = ARRAY_SIZE(max11646_channels),
1401 },
1402 [max11647] = {
1403 .bits = 10,
1404 .int_vref_mv = 2048,
1405 .mode_list = max11644_mode_list,
1406 .num_modes = ARRAY_SIZE(max11644_mode_list),
1407 .default_mode = s0to1,
1408 .info = &max1238_info,
1409 .channels = max11646_channels,
1410 .num_channels = ARRAY_SIZE(max11646_channels),
1411 },
1412 };
1413
max1363_initial_setup(struct max1363_state * st)1414 static int max1363_initial_setup(struct max1363_state *st)
1415 {
1416 st->setupbyte = MAX1363_SETUP_INT_CLOCK
1417 | MAX1363_SETUP_UNIPOLAR
1418 | MAX1363_SETUP_NORESET;
1419
1420 if (st->vref)
1421 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1422 else
1423 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1424 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1425
1426 /* Set scan mode writes the config anyway so wait until then */
1427 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1428 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1429 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1430
1431 return max1363_set_scan_mode(st);
1432 }
1433
max1363_alloc_scan_masks(struct iio_dev * indio_dev)1434 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1435 {
1436 struct max1363_state *st = iio_priv(indio_dev);
1437 unsigned long *masks;
1438 int i;
1439
1440 masks = devm_kzalloc(&indio_dev->dev,
1441 array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
1442 sizeof(long),
1443 st->chip_info->num_modes + 1),
1444 GFP_KERNEL);
1445 if (!masks)
1446 return -ENOMEM;
1447
1448 for (i = 0; i < st->chip_info->num_modes; i++)
1449 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1450 max1363_mode_table[st->chip_info->mode_list[i]]
1451 .modemask, MAX1363_MAX_CHANNELS);
1452
1453 indio_dev->available_scan_masks = masks;
1454
1455 return 0;
1456 }
1457
max1363_trigger_handler(int irq,void * p)1458 static irqreturn_t max1363_trigger_handler(int irq, void *p)
1459 {
1460 struct iio_poll_func *pf = p;
1461 struct iio_dev *indio_dev = pf->indio_dev;
1462 struct max1363_state *st = iio_priv(indio_dev);
1463 __u8 *rxbuf;
1464 int b_sent;
1465 size_t d_size;
1466 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1467 MAX1363_MAX_CHANNELS);
1468
1469 /* Ensure the timestamp is 8 byte aligned */
1470 if (st->chip_info->bits != 8)
1471 d_size = numvals*2;
1472 else
1473 d_size = numvals;
1474 if (indio_dev->scan_timestamp) {
1475 d_size += sizeof(s64);
1476 if (d_size % sizeof(s64))
1477 d_size += sizeof(s64) - (d_size % sizeof(s64));
1478 }
1479 /* Monitor mode prevents reading. Whilst not currently implemented
1480 * might as well have this test in here in the meantime as it does
1481 * no harm.
1482 */
1483 if (numvals == 0)
1484 goto done;
1485
1486 rxbuf = kmalloc(d_size, GFP_KERNEL);
1487 if (rxbuf == NULL)
1488 goto done;
1489 if (st->chip_info->bits != 8)
1490 b_sent = st->recv(st->client, rxbuf, numvals * 2);
1491 else
1492 b_sent = st->recv(st->client, rxbuf, numvals);
1493 if (b_sent < 0)
1494 goto done_free;
1495
1496 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
1497 iio_get_time_ns(indio_dev));
1498
1499 done_free:
1500 kfree(rxbuf);
1501 done:
1502 iio_trigger_notify_done(indio_dev->trig);
1503
1504 return IRQ_HANDLED;
1505 }
1506
1507 #define MAX1363_COMPATIBLE(of_compatible, cfg) { \
1508 .compatible = of_compatible, \
1509 .data = &max1363_chip_info_tbl[cfg], \
1510 }
1511
1512 static const struct of_device_id max1363_of_match[] = {
1513 MAX1363_COMPATIBLE("maxim,max1361", max1361),
1514 MAX1363_COMPATIBLE("maxim,max1362", max1362),
1515 MAX1363_COMPATIBLE("maxim,max1363", max1363),
1516 MAX1363_COMPATIBLE("maxim,max1364", max1364),
1517 MAX1363_COMPATIBLE("maxim,max1036", max1036),
1518 MAX1363_COMPATIBLE("maxim,max1037", max1037),
1519 MAX1363_COMPATIBLE("maxim,max1038", max1038),
1520 MAX1363_COMPATIBLE("maxim,max1039", max1039),
1521 MAX1363_COMPATIBLE("maxim,max1136", max1136),
1522 MAX1363_COMPATIBLE("maxim,max1137", max1137),
1523 MAX1363_COMPATIBLE("maxim,max1138", max1138),
1524 MAX1363_COMPATIBLE("maxim,max1139", max1139),
1525 MAX1363_COMPATIBLE("maxim,max1236", max1236),
1526 MAX1363_COMPATIBLE("maxim,max1237", max1237),
1527 MAX1363_COMPATIBLE("maxim,max1238", max1238),
1528 MAX1363_COMPATIBLE("maxim,max1239", max1239),
1529 MAX1363_COMPATIBLE("maxim,max11600", max11600),
1530 MAX1363_COMPATIBLE("maxim,max11601", max11601),
1531 MAX1363_COMPATIBLE("maxim,max11602", max11602),
1532 MAX1363_COMPATIBLE("maxim,max11603", max11603),
1533 MAX1363_COMPATIBLE("maxim,max11604", max11604),
1534 MAX1363_COMPATIBLE("maxim,max11605", max11605),
1535 MAX1363_COMPATIBLE("maxim,max11606", max11606),
1536 MAX1363_COMPATIBLE("maxim,max11607", max11607),
1537 MAX1363_COMPATIBLE("maxim,max11608", max11608),
1538 MAX1363_COMPATIBLE("maxim,max11609", max11609),
1539 MAX1363_COMPATIBLE("maxim,max11610", max11610),
1540 MAX1363_COMPATIBLE("maxim,max11611", max11611),
1541 MAX1363_COMPATIBLE("maxim,max11612", max11612),
1542 MAX1363_COMPATIBLE("maxim,max11613", max11613),
1543 MAX1363_COMPATIBLE("maxim,max11614", max11614),
1544 MAX1363_COMPATIBLE("maxim,max11615", max11615),
1545 MAX1363_COMPATIBLE("maxim,max11616", max11616),
1546 MAX1363_COMPATIBLE("maxim,max11617", max11617),
1547 MAX1363_COMPATIBLE("maxim,max11644", max11644),
1548 MAX1363_COMPATIBLE("maxim,max11645", max11645),
1549 MAX1363_COMPATIBLE("maxim,max11646", max11646),
1550 MAX1363_COMPATIBLE("maxim,max11647", max11647),
1551 { /* sentinel */ }
1552 };
1553 MODULE_DEVICE_TABLE(of, max1363_of_match);
1554
max1363_probe(struct i2c_client * client)1555 static int max1363_probe(struct i2c_client *client)
1556 {
1557 const struct i2c_device_id *id = i2c_client_get_device_id(client);
1558 int ret;
1559 struct max1363_state *st;
1560 struct iio_dev *indio_dev;
1561
1562 indio_dev = devm_iio_device_alloc(&client->dev,
1563 sizeof(struct max1363_state));
1564 if (!indio_dev)
1565 return -ENOMEM;
1566
1567 st = iio_priv(indio_dev);
1568
1569 mutex_init(&st->lock);
1570 ret = devm_regulator_get_enable(&client->dev, "vcc");
1571 if (ret)
1572 return ret;
1573
1574 st->chip_info = i2c_get_match_data(client);
1575 st->client = client;
1576
1577 ret = devm_regulator_get_enable_read_voltage(&client->dev, "vref");
1578 if (ret < 0 && ret != -ENODEV)
1579 return ret;
1580
1581
1582 st->vref_uv = ret == -ENODEV ? st->chip_info->int_vref_mv * 1000 : ret;
1583
1584 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1585 st->send = i2c_master_send;
1586 st->recv = i2c_master_recv;
1587 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1588 && st->chip_info->bits == 8) {
1589 st->send = max1363_smbus_send;
1590 st->recv = max1363_smbus_recv;
1591 } else {
1592 return -EOPNOTSUPP;
1593 }
1594
1595 ret = max1363_alloc_scan_masks(indio_dev);
1596 if (ret)
1597 return ret;
1598
1599 indio_dev->name = id->name;
1600 indio_dev->channels = st->chip_info->channels;
1601 indio_dev->num_channels = st->chip_info->num_channels;
1602 indio_dev->info = st->chip_info->info;
1603 indio_dev->modes = INDIO_DIRECT_MODE;
1604 ret = max1363_initial_setup(st);
1605 if (ret < 0)
1606 return ret;
1607
1608 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1609 &max1363_trigger_handler, NULL);
1610 if (ret)
1611 return ret;
1612
1613 if (client->irq) {
1614 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1615 NULL,
1616 &max1363_event_handler,
1617 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1618 "max1363_event",
1619 indio_dev);
1620
1621 if (ret)
1622 return ret;
1623 }
1624
1625 return devm_iio_device_register(&client->dev, indio_dev);
1626 }
1627
1628 #define MAX1363_ID_TABLE(_name, cfg) { \
1629 .name = _name, \
1630 .driver_data = (kernel_ulong_t)&max1363_chip_info_tbl[cfg], \
1631 }
1632
1633 static const struct i2c_device_id max1363_id[] = {
1634 MAX1363_ID_TABLE("max1361", max1361),
1635 MAX1363_ID_TABLE("max1362", max1362),
1636 MAX1363_ID_TABLE("max1363", max1363),
1637 MAX1363_ID_TABLE("max1364", max1364),
1638 MAX1363_ID_TABLE("max1036", max1036),
1639 MAX1363_ID_TABLE("max1037", max1037),
1640 MAX1363_ID_TABLE("max1038", max1038),
1641 MAX1363_ID_TABLE("max1039", max1039),
1642 MAX1363_ID_TABLE("max1136", max1136),
1643 MAX1363_ID_TABLE("max1137", max1137),
1644 MAX1363_ID_TABLE("max1138", max1138),
1645 MAX1363_ID_TABLE("max1139", max1139),
1646 MAX1363_ID_TABLE("max1236", max1236),
1647 MAX1363_ID_TABLE("max1237", max1237),
1648 MAX1363_ID_TABLE("max1238", max1238),
1649 MAX1363_ID_TABLE("max1239", max1239),
1650 MAX1363_ID_TABLE("max11600", max11600),
1651 MAX1363_ID_TABLE("max11601", max11601),
1652 MAX1363_ID_TABLE("max11602", max11602),
1653 MAX1363_ID_TABLE("max11603", max11603),
1654 MAX1363_ID_TABLE("max11604", max11604),
1655 MAX1363_ID_TABLE("max11605", max11605),
1656 MAX1363_ID_TABLE("max11606", max11606),
1657 MAX1363_ID_TABLE("max11607", max11607),
1658 MAX1363_ID_TABLE("max11608", max11608),
1659 MAX1363_ID_TABLE("max11609", max11609),
1660 MAX1363_ID_TABLE("max11610", max11610),
1661 MAX1363_ID_TABLE("max11611", max11611),
1662 MAX1363_ID_TABLE("max11612", max11612),
1663 MAX1363_ID_TABLE("max11613", max11613),
1664 MAX1363_ID_TABLE("max11614", max11614),
1665 MAX1363_ID_TABLE("max11615", max11615),
1666 MAX1363_ID_TABLE("max11616", max11616),
1667 MAX1363_ID_TABLE("max11617", max11617),
1668 MAX1363_ID_TABLE("max11644", max11644),
1669 MAX1363_ID_TABLE("max11645", max11645),
1670 MAX1363_ID_TABLE("max11646", max11646),
1671 MAX1363_ID_TABLE("max11647", max11647),
1672 { /* sentinel */ }
1673 };
1674
1675 MODULE_DEVICE_TABLE(i2c, max1363_id);
1676
1677 static struct i2c_driver max1363_driver = {
1678 .driver = {
1679 .name = "max1363",
1680 .of_match_table = max1363_of_match,
1681 },
1682 .probe = max1363_probe,
1683 .id_table = max1363_id,
1684 };
1685 module_i2c_driver(max1363_driver);
1686
1687 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1688 MODULE_DESCRIPTION("Maxim 1363 ADC");
1689 MODULE_LICENSE("GPL v2");
1690