Searched +full:1 +full:- +full:bit (Results 1 – 25 of 1038) sorted by relevance
12345678910>>...42
| /Documentation/ABI/testing/ |
| D | sysfs-driver-zynqmp-fpga | 1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
7 of the FPGA device. Each bit position in the status value is
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
12 BIT(0) 0: No CRC error
13 1: CRC error
15 BIT(1) 0: Decryptor security not set
16 1: Decryptor security set
18 BIT(2) 0: MMCMs/PLLs are not locked
19 1: MMCMs/PLLs are locked
21 BIT(3) 0: DCI not matched
[all …]
|
| /Documentation/devicetree/bindings/mfd/ |
| D | mc13xxx.txt | 4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
[all …]
|
| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec2.txt | 1 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
5 - compatible : Should contain entries for this and backward compatible
6 SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
9 - reg : Offset and length of the register set for the device
10 - interrupts : the SEC's interrupt number
11 - fsl,num-channels : An integer representing the number of channels
13 - fsl,channel-fifo-len : An integer representing the number of
15 - fsl,exec-units-mask : The bitmask representing what execution units
16 (EUs) are available. It's a single 32-bit cell. EU information
20 bit 0 = reserved - should be 0
[all …]
|
| /Documentation/devicetree/bindings/timer/ |
| D | renesas,cmt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
[all …]
|
| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-74xx-mmio.txt | 4 - compatible: Should contain one of the following:
5 "ti,741g125": for 741G125 (1-bit Input),
6 "ti,741g174": for 741G74 (1-bit Output),
7 "ti,742g125": for 742G125 (2-bit Input),
8 "ti,7474" : for 7474 (2-bit Output),
9 "ti,74125" : for 74125 (4-bit Input),
10 "ti,74175" : for 74175 (4-bit Output),
11 "ti,74365" : for 74365 (6-bit Input),
12 "ti,74174" : for 74174 (6-bit Output),
13 "ti,74244" : for 74244 (8-bit Input),
[all …]
|
| /Documentation/arch/arm64/ |
| D | asymmetric-32bit.rst | 2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
[all …]
|
| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
15 1. The request line number
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
[all …]
|
| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
15 1. The channel id
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
[all …]
|
| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
45 - isa
52 implementation that lacks the "transactional-memory" cpufeature node
[all …]
|
| /Documentation/devicetree/bindings/hwmon/ |
| D | max6697.txt | 4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
23 - extended-range-enable
26 - beta-compensation-enable
28 remote temperature channel 1.
30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
32 Select bit 0 for local temperature, bit 1..7 for remote temperatures.
34 - over-temperature-mask
[all …]
|
| /Documentation/input/devices/ |
| D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
6 Extra information for hardware version 1 found and
15 1. Introduction
18 4. Hardware version 1
25 5.2.1 Parity checking and packet re-synchronization
31 6.2.1 One/Three finger touch
36 7.2.1 Status packet
42 8.2.1 Status Packet
50 hardware versions unimaginatively called version 1,version 2, version 3
51 and version 4. Version 1 is found in "older" laptops and uses 4 bytes per
[all …]
|
| /Documentation/userspace-api/media/rc/ |
| D | rc-protos.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
38 .. flat-table:: rc5 bits scancode mapping
39 :widths: 1 1 2
41 * - rc-5 bit
43 - scancode bit
[all …]
|
| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 3 The ECC Manager counts and corrects single bit errors and counts/handles
4 double bit errors which are uncorrectable.
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
24 - compatible : Should be "altr,socfpga-ocram-ecc"
[all …]
|
| /Documentation/PCI/endpoint/ |
| D | pci-test-function.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 However with the addition of EP-core in linux kernel, it is possible
21 1) PCI_ENDPOINT_TEST_MAGIC
44 Bit 0 raise legacy IRQ
45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
47 Bit 3 read command (read data from RC buffer)
48 Bit 4 write command (write data to RC buffer)
49 Bit 5 copy command (copy data from one RC buffer to another RC buffer)
59 Bit 0 read success
[all …]
|
| /Documentation/arch/riscv/ |
| D | vector.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
10 1. prctl() Interface
11 ---------------------
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
21 please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
33 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
[all …]
|
| /Documentation/devicetree/bindings/leds/ |
| D | register-bit-led.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/register-bit-led.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Register Bit LEDs
10 - Linus Walleij <linus.walleij@linaro.org>
13 Register bit leds are used with syscon multifunctional devices where single
14 bits in a certain register can turn on/off a single LED. The register bit LEDs
20 - $ref: /schemas/leds/common.yaml#
25 The unit-address is in the form of @<reg addr>,<bit offset>
[all …]
|
| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-sdr-pcu16be.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU16BE:
9 Planar complex unsigned 16-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
16 and Q are represented as a 16 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
20 the 16 bits, bit 15:2 (14 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
28 :stub-columns: 0
[all …]
|
| D | pixfmt-sdr-pcu18be.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU18BE:
9 Planar complex unsigned 18-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
16 and Q are represented as a 18 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
20 the 18 bits, bit 17:2 (16 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
28 :stub-columns: 0
[all …]
|
| /Documentation/devicetree/bindings/sound/ |
| D | everest,es8326.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Yang <yangxiaohua@everest-semi.com>
17 maxItems: 1
21 - description: clock for master clock (MCLK)
23 clock-names:
25 - const: mclk
27 "#sound-dai-cells":
30 everest,jack-pol:
[all …]
|
| /Documentation/devicetree/bindings/clock/ti/ |
| D | autoidle.txt | 3 This binding uses the common clock binding[1]. It assumes a register mapped
5 and a configuration bit setting. Autoidle clock is never an individual
7 or fixed-factor.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - reg : offset for the register controlling the autoidle
13 - ti,autoidle-shift : bit shift of the autoidle enable bit
14 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
18 #clock-cells = <0>;
19 compatible = "ti,divider-clock";
21 ti,max-div = <31>;
[all …]
|
| /Documentation/networking/ |
| D | oa-tc6-framework.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
[all …]
|
| /Documentation/gpu/ |
| D | afbc.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
32 * Component 1: G
37 reside in the least-significant bits of the corresponding linear
43 * Component 1: G(8)
50 * Component 1: G(8)
56 * Component 1: Cb(8, 2x1 subsampled)
66 * Component 1: G(8)
75 '1'. If there is no requirement for a fourth component, then a format
[all …]
|
| /Documentation/w1/masters/ |
| D | w1-uart.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 …ng a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
[all …]
|
| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci.txt | 2 host controllers refer to the mmc[1] bindings.
4 [1] Documentation/devicetree/bindings/mmc/mmc.txt
7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
9 is on in the mask then the bit is incorrect in the register and should be
10 turned off, before applying sdhci-caps.
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
13 bit is on in the property then the bit should be turned on.
|
| /Documentation/networking/device_drivers/cellular/qualcomm/ |
| D | rmnet.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 1. Introduction
24 sending aggregated bunch of MAP frames. rmnet driver will de-aggregate
36 Bit 0 1 2-7 8-15 16-31
39 Bit 32-x
42 Command (1)/ Data (0) bit value is to indicate if the packet is a MAP command
62 Bit 0 1 2-7 8-15 16-31
65 Bit 32-(x-33) (x-32)-x
68 Command (1)/ Data (0) bit value is to indicate if the packet is a MAP command
87 Bit 0-14 15 16-31
[all …]
|
12345678910>>...42