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/Documentation/devicetree/bindings/mtd/
Damlogic,meson-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
10 - $ref: nand-controller.yaml
13 - liang.yang@amlogic.com
18 - amlogic,meson-gxl-nfc
19 - amlogic,meson-axg-nfc
24 reg-names:
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Drockchip,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoCs NAND FLASH Controller (NFC)
10 - $ref: nand-controller.yaml#
13 - Heiko Stuebner <heiko@sntech.de>
18 - const: rockchip,px30-nfc
19 - const: rockchip,rk2928-nfc
20 - const: rockchip,rv1108-nfc
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Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NAND controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
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Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs NAND controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
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Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raw NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
19 {size} bytes for a particular raw NAND chip.
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
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Dsamsung-s3c2410.txt1 * Samsung S3C2410 and compatible NAND flash controller
4 - compatible : The possible values are:
5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
8 - reg : register's location and length.
9 - #address-cells, #size-cells : see nand-controller.yaml
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
14 Child nodes representing the available nand chips.
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Dorion-nand.txt1 NAND support for Marvell Orion SoC platforms
4 - compatible : "marvell,orion-nand".
5 - reg : Base physical address of the NAND and length of memory mapped
9 - cle : Address line number connected to CLE. Default is 0
10 - ale : Address line number connected to ALE. Default is 1
11 - bank-width : Width in bytes of the device. Default is 1
12 - chip-delay : Chip dependent delay for transferring data from array to read
15 The device tree may optionally contain sub-nodes describing partitions of the
20 nand@f4000000 {
21 #address-cells = <1>;
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Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
27 -- Additional SoC-specific NAND controller properties --
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Dlpc32xx-mlc.txt1 NXP LPC32xx SoC NAND MLC controller
4 - compatible: "nxp,lpc3220-mlc"
5 - reg: Address and size of the controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
13 - nxp,tcea_delay: TCEA_DELAY
14 - nxp,busy_delay: BUSY_DELAY
15 - nxp,nand_ta: NAND_TA
16 - nxp,rd_high: RD_HIGH
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Dlpc32xx-slc.txt1 NXP LPC32xx SoC NAND SLC controller
4 - compatible: "nxp,lpc3220-slc"
5 - reg: Address and size of the controller
6 - nand-on-flash-bbt: Use bad block table on flash
7 - gpios: GPIO specification for NAND write protect
11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
15 - nxp,wwidth: Write pulse width (W_WIDTH)
16 - nxp,whold: Write hold time (W_HOLD)
17 - nxp,wsetup: Write setup time (W_SETUP)
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/Documentation/devicetree/bindings/mfd/
Dhi6421.txt1 * HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
4 - compatible : One of the following chip-specific strings:
5 "hisilicon,hi6421-pmic";
6 "hisilicon,hi6421v530-pmic";
7 - reg : register range space of hi6421;
9 Supported Hi6421 sub-devices include:
12 ------ --------- ------------ -----------
20 compatible = "hisilicon,hi6421-pmic";
24 // supply for MLC NAND/ eMMC
26 regulator-name = "VOUT0";
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/Documentation/filesystems/
Dubifs.rst1 .. SPDX-License-Identifier: GPL-2.0
10 UBIFS file-system stands for UBI File System. UBI stands for "Unsorted
13 is completely different to any traditional file-system in Linux, like
14 Ext2, XFS, JFS, etc. UBIFS represents a separate class of file-systems
16 file-system of this class is JFFS2.
24 2 MTD devices support 3 main operations - read from some offset within an
26 eraseblock. Block devices support 2 main operations - read a whole
29 re-write its contents. Blocks may be just re-written.
30 4 Eraseblocks become worn out after some number of erase cycles -
31 typically 100K-1G for SLC NAND and NOR flashes, and 1K-10K for MLC
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Dubifs-authentication.rst1 .. SPDX-License-Identifier: GPL-2.0
24 binary to perform a malicious action when executed [DMC-CBC-ATTACK]. Since
28 Other full disk encryption systems like dm-crypt cover all filesystem metadata,
31 time. For dm-crypt and other filesystems that build upon the Linux block IO
32 layer, the dm-integrity or dm-verity subsystems [DM-INTEGRITY, DM-VERITY]
34 These can also be combined with dm-crypt [CRYPTSETUP2].
44 ----------------
50 addition, it deals with flash-specific wear-leveling and transparent I/O error
60 +------------+ +*******+ +-----------+ +-----+
61 | | * UBIFS * | UBI-BLOCK | | ... |
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/Documentation/devicetree/bindings/mtd/partitions/
Dpartition.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 Everything after 'partition-' will be used as the partition name to compare
26 - Rafał Miłecki <rafal@milecki.pl>
37 read-only:
39 should only be mounted read-only. This is usually used for flash
40 partitions containing early-boot firmware images or data which should
49 slc-mode:
51 on a partition attached to an MLC NAND thus making this partition
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/Documentation/networking/devlink/
Diosm.rst1 .. SPDX-License-Identifier: GPL-2.0
13 The ``iosm`` driver implements the following driver-specific parameters.
15 .. list-table:: Driver-specific parameters implemented
18 * - Name
19 - Type
20 - Mode
21 - Description
22 * - ``erase_full_flash``
23 - u8
24 - runtime
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/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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/Documentation/devicetree/bindings/spi/
Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/Documentation/ABI/testing/
Dsysfs-driver-ufs3 Contact: linux-scsi@vger.kernel.org
5 This file contains the auto-hibernate idle timer setting of a
6 UFS host controller. A value of '0' means auto-hibernate is not
11 10-bit values with a power-of-ten multiplier which allows a
82 enabled for boot. This is one of the UFS device descriptor
94 of the boot sequence. This is one of the UFS device descriptor
273 written during the pre-soldering phase of the PSA flow.
307 Description: This file shows the MIPI M-PHY version number in BCD format.
395 Description: This file shows the maximum data-in buffer size. This
406 Description: This file shows the maximum data-out buffer size. This
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/Documentation/admin-guide/
Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
28 by the boot loader; newer kernels use /dev/ram0 for
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
106 3 char Pseudo-TTY slaves
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