| /Documentation/userspace-api/gpio/ |
| D | chardev.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 Do NOT abuse userspace APIs to control hardware that has proper kernel
15 kernel driver is sure to provide a superior solution to bitbashing
18 Read Documentation/driver-api/gpio/drivers-on-gpio.rst to avoid reinventing
21 Similarly, for multi-function lines there may be other subsystems, such as
23 Documentation/driver-api/pwm.rst, Documentation/w1/index.rst etc, that
28 The API is based around two major objects, the :ref:`gpio-v2-chip` and the
29 :ref:`gpio-v2-line-request`.
31 .. _gpio-v2-chip:
33 Chip chapter
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| D | chardev_v1.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 encouraged to migrate as soon as possible, as this API will be removed
13 v1 call can be directly translated to a v2 equivalent.
15 This interface will continue to be maintained for the migration period,
16 but new features will only be added to the new API.
20 The API is based around three major objects, the :ref:`gpio-v1-chip`, the
21 :ref:`gpio-v1-line-handle`, and the :ref:`gpio-v1-line-event`.
23 Where "line event" is used in this document it refers to the request that can
26 .. _gpio-v1-chip:
28 Chip chapter
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| /Documentation/userspace-api/media/v4l/ |
| D | vidioc-dbg-g-chip-info.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_DBG_G_CHIP_INFO - Identify the chips on a TV card
29 Pointer to struct :c:type:`v4l2_dbg_chip_info`.
39 For driver debugging purposes this ioctl allows test applications to
41 applications must not use it. When you found a chip specific bug, please
42 contact the linux-media mailing list
47 ``CONFIG_VIDEO_ADV_DEBUG`` option to enable this ioctl.
49 To query the driver applications must initialize the ``match.type`` and
52 :ref:`VIDIOC_DBG_G_CHIP_INFO` with a pointer to this structure. On success
53 the driver stores information about the selected chip in the ``name``
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| D | vidioc-dbg-g-register.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_DBG_G_REGISTER - VIDIOC_DBG_S_REGISTER - Read or write hardware registers
33 Pointer to struct :c:type:`v4l2_dbg_register`.
43 For driver debugging purposes these ioctls allow test applications to
50 with the ``CONFIG_VIDEO_ADV_DEBUG`` option to enable these ioctls.
52 To write a register applications must initialize all fields of a struct
54 call ``VIDIOC_DBG_S_REGISTER`` with a pointer to this structure. The
55 ``match.type`` and ``match.addr`` or ``match.name`` fields select a chip
57 ``val`` field the value to be written into the register.
59 To read a register applications must initialize the ``match.type``,
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| /Documentation/core-api/ |
| D | genericirq.rst | 7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
13 The generic interrupt handling layer is designed to provide a complete
14 abstraction of interrupt handling for device drivers. It is able to
16 drivers use generic API functions to request, enable, disable and free
17 interrupts. The drivers do not have to know anything about interrupt
21 This documentation is provided to developers who want to implement an
29 __do_IRQ() super-handler, which is able to deal with every type of
32 Originally, Russell King identified different types of handlers to build
36 - Level type
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsl-upm-nand.txt | 1 Freescale Localbus UPM programmed to work with NAND flash
4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are used to select the chip.
12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
14 according to the number of chips.
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| D | nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
15 all NAND chips attached to this controller should be defined as
17 enforced even for simple controllers supporting only one chip.
21 pattern: "^nand-controller(@.*)?"
23 "#address-cells":
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| D | raw-nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raw NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
18 they request the ECC engine to correct {strength} bit errors per
19 {size} bytes for a particular raw NAND chip.
21 The interpretation of these parameters is implementation-defined, so
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| /Documentation/devicetree/bindings/power/reset/ |
| D | ltc2952-poweroff.txt | 3 This chip is used to externally trigger a system shut down. Once the trigger has
4 been sent, the chip's watchdog has to be reset to gracefully shut down.
9 - compatible: Must contain: "lltc,ltc2952"
10 - watchdog-gpios: phandle + gpio-specifier for the GPIO connected to the
11 chip's watchdog line
12 - kill-gpios: phandle + gpio-specifier for the GPIO connected to the
13 chip's kill line
16 - trigger-gpios: phandle + gpio-specifier for the GPIO connected to the
17 chip's trigger line. If this property is not set, the
18 trigger function is ignored and the chip is kept alive
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| D | ocelot-reset.txt | 3 The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
11 - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
12 "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
16 compatible = "mscc,ocelot-chip-reset";
|
| /Documentation/devicetree/bindings/spi/ |
| D | sprd,spi-adi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
16 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
17 framework for its hardware implementation is alike to SPI bus and its timing
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| /Documentation/hwmon/ |
| D | w83773g.rst | 12 Datasheet: https://www.nuvoton.com/resource-files/W83773G_SG_DatasheetV1_2.pdf
19 -----------
22 chip. This chip implements one local and two remote sensors.
23 The chip also features offsets for the two remote sensors which get added to
24 the input readings. The chip does all the scaling by itself and the driver
25 therefore reports true temperatures that don't need any user-space adjustments.
27 The chip is wired over I2C/SMBus and specified over a temperature
28 range of -40 to +125 degrees Celsius (for local sensor) and -40 to +127
32 The chip supports only temperature measurement. The driver exports
35 **temp[1-3]_input, temp[2-3]_fault, temp[2-3]_offset, update_interval**
|
| D | pmbus-core.rst | 9 power-management protocol with a fully defined command language that facilitates
11 protocol is implemented over the industry-standard SMBus serial interface and
12 enables programming, control, and real-time monitoring of compliant power
16 time to market for power system designers. Pioneered by leading power supply and
18 promoted by the PMBus Implementers Forum (PMBus-IF), comprising 30+ adopters
19 with the objective to provide support to, and facilitate adoption among, users.
22 commands, and manufacturers can add as many non-standard commands as they like.
23 Also, different PMBUs devices act differently if non-supported commands are
28 and supported since kernel version 2.6.39. However, it was necessary to support
29 device specific extensions in addition to the core PMBus driver, since it is
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| D | w83793.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
15 - Yuan Mu (Winbond Electronics)
16 - Rudolf Marek <r.marek@assembler.cz>
20 -----------------
26 settings. Use 'reset=1' to reset the chip when loading this module.
29 This is used to force the i2c addresses for subclients of
30 a certain chip. Typical usage is `force_subclients=0,0x2f,0x4a,0x4b`
31 to force the subclients of chip 0x2f on bus 0 to i2c addresses
36 -----------
41 This driver exports 10 voltage sensors, up to 12 fan tachometer inputs,
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| D | nsa320.rst | 8 it to act as a hardware monitor.
22 Adam Baker <linux@baker-net.org.uk>
25 -----------
27 This chip is known to be used in the Zyxel NSA320 and NSA325 NAS Units and
29 on the NSA320. In all of these devices it is connected to the same 3 GPIO
30 lines which are used to provide chip select, clock and data lines. The
31 interface behaves similarly to SPI but at much lower speeds than are normally
34 Following each chip select pulse the chip will generate a single 32 bit word
35 that contains 0x55 as a marker to indicate that data is being read correctly,
40 sysfs-Interface
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| /Documentation/w1/slaves/ |
| D | w1_ds2438.rst | 16 -----------
18 The DS2438 chip provides several functions that are desirable to carry in
20 Because the ability of temperature, current and voltage measurement, the chip
28 -----
36 When writing to sysfs file bits 2-7 are ignored, so it's safe to write ASCII.
40 -------
41 This file provides full 8 bytes of the chip Page 0 (00h).
45 to userspace, otherwise an I/O error is returned.
48 -------
49 This file provides full 8 bytes of the chip Page 1 (01h).
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| /Documentation/scsi/ |
| D | 53c700.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 This driver supports the 53c700 and 53c700-66 chips. It also supports
12 does sync (-66 and 710 only), disconnects and tag command queueing.
14 Since the 53c700 must be interfaced to a bus, you need to wrapper the
18 The comments in the 53c700.[ch] files tell you which parts you need to
19 fill in to get the driver working.
33 Using the Chip Core Driver
36 In order to plumb the 53c700 chip core driver into a working SCSI
37 driver, you need to know three things about the way the chip is wired
44 Optionally, you may also need to know other things, like how to read
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| /Documentation/admin-guide/gpio/ |
| D | gpio-mockup.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
8 This module has been obsoleted by the more flexible gpio-sim.rst.
10 encouraged to migrate as soon as possible.
11 This module will continue to be maintained but no new features will be
14 The GPIO Testing Driver (gpio-mockup) provides a way to create simulated GPIO
20 --------------------------------------------
22 When loading the gpio-mockup driver a number of parameters can be passed to the
28 pairs. Each pair defines the base GPIO number (non-negative integer)
29 and the first number after the last of this chip. If the base GPIO
30 is -1, the gpiolib will assign it automatically. while the following
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| /Documentation/misc-devices/ |
| D | bh1770glc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - ROHM BH1770GLC
10 - OSRAM SFH7770
19 -----------
23 but ALS side results are used to estimate reliability of the proximity sensor.
25 ALS produces 16 bit lux values. The chip contains interrupt logic to produce
28 Proximity part contains IR-led driver up to 3 IR leds. The chip measures
30 8 bit. Driver supports only one channel. Driver uses ALS results to estimate
34 Driver uses threshold interrupts to avoid need for polling the values.
35 Proximity low interrupt doesn't exists in the chip. This is simulated
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
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| /Documentation/arch/powerpc/ |
| D | vcpudispatch_stats.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 static mapping of the LPAR processors (vcpus) to physical processor
9 chips (representing the "home" node) and tries to always dispatch vcpus
10 on their associated physical processor chip. However, under certain
11 scenarios, vcpus may be dispatched on a different processor chip (away
14 /proc/powerpc/vcpudispatch_stats can be used to obtain statistics
15 related to the vcpu dispatch behavior. Writing '1' to this file enables
18 as not to miss any entries. This processing frequency can be changed
22 /proc/powerpc/vcpudispatch_stats. Each line in the output corresponds to
25 The first number corresponds to:
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|
| /Documentation/sound/kernel-api/ |
| D | writing-an-alsa-driver.rst | 10 This document describes how to write an `ALSA (Advanced Linux Sound
11 Architecture) <http://www.alsa-project.org/>`__ driver. The document
19 low-level driver implementation details. It only describes the standard
20 way to write a PCI sound driver on ALSA.
26 -------
56 --------------
60 sub-directories contain different modules and are dependent upon the
74 This directory and its sub-directories are for the ALSA sequencer. This
76 as snd-seq-midi, snd-seq-virmidi, etc. They are compiled only when
85 -----------------
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | melfas_mip4.txt | 4 - compatible: must be "melfas,mip4_ts"
5 - reg: I2C slave address of the chip (0x48 or 0x34)
6 - interrupts: interrupt to which the chip is connected
9 - ce-gpios: GPIO connected to the CE (chip enable) pin of the chip
16 interrupt-parent = <&gpio>;
18 ce-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
|
| /Documentation/driver-api/ |
| D | mtdnand.rst | 10 The generic NAND driver supports almost all NAND and AG-AND based chips
11 and connects them to the Memory Technology Devices (MTD) subsystem of
14 This documentation is provided for developers who want to implement
31 --------------------------
37 - [MTD Interface]
39 These functions provide the interface to the MTD kernel API. They are
43 - [NAND Interface]
45 These functions are exported and provide the interface to the NAND
48 - [GENERIC]
53 - [DEFAULT]
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-max3191x.txt | 4 - compatible: Must be one of:
11 - reg: Chip select number.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells: Should be two. For consumer use see gpio.txt.
16 - #daisy-chained-devices:
17 Number of chips in the daisy-chain (default is 1).
18 - maxim,modesel-gpios: GPIO pins to configure modesel of each chip.
19 The number of GPIOs must equal "#daisy-chained-devices"
20 (if each chip is driven by a separate pin) or 1
21 (if all chips are wired to the same pin).
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|