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/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/Documentation/block/
Dwriteback_cache_control.rst2 Explicit volatile write back cache control
6 ------------
9 write back caches. That means the devices signal I/O completion to the
10 operating system before data actually has hit the non-volatile storage. This
12 system needs to force data out to the non-volatile storage when it performs
17 a forced cache flush, and the Force Unit Access (FUA) flag for requests.
20 Explicit cache flushes
21 ----------------------
24 the filesystem and will make sure the volatile cache of the storage device
25 has been flushed before the actual I/O operation is started. This explicitly
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/Documentation/filesystems/caching/
Dnetfs-api.rst1 .. SPDX-License-Identifier: GPL-2.0
10 (1) A cache is logically organised into volumes and data storage objects
18 (4) Cookies have coherency data that allows a cache to determine if the
21 (5) I/O is done asynchronously where possible.
34 (6) Data I/O API
55 maximum size of a filename component (allowing the cache backend one char for
62 their parent volume. The cache backend is responsible for rendering the binary
71 This causes fscache to send the cache backend off to look up/create resources
83 extra pins into the cache to stop cache withdrawal from tearing down the
87 The filesystem is expected to use netfslib to access the cache, but that's not
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/Documentation/networking/
Dpktgen.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
31 overload type of benchmarking, as this could hurt the normal use-case.
35 # ethtool -G ethX tx 1024
39 than the CPU's L1/L2 cache, 2) because it allows more queueing in the
44 ring-buffers for various performance reasons, and packets stalling
49 and the cleanup interval is affected by the ethtool --coalesce setting
50 of parameter "rx-usecs".
54 # ethtool -C ethX rx-usecs 30
72 * add_device DEVICE@NAME -- adds a single device
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Dipvs-sysctl.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IPvs-sysctl
10 am_droprate - INTEGER
13 It sets the always mode drop rate, which is used in the mode 3
16 amemthresh - INTEGER
19 It sets the available memory threshold (in pages), which is
25 backup_only - BOOLEAN
26 - 0 - disabled (default)
27 - not 0 - enabled
32 conn_reuse_mode - INTEGER
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/Documentation/devicetree/bindings/cache/
Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
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/Documentation/admin-guide/device-mapper/
Dvdo.rst1 .. SPDX-License-Identifier: GPL-2.0-only
3 dm-vdo
6 The dm-vdo (virtual data optimizer) device mapper target provides
7 block-level deduplication, compression, and thin provisioning. As a device
20 https://github.com/dm-vdo/vdo/
25 enter or come up in read-only mode. Because read-only mode is indicative of
26 data-loss, a positive action must be taken to bring vdo out of read-only
28 prepare a read-only vdo to exit read-only mode. After running this tool,
34 inspect a vdo target's on-disk metadata. Fortunately, these tools are
35 rarely needed except by dm-vdo developers.
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Dvdo-design.rst1 .. SPDX-License-Identifier: GPL-2.0-only
4 Design of dm-vdo
7 The dm-vdo (virtual data optimizer) target provides inline deduplication,
8 compression, zero-block elimination, and thin provisioning. A dm-vdo target
12 production environments ever since. It was made open-source in 2017 after
14 dm-vdo. For usage, see vdo.rst in the same directory as this file.
18 deduplication rates of 254:1, i.e. up to 254 copies of a given 4K block can
25 The design of dm-vdo is based on the idea that deduplication is a two-part
27 storing multiple copies of those duplicates. Therefore, dm-vdo has two main
34 -------------------
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/Documentation/mm/
Dhmm.rst5 Provide infrastructure and helpers to integrate non-conventional memory (device
10 HMM also provides optional helpers for SVM (Share Virtual Memory), i.e.,
17 This document is divided as follows: in the first section I expose the problems
18 related to using device specific memory allocators. In the second section, I
21 CPU page-table mirroring works and the purpose of HMM in this context. The
35 regular file backed memory). From here on I will refer to this aspect as split
36 address space. I use shared address space to refer to the opposite situation:
37 i.e., one in which any application memory region can be used by a device
50 For flat data sets (array, grid, image, ...) this isn't too hard to achieve but
51 for complex data sets (list, tree, ...) it's hard to get right. Duplicating a
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Dslub.rst18 slabs that have data in them. See "slabinfo -h" for more options when
22 gcc -o slabinfo tools/mm/slabinfo.c
30 -------------------------------------------
35 slab_debug=<Debug-Options>
38 slab_debug=<Debug-Options>,<slab name1>,<slab name2>,...
55 A Enable failslab filter mark for the cache
58 - Switch all debugging off (useful if the kernel is
65 Trying to find an issue in the dentry cache? Try::
69 to only enable debugging on the dentry cache. You may use an asterisk at the
71 example, here's how you can poison the dentry cache as well as all kmalloc
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/Documentation/admin-guide/
Dbcache.rst2 A block layer cache (bcache)
6 nice if you could use them as cache... Hence bcache.
11 This is the git repository of bcache-tools:
12 https://git.kernel.org/pub/scm/linux/kernel/git/colyli/bcache-tools.git/
17 It's designed around the performance characteristics of SSDs - it only allocates
25 great lengths to protect your data - it reliably handles unclean shutdown. (It
29 Writeback caching can use most of the cache for buffering writes - writing
36 average is above the cutoff it will skip all IO from that task - instead of
38 thus entirely bypass the cache.
41 from disk or invalidating cache entries. For unrecoverable errors (meta data
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Dmd.rst5 ---------------------------------
49 -1 linear mode
58 (raid-0 and raid-1 only)
78 --------------------------------------
87 that all auto-detected arrays are assembled as partitionable.
90 -------------------------------------------
102 mdadm --assemble --force ....
112 md-mod.start_dirty_degraded=1
116 ------------------
119 Currently, it supports superblock formats ``0.90.0`` and the ``md-1`` format
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Dext4.rst1 .. SPDX-License-Identifier: GPL-2.0
9 (64 bit) in keeping with increasing disk capacities and state-of-the-art
12 Mailing list: linux-ext4@vger.kernel.org
23 - The latest version of e2fsprogs can be found at:
35 - Create a new filesystem using the ext4 filesystem type:
37 # mke2fs -t ext4 /dev/hda1
41 # tune2fs -O extents /dev/hda1
46 # tune2fs -I 256 /dev/hda1
48 - Mounting:
50 # mount -t ext4 /dev/hda1 /wherever
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/Documentation/admin-guide/blockdev/
Dfloppy.rst19 Example: If your kernel is called linux-2.6.9, type the following line
22 linux-2.6.9 floppy=thinkpad
25 of linux-2.6.9::
31 linux-2.6.9 floppy=daring floppy=two_fdc
62 Sets the bit mask to allow only units 0 and 1. (default)
96 and is thus harder to find, whereas non-dma buffers may be
97 allocated in virtual memory. However, I advise against this if
100 If you use nodma mode, I suggest you also set the FIFO
104 If you have a FIFO-able FDC, the floppy driver automatically
105 falls back on non DMA mode if no DMA-able memory can be found.
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/Documentation/devicetree/bindings/opp/
Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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/Documentation/filesystems/
Dgfs2-glocks.rst1 .. SPDX-License-Identifier: GPL-2.0
13 2. A non-blocking bit lock, GLF_LOCK, which is used to prevent other
39 shared lock mode, SH. In GFS2 the DF mode is used exclusively for direct I/O
41 with cache management. The following rules apply for the cache:
44 Glock mode Cache Metadata Cache data Dirty Data Dirty Metadata
62 go_xmote_bh Called after remote state change (e.g. to refill cache)
63 go_inval Called if remote state change requires invalidating the cache
118 5. Transaction glock (via gfs2_trans_begin) for non-read operations
126 is on a per-inode basis. Locking of rgrps is on a per rgrp basis.
130 ----------------
[all …]
Dvfat.rst8 To use the vfat filesystem, use the filesystem type 'vfat'. i.e.::
10 mount -t vfat /dev/fd0 /mnt
42 **-20**: If current process is in group of file's group ID,
45 **-2**: Other users can change timestamp.
48 writable, utime(2) is also allowed. i.e. ~dmask & 022.
57 Sets the codepage number for converting to shortname
69 There is also an option of doing UTF-8 translations
76 UTF-8 is the filesystem safe version of Unicode that
79 If 'uni_xlate' gets set, UTF-8 gets disabled.
151 used by FAT to UTC. I.e. <minutes> minutes will be subtracted
[all …]
Dcoda.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Coda Kernel-Venus Interface
10 Coda -- this document describes the client kernel-Venus interface.
20 To run Coda you need to get a user level cache manager for the client,
35 level filesystem code needed for the operation of the Coda file sys-
98 A key component in the Coda Distributed File System is the cache
105 client cache and makes remote procedure calls to Coda file servers and
124 leads to an almost natural environment for implementing a kernel-level
148 filesystem (VFS) layer, which is named I/O Manager in NT and IFS
153 pre-processing, the VFS starts invoking exported routines in the FS
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/Documentation/admin-guide/mm/
Dnuma_memory_policy.rst10 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
16 (``Documentation/admin-guide/cgroup-v1/cpusets.rst``)
19 programming interface that a NUMA-aware application can take advantage of. When
28 ------------------------
41 not to overload the initial boot node with boot-time
45 this is an optional, per-task policy. When defined for a
61 In a multi-threaded task, task policies apply only to the thread
98 mapping-- i.e., at Copy-On-Write.
101 virtual address space--a.k.a. threads--independent of when
106 are NOT inheritable across exec(). Thus, only NUMA-aware
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/Documentation/arch/x86/
Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
24 to cache translations for virtual addresses. The IOMMU driver uses the
25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
62 to perform I/O operations via use of PASID.
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
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/Documentation/ABI/testing/
Dsysfs-devices-system-cpu2 Date: pre-git history
3 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
18 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
37 See Documentation/admin-guide/cputopology.rst for more information.
43 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
58 Contact: Linux memory management mailing list <linux-mm@kvack.org>
67 /sys/devices/system/cpu/cpu42/node2 -> ../../node/node2
77 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
89 core_siblings_list: human-readable list of the logical CPU
99 thread_siblings_list: human-readable list of cpuX's hardware
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/Documentation/admin-guide/cgroup-v1/
Dmemory.rst18 we call it "memory cgroup". When you see git-log and source code, you'll
30 Memory-hungry applications can be isolated and limited to a smaller
42 Current Status: linux-2.6.34-mmotm(development version of 2010/April)
46 - accounting anonymous pages, file caches, swap caches usage and limiting them.
47 - pages are linked to per-memcg LRU exclusively, and there is no global LRU.
48 - optionally, memory+swap usage can be accounted and limited.
49 - hierarchical accounting
50 - soft limit
51 - moving (recharging) account at moving a task is selectable.
52 - usage threshold notifier
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/Documentation/driver-api/
Ddevice-io.rst10 Bus-Independent Device Accesses
27 ----------------------------
49 --------------------
52 memory-mapped registers on the device. Linux provides interfaces to read
53 and write 8-bit, 16-bit, 32-bit and 64-bit quantities. Due to a
69 compiler is not permitted to reorder the I/O sequence. When the ordering
82 from config space, which is guaranteed to soft-fail if the card doesn't
94 reg = ha->iobase;
96 WRT_REG_WORD(&reg->ictrl, 0);
102 RD_REG_WORD(&reg->ictrl);
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/Documentation/networking/device_drivers/ethernet/amazon/
Dena.rst1 .. SPDX-License-Identifier: GPL-2.0
17 The driver supports a range of ENA devices, is link-speed independent
18 (i.e., the same driver is used for 10GbE, 25GbE, 40GbE, etc), and has
21 Some ENA devices support SR-IOV. This driver is used for both the
22 SR-IOV Physical Function (PF) and Virtual Function (VF) devices.
26 is advertised by the device via the Admin Queue), a dedicated MSI-X
31 checksum offload. Receive-side scaling (RSS) is supported for multi-core
39 Some of the ENA devices support a working mode called Low-latency
54 ena_regs_defs.h Definition of ENA PCI memory-mapped (MMIO) registers.
66 - PCIe Configuration Space
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/Documentation/core-api/
Ddma-api-howto.rst10 with example pseudo-code. For a concise description of the API, see
11 Documentation/core-api/dma-api.rst.
30 I/O devices use a third kind of address: a "bus address". If a device has
39 supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
40 so devices only need to use 32-bit DMA addresses.
49 +-------+ +------+ +------+
52 C +-------+ --------> B +------+ ----------> +------+ A
54 +-----+ | | | | bridge | | +--------+
55 | | | | +------+ | | | |
58 +-----+ +-------+ +------+ +------+ +--------+
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