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| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
24 ratified states, with the exception of the I, Zicntr & Zihpm extensions.
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | pamu.txt | 5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
15 I/O space utilized by the controller. The size should
16 be set to the total size of the register space of all
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
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| /Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
78 address space is available via vma->vm_mm. Also, one may
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| D | dma-api.rst | 8 of the API (and actual examples), see Documentation/core-api/dma-api-howto.rst.
10 This API is split into two pieces. Part I describes the basic API.
11 Part II describes extensions for supporting non-consistent memory
13 non-consistent platforms (this is usually only legacy platforms) you
14 should only use the API described in part I.
16 Part I - dma_API
17 ----------------
19 To get the dma_API, you must #include <linux/dma-mapping.h>. This
27 Part Ia - Using large DMA-coherent buffers
28 ------------------------------------------
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| /Documentation/filesystems/caching/ |
| D | backend-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Cache Backend API
7 The FS-Cache system provides an API by which actual caches can be supplied to
8 FS-Cache for it to then serve out to network filesystems and other interested
11 #include <linux/fscache-cache.h>.
17 Interaction with the API is handled on three levels: cache, volume and data
23 Cache cookie struct fscache_cache
28 Cookies are used to provide some filesystem data to the cache, manage state and
29 pin the cache during access in addition to acting as reference points for the
34 The cache backend and the network filesystem can both ask for cache cookies -
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| D | netfs-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 (1) A cache is logically organised into volumes and data storage objects
18 (4) Cookies have coherency data that allows a cache to determine if the
21 (5) I/O is done asynchronously where possible.
34 (6) Data I/O API
55 maximum size of a filename component (allowing the cache backend one char for
62 their parent volume. The cache backend is responsible for rendering the binary
71 This causes fscache to send the cache backend off to look up/create resources
83 extra pins into the cache to stop cache withdrawal from tearing down the
87 The filesystem is expected to use netfslib to access the cache, but that's not
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| D | cachefiles.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Cache on Already Mounted Filesystem
15 (*) Starting the cache.
19 (*) Cache culling.
21 (*) Cache structure.
31 (*) On-demand Read.
37 CacheFiles is a caching backend that's meant to use as a cache a directory on
40 CacheFiles uses a userspace daemon to do some of the cache management - such as
44 The filesystem and data integrity of the cache are only as good as those of the
49 CacheFiles creates a misc character device - "/dev/cachefiles" - that is used
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| D | fscache.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 This facility is a general purpose cache for network filesystems, though it
13 FS-Cache mediates between cache backends (such as CacheFiles) and network
16 +---------+
17 | | +--------------+
18 | NFS |--+ | |
19 | | | +-->| CacheFS |
20 +---------+ | +----------+ | | /dev/hda5 |
21 | | | | +--------------+
22 +---------+ +-------------->| | |
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| /Documentation/filesystems/ |
| D | fuse-io.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Fuse I/O Modes
7 Fuse supports the following I/O modes:
9 - direct-io
10 - cached
11 + write-through
12 + writeback-cache
14 The direct-io mode can be selected with the FOPEN_DIRECT_IO flag in the
17 In direct-io mode the page cache is completely bypassed for reads and writes.
18 No read-ahead takes place. Shared mmap is disabled by default. To allow shared
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| D | squashfs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Squashfs is a compressed read-only filesystem for Linux.
12 maximum of 1Mbytes (default block size 128K).
14 Squashfs is intended for general read-only filesystem use, for archival
15 use (i.e. in cases where a .tar.gz file may be used), and in constrained
19 Mailing list: squashfs-devel@lists.sourceforge.net
23 ----------------------
30 Max filesystem size 2^64 256 MiB
31 Max file size ~ 2 TiB 16 MiB
35 Max block size 1 MiB 4 KiB
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| D | netfs_library.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - Overview.
10 - Per-inode context.
11 - Inode context helper functions.
12 - Buffered read helpers.
13 - Read helper functions.
14 - Read helper structures.
15 - Read helper operations.
16 - Read helper procedure.
17 - Read helper cache API.
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| /Documentation/admin-guide/device-mapper/ |
| D | vdo.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
3 dm-vdo
6 The dm-vdo (virtual data optimizer) device mapper target provides
7 block-level deduplication, compression, and thin provisioning. As a device
20 https://github.com/dm-vdo/vdo/
25 enter or come up in read-only mode. Because read-only mode is indicative of
26 data-loss, a positive action must be taken to bring vdo out of read-only
28 prepare a read-only vdo to exit read-only mode. After running this tool,
34 inspect a vdo target's on-disk metadata. Fortunately, these tools are
35 rarely needed except by dm-vdo developers.
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| D | dm-clone.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
4 dm-clone
10 dm-clone is a device mapper target which produces a one-to-one copy of an
11 existing, read-only source device into a writable destination device: It
15 The main use case of dm-clone is to clone a potentially remote, high-latency,
16 read-only, archival-type block device into a writable, fast, primary-type device
17 for fast, low-latency I/O. The cloned device is visible/mountable immediately
19 background, in parallel with user I/O.
21 For example, one could restore an application backup from a read-only copy,
26 When the cloning completes, the dm-clone table can be removed altogether and be
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| D | writecache.rst | 6 doesn't cache reads because reads are supposed to be cached in page cache
14 1. type of the cache device - "p" or "s"
15 - p - persistent memory
16 - s - SSD
18 3. the cache device
19 4. block size (4096 is recommended; the maximum block size is the page
20 size)
25 offset from the start of cache device in 512-byte sectors
45 applicable only to persistent memory - use the FUA flag
49 applicable only to persistent memory - don't use the FUA
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| D | cache.rst | 2 Cache title
8 dm-cache is a device mapper target written by Joe Thornber, Heinz
15 This device-mapper solution allows us to insert this caching at
17 a thin-provisioning pool. Caching solutions that are integrated more
20 The target reuses the metadata library used in the thin-provisioning
23 The decision as to what data to migrate and when is left to a plug-in
40 may be out of date or kept in sync with the copy on the cache device
46 Sub-devices
47 -----------
52 1. An origin device - the big, slow one.
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| /Documentation/admin-guide/ |
| D | bcache.rst | 2 A block layer cache (bcache)
6 nice if you could use them as cache... Hence bcache.
11 This is the git repository of bcache-tools:
12 https://git.kernel.org/pub/scm/linux/kernel/git/colyli/bcache-tools.git/
17 It's designed around the performance characteristics of SSDs - it only allocates
19 extents (which can be anywhere from a single sector to the bucket size). It's
25 great lengths to protect your data - it reliably handles unclean shutdown. (It
29 Writeback caching can use most of the cache for buffering writes - writing
36 average is above the cutoff it will skip all IO from that task - instead of
38 thus entirely bypass the cache.
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-dt.txt | 11 - None
14 - operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for
15 details. OPPs *must* be supplied either via DT, i.e. this property, or
17 - clock-latency: Specify the possible maximum transition latency for clock,
19 - voltage-tolerance: Specify the CPU voltage tolerance in percentage.
20 - #cooling-cells:
22 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-a9";
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| /Documentation/devicetree/bindings/cache/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
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| /Documentation/devicetree/bindings/thermal/ |
| D | thermal-cooling-devices.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-cooling-devices.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Amit Kucheria <amitk@kernel.org>
20 - thermal-sensor: device that measures temperature, has SoC-specific bindings
21 - cooling-device: device used to dissipate heat either passively or actively
22 - thermal-zones: a container of the following node types used to describe all
28 - Passive cooling: by means of regulating device performance. A typical
31 - Active cooling: by means of activating devices in order to remove the
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | sata-uctl.txt | 3 UCTL is the bridge unit between the I/O interconnect (an internal bus)
5 - provides interfaces for the applications to access the UAHC AHCI
6 registers on the CN71XX I/O space.
7 - provides a bridge for UAHC to fetch AHCI command table entries and data
8 buffers from Level 2 Cache.
9 - posts interrupts to the CIU.
10 - contains registers that:
11 - control the behavior of the UAHC
12 - control the clock/reset generation to UAHC
13 - control endian swapping for all UAHC registers and DMA accesses
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| /Documentation/admin-guide/mm/ |
| D | zswap.rst | 8 Zswap is a lightweight compressed cache for swap pages. It takes pages that are
10 dynamically allocated RAM-based memory pool. zswap basically trades CPU cycles
11 for potentially reduced swap I/O. This trade-off can also result in a
12 significant performance improvement if reads from the compressed cache are
19 * Overcommitted guests that share a common I/O resource can
20 dramatically reduce their swap I/O pressure, avoiding heavy handed I/O
22 impact to the guest workload and guests sharing the I/O subsystem
24 drastically reducing life-shortening writes.
26 Zswap evicts pages from compressed cache on an LRU basis to the backing swap
27 device when the compressed pool reaches its size limit. This requirement had
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| D | numaperf.rst | 10 as CPU cache coherence, but may have different performance. For example,
21 +------------------+ +------------------+
22 | Compute Node 0 +-----+ Compute Node 1 |
24 +--------+---------+ +--------+---------+
26 +--------+---------+ +--------+---------+
28 +------------------+ +--------+---------+
31 CPUs or separate memory I/O devices that can initiate memory requests.
36 performance when accessing a given memory target. Each initiator-target
48 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
49 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
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| /Documentation/driver-api/usb/ |
| D | dma.rst | 5 over how DMA may be used to perform I/O operations. The APIs are detailed
12 though they still must provide DMA-ready buffers (see
13 Documentation/core-api/dma-api-howto.rst). That's how they've worked through
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
19 manage dma mappings for existing dma-ready buffers (see below).
21 - URBs have an additional "transfer_dma" field, as well as a transfer_flags
25 - "usbcore" will map this DMA address, if a DMA-aware driver didn't do
29 - There's a new "generic DMA API", parts of which are usable by USB device
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| /Documentation/ABI/testing/ |
| D | sysfs-kernel-slab | 5 Christoph Lameter <cl@linux-foundation.org>
8 internal state of the SLUB allocator for each cache. Certain
9 files may be modified to change the behavior of the cache (and
10 any cache it aliases, if any).
13 What: /sys/kernel/slab/<cache>/aliases
17 Christoph Lameter <cl@linux-foundation.org>
19 The aliases file is read-only and specifies how many caches
20 have merged into this cache.
22 What: /sys/kernel/slab/<cache>/align
26 Christoph Lameter <cl@linux-foundation.org>
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