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/drivers/spi/
Dspi-qup.c163 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
165 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
179 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
181 return controller->n_words * controller->w_size; in spi_qup_len()
184 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) in spi_qup_is_valid_state() argument
186 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
191 static int spi_qup_vote_bw(struct spi_qup *controller, u32 speed_hz) in spi_qup_vote_bw() argument
196 if (controller->bw_speed_hz == speed_hz) in spi_qup_vote_bw()
200 ret = icc_set_bw(controller->icc_path, 0, needed_peak_bw); in spi_qup_vote_bw()
204 controller->bw_speed_hz = speed_hz; in spi_qup_vote_bw()
[all …]
Dspi-fsl-lpspi.c195 static bool fsl_lpspi_can_dma(struct spi_controller *controller, in fsl_lpspi_can_dma() argument
201 if (!controller->dma_rx) in fsl_lpspi_can_dma()
218 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) in lpspi_prepare_xfer_hardware() argument
221 spi_controller_get_devdata(controller); in lpspi_prepare_xfer_hardware()
233 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) in lpspi_unprepare_xfer_hardware() argument
236 spi_controller_get_devdata(controller); in lpspi_unprepare_xfer_hardware()
361 static int fsl_lpspi_dma_configure(struct spi_controller *controller) in fsl_lpspi_dma_configure() argument
367 spi_controller_get_devdata(controller); in fsl_lpspi_dma_configure()
387 ret = dmaengine_slave_config(controller->dma_tx, &tx); in fsl_lpspi_dma_configure()
398 ret = dmaengine_slave_config(controller->dma_rx, &rx); in fsl_lpspi_dma_configure()
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Dspi-pxa2xx-dma.c28 struct spi_message *msg = drv_data->controller->cur_msg; in pxa2xx_spi_dma_transfer_complete()
57 spi_finalize_current_transfer(drv_data->controller); in pxa2xx_spi_dma_transfer_complete()
98 chan = drv_data->controller->dma_tx; in pxa2xx_spi_dma_prepare_one()
105 chan = drv_data->controller->dma_rx; in pxa2xx_spi_dma_prepare_one()
126 dmaengine_terminate_async(drv_data->controller->dma_rx); in pxa2xx_spi_dma_transfer()
127 dmaengine_terminate_async(drv_data->controller->dma_tx); in pxa2xx_spi_dma_transfer()
165 dmaengine_terminate_async(drv_data->controller->dma_tx); in pxa2xx_spi_dma_prepare()
172 dma_async_issue_pending(drv_data->controller->dma_rx); in pxa2xx_spi_dma_start()
173 dma_async_issue_pending(drv_data->controller->dma_tx); in pxa2xx_spi_dma_start()
181 dmaengine_terminate_sync(drv_data->controller->dma_rx); in pxa2xx_spi_dma_stop()
[all …]
Dspi-loongson-core.c34 struct loongson_spi *loongson_spi = spi_controller_get_devdata(spi->controller); in loongson_spi_set_cs()
93 loongson_spi = spi_controller_get_devdata(spi->controller); in loongson_spi_setup()
97 if (spi_get_chipselect(spi, 0) >= spi->controller->num_chipselect) in loongson_spi_setup()
110 struct loongson_spi *loongson_spi = spi_controller_get_devdata(spi->controller); in loongson_spi_write_read_8bit()
161 struct loongson_spi *loongson_spi = spi_controller_get_devdata(spi->controller); in loongson_spi_transfer_one()
197 struct spi_controller *controller; in loongson_spi_init_controller() local
201 controller = devm_spi_alloc_host(dev, sizeof(struct loongson_spi)); in loongson_spi_init_controller()
202 if (controller == NULL) in loongson_spi_init_controller()
205 controller->mode_bits = SPI_MODE_X_MASK | SPI_CS_HIGH; in loongson_spi_init_controller()
206 controller->setup = loongson_spi_setup; in loongson_spi_init_controller()
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Dspi-ljca.c71 struct spi_controller *controller; member
193 static int ljca_spi_transfer_one(struct spi_controller *controller, in ljca_spi_transfer_one() argument
197 u8 div = DIV_ROUND_UP(controller->max_speed_hz, xfer->speed_hz) / 2 - 1; in ljca_spi_transfer_one()
198 struct ljca_spi_dev *ljca_spi = spi_controller_get_devdata(controller); in ljca_spi_transfer_one()
222 struct spi_controller *controller; in ljca_spi_probe() local
226 controller = devm_spi_alloc_host(&auxdev->dev, sizeof(*ljca_spi)); in ljca_spi_probe()
227 if (!controller) in ljca_spi_probe()
230 ljca_spi = spi_controller_get_devdata(controller); in ljca_spi_probe()
233 ljca_spi->controller = controller; in ljca_spi_probe()
235 controller->bus_num = -1; in ljca_spi_probe()
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DKconfig12 controller and a chipselect. Most SPI slaves don't support
16 eeprom and flash memory, codecs and various other controller
33 sysfs, and debugfs support in SPI controller and protocol drivers.
44 If your system has an master-capable SPI controller (which
46 controller and the protocol drivers for the SPI slave chips
67 Flash Interface found on Airoha ARM SoCs. This controller
68 is implemented as a SPI-MEM controller.
89 Altera SPI master controller. The SPI master is connected
93 tristate "Amlogic A1 SPIFC controller"
97 controller) available in Amlogic A1 (A113L SoC).
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Dspi-pxa2xx.c363 spi_controller_get_devdata(spi->controller); in lpss_ssp_select_cs()
386 (drv_data->controller->max_speed_hz / 2)); in lpss_ssp_select_cs()
393 spi_controller_get_devdata(spi->controller); in lpss_ssp_cs_control()
429 spi_controller_get_devdata(spi->controller); in cs_assert()
443 spi_controller_get_devdata(spi->controller); in cs_deassert()
586 if (drv_data->controller->cur_msg) { in reset_sccr1()
587 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); in reset_sccr1()
627 drv_data->controller->cur_msg->status = err; in int_error_stop()
628 spi_finalize_current_transfer(drv_data->controller); in int_error_stop()
635 spi_finalize_current_transfer(drv_data->controller); in int_transfer_complete()
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Dspi-imx.c93 struct spi_controller *controller; member
233 static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi, in spi_imx_can_dma() argument
236 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); in spi_imx_can_dma()
238 if (!use_dma || controller->fallback) in spi_imx_can_dma()
241 if (!controller->dma_rx) in spi_imx_can_dma()
524 return spi->controller->unused_native_cs; in mx51_ecspi_channel()
1199 static int spi_imx_dma_configure(struct spi_controller *controller) in spi_imx_dma_configure() argument
1204 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); in spi_imx_dma_configure()
1224 ret = dmaengine_slave_config(controller->dma_tx, &tx); in spi_imx_dma_configure()
1234 ret = dmaengine_slave_config(controller->dma_rx, &rx); in spi_imx_dma_configure()
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/drivers/usb/musb/
Dmusb_cppi41.c37 struct dma_controller controller; member
61 if (!is_host_active(cppi41_channel->controller->controller.musb)) in save_rx_toggle()
187 struct cppi41_dma_controller *controller; in cppi41_recheck_tx_req() local
193 controller = container_of(timer, struct cppi41_dma_controller, in cppi41_recheck_tx_req()
195 musb = controller->controller.musb; in cppi41_recheck_tx_req()
198 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list, in cppi41_recheck_tx_req()
210 if (!list_empty(&controller->early_tx_list) && in cppi41_recheck_tx_req()
211 !hrtimer_is_queued(&controller->early_tx)) { in cppi41_recheck_tx_req()
213 hrtimer_forward_now(&controller->early_tx, 20 * NSEC_PER_USEC); in cppi41_recheck_tx_req()
226 struct cppi41_dma_controller *controller; in cppi41_dma_callback() local
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Dmusbhsdma.c55 struct musb_dma_controller *controller; member
65 struct dma_controller controller; member
76 static void dma_controller_stop(struct musb_dma_controller *controller) in dma_controller_stop() argument
78 struct musb *musb = controller->private_data; in dma_controller_stop()
82 if (controller->used_channels != 0) { in dma_controller_stop()
83 dev_err(musb->controller, in dma_controller_stop()
87 if (controller->used_channels & (1 << bit)) { in dma_controller_stop()
88 channel = &controller->channel[bit].channel; in dma_controller_stop()
91 if (!controller->used_channels) in dma_controller_stop()
101 struct musb_dma_controller *controller = container_of(c, in dma_channel_allocate() local
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Dux500_dma.c32 struct ux500_dma_controller *controller; member
43 struct dma_controller controller; member
59 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", in ux500_dma_callback()
82 struct musb *musb = ux500_channel->controller->private_data; in ux500_configure_channel()
84 ux500_channel->controller->phy_base); in ux500_configure_channel()
86 dev_dbg(musb->controller, in ux500_configure_channel()
131 struct ux500_dma_controller *controller = container_of(c, in ux500_dma_channel_allocate() local
132 struct ux500_dma_controller, controller); in ux500_dma_channel_allocate()
134 struct musb *musb = controller->private_data; in ux500_dma_channel_allocate()
147 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) : in ux500_dma_channel_allocate()
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/drivers/peci/
Dcore.c21 struct peci_controller *controller = to_peci_controller(dev); in peci_controller_dev_release() local
23 mutex_destroy(&controller->bus_lock); in peci_controller_dev_release()
24 ida_free(&peci_controller_ida, controller->id); in peci_controller_dev_release()
25 kfree(controller); in peci_controller_dev_release()
32 int peci_controller_scan_devices(struct peci_controller *controller) in peci_controller_scan_devices() argument
38 ret = peci_device_create(controller, addr); in peci_controller_scan_devices()
49 struct peci_controller *controller; in peci_controller_alloc() local
55 controller = kzalloc(sizeof(*controller), GFP_KERNEL); in peci_controller_alloc()
56 if (!controller) in peci_controller_alloc()
62 controller->id = ret; in peci_controller_alloc()
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/drivers/gpio/
Dgpio-zevio.c80 struct zevio_gpio *controller = gpiochip_get_data(chip); in zevio_gpio_get() local
83 spin_lock(&controller->lock); in zevio_gpio_get()
84 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); in zevio_gpio_get()
86 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); in zevio_gpio_get()
88 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_get()
89 spin_unlock(&controller->lock); in zevio_gpio_get()
96 struct zevio_gpio *controller = gpiochip_get_data(chip); in zevio_gpio_set() local
99 spin_lock(&controller->lock); in zevio_gpio_set()
100 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_set()
106 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); in zevio_gpio_set()
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/drivers/net/ethernet/mellanox/mlx5/core/sf/diag/
Dsf_tracepoint.h17 u32 controller,
20 TP_ARGS(dev, port_index, controller, hw_fn_id, sfnum),
23 __field(u32, controller)
29 __entry->controller = controller;
34 __get_str(devname), __entry->port_index, __entry->controller,
41 u32 controller,
43 TP_ARGS(dev, port_index, controller, hw_fn_id),
46 __field(u32, controller)
51 __entry->controller = controller;
55 __get_str(devname), __entry->port_index, __entry->controller,
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/drivers/pci/hotplug/
Dpciehp.h91 struct controller { struct
164 void pciehp_request(struct controller *ctrl, int action);
165 void pciehp_handle_button_press(struct controller *ctrl);
166 void pciehp_handle_disable_request(struct controller *ctrl);
167 void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events);
168 int pciehp_configure_device(struct controller *ctrl);
169 void pciehp_unconfigure_device(struct controller *ctrl, bool presence);
171 struct controller *pcie_init(struct pcie_device *dev);
172 int pcie_init_notification(struct controller *ctrl);
173 void pcie_shutdown_notification(struct controller *ctrl);
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/drivers/pci/controller/dwc/
DKconfig18 bool "Amazon Annapurna Labs PCIe controller"
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
36 Say Y here if you want to enable PCI controller support on Amlogic
37 SoCs. The PCI controller on Amlogic is based on DesignWare hardware
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
51 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
55 bool "Axis ARTPEC-6 PCIe controller (endpoint mode)"
61 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
[all …]
/drivers/pci/controller/
DKconfig3 menu "PCI controller drivers"
7 tristate "Aardvark PCIe controller"
14 controller is part of the South Bridge of the Marvel Armada
18 tristate "Altera PCIe controller"
21 Say Y here if you want to enable PCIe controller support on Altera
30 This MSI driver supports Altera MSI to GIC controller IP.
38 tristate "Apple PCIe controller"
44 Say Y here if you want to enable PCIe controller support on Apple
51 bool "ARM Versatile PB PCI controller"
55 tristate "Broadcom Brcmstb PCIe controller"
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/drivers/mtd/nand/raw/
DKconfig19 tristate "Denali NAND controller on Intel Moorestown"
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
32 controller as a DT device.
35 tristate "Amstrad E3 NAND controller"
42 tristate "OMAP2, OMAP3, OMAP4 and Keystone NAND controller"
69 This enables the driver for the NAND flash controller on the
73 tristate "IBM/MCC 4xx NAND controller"
81 tristate "Samsung S3C NAND controller"
84 This enables the NAND flash controller on the S3C24xx and S3C64xx
[all …]
Dcs553x_nand.c98 to_cs553x(struct nand_controller *controller) in to_cs553x() argument
100 return container_of(controller, struct cs553x_nand_controller, base); in to_cs553x()
196 struct cs553x_nand_controller *cs553x = to_cs553x(this->controller); in cs553x_exec_op()
219 struct cs553x_nand_controller *cs553x = to_cs553x(this->controller); in cs_enable_hwecc()
227 struct cs553x_nand_controller *cs553x = to_cs553x(this->controller); in cs_calculate_ecc()
262 struct cs553x_nand_controller *controller; in cs553x_init_one() local
276 controller = kzalloc(sizeof(*controller), GFP_KERNEL); in cs553x_init_one()
277 if (!controller) { in cs553x_init_one()
282 this = &controller->chip; in cs553x_init_one()
283 nand_controller_init(&controller->base); in cs553x_init_one()
[all …]
/drivers/mtd/nand/raw/brcmnand/
DKconfig2 tristate "Broadcom STB NAND controller"
6 Enables the Broadcom NAND controller driver. The controller was
13 tristate "Broadcom BCM63xx NAND controller glue"
16 Enables the BRCMNAND glue driver to register the NAND controller
20 tristate "Broadcom BCMA NAND controller"
24 Enables the BRCMNAND controller over BCMA on BCM47186/BCM5358 SoCs.
26 operations to interface the BRCMNAND controller over the BCMA bus.
29 tristate "Broadcom BCMBCA NAND controller glue"
32 Enables the BRCMNAND glue driver to register the NAND controller
36 tristate "Broadcom STB Nand controller glue"
[all …]
/drivers/usb/host/
Dohci-dbg.c101 ohci_dump_status (struct ohci_hcd *controller, char **next, unsigned *size) in ohci_dump_status() argument
103 struct ohci_regs __iomem *regs = controller->regs; in ohci_dump_status()
106 temp = ohci_readl (controller, &regs->revision) & 0xff; in ohci_dump_status()
107 ohci_dbg_sw (controller, next, size, in ohci_dump_status()
111 rh_state_string(controller)); in ohci_dump_status()
113 temp = ohci_readl (controller, &regs->control); in ohci_dump_status()
114 ohci_dbg_sw (controller, next, size, in ohci_dump_status()
128 temp = ohci_readl (controller, &regs->cmdstatus); in ohci_dump_status()
129 ohci_dbg_sw (controller, next, size, in ohci_dump_status()
138 ohci_dump_intr_mask (controller, "intrstatus", in ohci_dump_status()
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/drivers/clk/samsung/
DKconfig4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
21 Support for the clock controller present on the Samsung S3C64xx SoCs.
25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
28 Support for the clock controller present on the Samsung S5Pv210 SoCs.
32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
35 Support for the clock controller present on the Samsung
39 bool "Samsung Exynos4 clock controller support" if COMPILE_TEST
42 Support for the clock controller present on the Samsung
47 bool "Samsung Exynos5250 clock controller support" if COMPILE_TEST
[all …]
/drivers/clk/rockchip/
DKconfig5 bool "Rockchip clock controller common support"
9 Say y here to enable common clock controller for Rockchip platforms.
13 bool "Rockchip PX30 clock controller support"
20 bool "Rockchip RV110x clock controller support"
27 bool "Rockchip RV1126 clock controller support"
34 bool "Rockchip RK3036 clock controller support"
41 bool "Rockchip RK312x clock controller support"
48 bool "Rockchip RK3188 clock controller support"
55 bool "Rockchip RK322x clock controller support"
62 bool "Rockchip RK3288 clock controller support"
[all …]
/drivers/clk/qcom/
DKconfig27 Support for the camera clock controller on X1E80100 devices.
45 Support for the global clock controller on Qualcomm Technologies, Inc
55 Support for the graphics clock controller on X1E80100 devices.
56 Say Y if you want to support graphics controller devices and
64 Support for the TCSR clock controller on X1E80100 devices.
72 Support for the graphics clock controller on QCM2290 devices.
73 Say Y if you want to support graphics controller devices and
107 Support for the CPU clock controller on msm8996 devices.
159 Support for the global clock controller on apq8084 devices.
169 Support for the multimedia clock controller on apq8084 devices.
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/drivers/mailbox/
Dbcm2835-mailbox.c58 struct mbox_controller controller; member
63 return container_of(link->mbox, struct bcm2835_mbox, controller); in bcm2835_link_mbox()
69 struct device *dev = mbox->controller.dev; in bcm2835_mbox_irq()
70 struct mbox_chan *link = &mbox->controller.chans[0]; in bcm2835_mbox_irq()
87 dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); in bcm2835_send_data()
162 mbox->controller.txdone_poll = true; in bcm2835_mbox_probe()
163 mbox->controller.txpoll_period = 5; in bcm2835_mbox_probe()
164 mbox->controller.ops = &bcm2835_mbox_chan_ops; in bcm2835_mbox_probe()
165 mbox->controller.of_xlate = &bcm2835_mbox_index_xlate; in bcm2835_mbox_probe()
166 mbox->controller.dev = dev; in bcm2835_mbox_probe()
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